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41. 发明公开

EP0039227A3 Data processing system 失效
标题翻译：数据处理系统
公开(公告)号：EP0039227A3
公开(公告)日：1982-09-01
申请号：EP81301836
申请日：1981-04-27
申请人： DATA GENERAL CORPORATION
发明人： Alsing, Carl J. , Coyle, Richard W , Druke, Michael B. , Epstein, David I. , Guyer, James M. , Henry, Carl , Holberger, Kenneth D. , Holland, Charles J. , Keating, David L. , Rasala, Edward , Reilly, Paul , Rosen, Josh , Staudaher, Steven M. , Veres, James E. , Wallach, Steven , West, Thomas , Ziegler, Michael L.
IPC分类号： G11C09/06 , G06F13/00 , G06F09/30 , G06F09/22 , G06F03/04 , G06F11/10
CPC分类号： G06F9/342 , G06F9/261 , G06F9/30145 , G06F9/3017 , G06F9/30174 , G06F9/30181 , G06F9/30189 , G06F9/30196 , G06F11/106 , G06F12/0292 , G06F12/0623 , G06F12/0802 , G06F12/0804 , G06F12/1009 , G06F12/1491
摘要： The system includes a central processor responsive to macroinstructions to produce microcontrol signals to which arithmetic logic unit (11) responds. An instruction processor (12) decodes macroinstructions to produce a starting address for one or more microinstructions. These are decoded by a programmable read only memory capable of decoding instructions of two types, the instruction being decoded containing bit patterns which identify uniquely the instruction type to be decoded. The instructions belong to a first basic instruction set having a logical address space of 2 power 16 bytes or to a second set providing an extended logical address space of 2 power 32 bytes. A microsequencer (13) responds to the starting address to provide a sequence of one or more microinstructions for producing a number of microcontrol signals. An address translation unit (14) responds to selected ones of the microcontrol signals to convert logical addresses into physical addresses. The systems main memory (16) stores information for use in the system in one to eight memory modules providing 2-4 megabytes of main memory in several memory plans e.g four planes of 16K 39-bit words in each module. A bank controller (18) controls the transfer of information between the main memory and a temporary storage device provided by a cache unit (17) having two ports to interface with the main memory. A central processor address bus (19) and a control processor memory bus (20) permit the transfer of addresses among the instruction processor (12), address translator (14) and the memory system and the transfer of instructions and operands among the arithmetic logic (11), processor (12), translator (14) and memory system (15).

42. 发明公开

EP0035334A3 Data processing system with two level microprogramming and frequency synthesisers 有权
标题翻译：具有两级微控制和频率合成器的数据处理系统
公开(公告)号：EP0035334A3
公开(公告)日：1981-12-09
申请号：EP81300560
申请日：1981-02-11
申请人： DATA GENERAL CORPORATION
发明人： Bernstein, David H. , Carberry, Richard A. , Druke, Michael B. , Gusowski, Ronald I. , Buckley, Edward M. , March, Roger W.
IPC分类号： G06F09/26 , G06F03/04 , H03K05/156
CPC分类号： H03K23/667 , G06F9/26 , G06F9/268 , G06F13/22 , G06F13/36 , G06F13/4027 , G06F13/42 , G06F13/4217
摘要： The central processing unit of a data processing system employs a decoder 40 to decode macroinstructions held in an instruction register 19 under the control of a program counter 20. Each decoded macroinstruction provides a sequence of first microinstructions on an 18-bit bus 39. Each first microinstruction comprises a 4-bit address field applied to a sequencer 33 which also receives bits from the decoder 40 and addresses a ROM 31 which provides the first microinstructions. A 6-bit field of each first microinstruction addresses another ROM 32 which provides one of 64 second microinstructions of 33 bits each, HORM O-32. Fields of the second microinstructions are modified in accordance with two 4-bit modifier fields V1 and V2 from the first microinstruction in a modification circuit 34 which provides 35-bit output microinstructions HCOMT 0-34. These output microinstructions are applied to a decoder 35 whose outputs control the machine states of the CPU. A system bustiming system and a frequency synthesizer are also provided.
摘要翻译：数据处理系统的中央处理单元采用解码器40在程序计数器20的控制下解码保存在指令寄存器19中的宏指令。每个解码的宏指令在18位总线39上提供一系列第一微指令。微指令包括应用于定序器33的4位地址字段，其也从解码器40接收位，并寻址提供第一微指令的ROM 31。每个第一微指令的6位字段寻址另一个ROM 32，其提供64位每个33位的第二微指令之一，HORM O-32。根据提供35位输出微指令HCOMT 0-34的修改电路34，根据来自第一微指令的两个4位修改器字段V1和V2修改第二微指令的字段。这些输出微指令被应用于其输出控制CPU的机器状态的解码器35。还提供了系统稳定系统和频率合成器。

43. 发明授权

EP0938705B1 FAIL-OVER SWITCHING SYSTEM 失效
标题翻译：切换系统的安全转移
公开(公告)号：EP0938705B1
公开(公告)日：2002-09-11
申请号：EP97910942.8
申请日：1997-10-08
申请人： DATA GENERAL CORPORATION
发明人： ESPY, James, W. , BLEIWESS, Scott , SOLOMON, Robert, C. , BAILEY, Brian, K. , EVERDELL, Peter
IPC分类号： G06F11/20
CPC分类号： G06F11/2094 , G06F11/201 , G06F11/2089
摘要： A fail-over switch (100, 102) for use in a data storage system that connects each of a plurality of data storage devices (112) to each of two communication paths (126, 128). The switch (100, 102) may route requests to either of the two communication paths (126, 128). Switching may be accomplished by two switches (100, 102) connected to each other and each in connection with one of the two communication paths (126, 128). With one data storage controller (90) in communication with the data storage devices (112) over a first path (126) and a second data storage controller (92) in communication with the data storage devices (112) over a second path (128), the fail-over switch (100, 102) may be used upon detection of a malfunction on one path to switch a controller into connection with the remaining operable path so as to share that path with the other controller.

44. 发明公开

EP0983548A1 APPARATUS AND METHOD FOR BACKUP OF A DISK STORAGE SYSTEM 失效
标题翻译：装置和方法用于保护的磁盘存储系统的
公开(公告)号：EP0983548A1
公开(公告)日：2000-03-08
申请号：EP98923431.5
申请日：1998-05-14
申请人： DATA GENERAL CORPORATION
发明人： CLIFTON, Richard, J. , CHATTERJEE, Sanjoy , LARSON, John, P. , RICHART, Joseph, R. , SAGAN, Cyril, E.
IPC分类号： G06F11/14
CPC分类号： G06F11/1466
摘要： A backup system and method provides for creation of a reconciled snapshot backup image of a database while the database, residing on a disk array system, is in use by users. A backup computer running a commercial backup utility is connected between the array system and a tape storage system. While the backup is underway, write requests to the database are suspended until the data currently in those data blocks is copied and stored in an original data cache. The disk system address of the copied block and a pointer to the location of the block in the cache are stored in a map. The backup utility incrementally reads portions of the database from the disk system and forwards those portions to the tape system. Prior to each portion being forwarded to the tape system, all data blocks in the portion which have an address that corresponds to the address of a block in the cache are discarded and replaced with the data from the cache for that address.

45. 发明授权

EP0616278B1 Synchronous gated clock generator 失效
标题翻译：同步切换时钟
公开(公告)号：EP0616278B1
公开(公告)日：1999-09-29
申请号：EP94301564.4
申请日：1994-03-04
申请人： DATA GENERAL CORPORATION
发明人： Frangioso, Ralph C., Jr. , Rebello, Paul , Dunbar, Joseph Michael
IPC分类号： G06F1/04
CPC分类号： G06F1/04

46. 发明公开

EP0938704A1 HIGH PERFORMANCE DATA PATH WITH XOR ON THE FLY 失效
标题翻译：高性能数据和即时XOR
公开(公告)号：EP0938704A1
公开(公告)日：1999-09-01
申请号：EP97910943.0
申请日：1997-10-08
申请人： DATA GENERAL CORPORATION
发明人： SOLOMON, Robert, C. , BAILEY, Brian, K. , YATES, Robert , EVERDELL, Peter , REEVES, Elizabeth, H.
IPC分类号： G06F3 , G06F11
CPC分类号： G06F11/1076 , G06F2211/1054
摘要： A high performance data path for performing XOR on the fly. A first memory is connected to a first bus and a second memory is connected to a second bus selectively coupled to the first bus. Logic for performing an XOR can be switched into connection with the first and second bus for XORing data in a buffer with the data passed from one of the memories to the other memory. The result is replaced into the buffer to permit successive XORing. When reading from an interrelated group of disks such as a RAID 3 group, the data path permits an N-1 and go mode in which a read does not wait for data from the last disk to retrieve its data sector. If the last disk contains data (as opposed to parity) the data is obtained from the XORed data in the XOR buffer of the high performance data path. For writing data, the XOR on the fly generates the parity sector for writing at the completion of a write to an interrelated group of disks.

47. 发明公开

EP0883845A1 DYNAMICALLY UPGRADEABLE DISK ARRAY SYSTEM AND ORTHOGONAL SIGNAL MULTIPLEXING SYSTEM THEREFOR 失效
标题翻译：动态扩展的磁盘阵列系统及其正交信号复用系统，
公开(公告)号：EP0883845A1
公开(公告)日：1998-12-16
申请号：EP97907877.0
申请日：1997-02-25
申请人： DATA GENERAL CORPORATION
发明人： ESPY, James, W. , BLEIWEISS, Scott, J. , HAWKINS, Thomas, B. , BROWN, Jeffrey, A.
IPC分类号： G06F13 , G06F3 , G06F11 , G06F12 , H04L5
CPC分类号： G06F11/3058 , G06F11/3034 , G06F11/3041 , G06F11/3051 , G06F11/3055 , G06F13/409 , H04L5/20
摘要： A dynamically upgradeable disk array chassis (10), a method for dynamically upgrading a data storage system, diplexed computer communications and a diplexer (50) wherein the diplexer (50) and the diplexed communications may be used in the dynamically upgradeable disk array chassis (10). The dynamically upgradeable disk array chassis (10) includes a serial bus (22) having a first bus for passing data in one direction and a second bus (24) for passing data in the opposite direction. A shunt (40) connects the first (22) and second (24) buses in a normal state. The shunt (40) has a switched state in which each of the first and second buses is coupled to a separate output from the chassis. The chassis (10) includes an environmental monitor (30) connected to a communication path (42). Upon connecting a new disk array chassis to an active disk array chassis, the environmental monitor (30) communicates through the communication path (42) before switching the shunt (40) to connect the serial bus with the serial bus of the new disk array chassis. The disk array chassis (10) may include a diplexer (50) for connecting the communication path (42) to the separate outputs of the shunt (40) and for combining the communicaton path signals with the serial path signals in one direction and for separating these signals in the other direction. The diplexer (50) may include an adder for adding the signals from the communication path with those on the serial path and a subtractor for subtracting signals of one path from the other. The environmental monitor path communications and the serial bus communications can take place over a single twinax cable (18). One signal is differentially coupled onto a first pair of conductors. A second signal is common mode coupled onto the first pair of conductors. In the opposite direction on the twinax cable (18), different signals are also differentially coupled and common mode coupled to the return pair of conductors.

48. 发明授权

EP0559488B1 Handling data in a system having a processor for controlling access to a plurality of data storage disks 失效
标题翻译：在具有用于控制多个数据存储磁盘的访问处理器的系统的数据管理
公开(公告)号：EP0559488B1
公开(公告)日：1998-08-19
申请号：EP93301686.7
申请日：1993-03-05
申请人： DATA GENERAL CORPORATION
发明人： Solomon, Robert C. , Todd, Stephen J. , Pendleton, Samuel S. , Lippit, Mark C.
IPC分类号： G06F11/00 , G06F11/10 , G06F11/14
CPC分类号： G06F11/1084
摘要： A method for handling data in a plurality of data storage disks (27) having user data sectors and corresponding parity sectors, the method being used when the disks are being operated in a non-degraded or a degraded mode wherein a non-volatile RAM (28) is used in an array control processor (25) which controls the operation of such disks. When new data is to be written into the array, the non-volatile RAM stores information identifying the array, the starting sector into which data is to be written and the number of sectors to be used for writing the new data so that parity and data entries in corresponding sectors can be matched when a power failure occurs. Further, when opening a new array, the data and parity entries in corresponding sectors can be matched and verified, the operation for such matching being peformed in between other operations that are being performed by the control processors (i.e., in the "background" thereof).

49. 发明公开

EP0768594A1 Computer system security 失效
标题翻译： Rechnersystemsicherheit
公开(公告)号：EP0768594A1
公开(公告)日：1997-04-16
申请号：EP96307368.9
申请日：1996-10-10
申请人： DATA GENERAL CORPORATION
发明人： Hayman, Kenneth John , Lewine, Eric Scott , Keene, Michael Donovan , Meyers, William James , Spencer, Jon Frederick , Taylor, Millard Cranford, II
IPC分类号： G06F1/00
CPC分类号： G06F21/31 , G06F2221/2113 , Y10S707/99931
摘要： A security system for a computer system imposes specific limitations on who has access to the computer system and to exactly what operations and data. Viruses are securely contained and prevented from expanding into areas where they can destroy stored programs or data. Viruses are also prevented from being introduced or executed in a large number of instances. The totality of computer functions is broken up into a set of events with an associated set of capabilities and different capabilities are assigned to each user depending on the particular job which that user is to do on the computer system. Also, security labels are placed on each data file and other system resources, and on each process. Further, a range of hierarchy/category labels (MAC labels) is assigned to each process to define a sub-lattice in which special capabilities can apply. Further, the hierarchy of labels is divided into a small number (for example 3) of regions, and a process operating in one region is generally not allowed to cross over into another region. Further an owner of a data file is allowed to place restrictions on the file so that only users who posses certain privileges can gain access to the file.
摘要翻译：计算机系统的安全系统对谁拥有计算机系统的访问权以及准确的操作和数据施加了特定的限制。病毒被安全地包含并阻止扩展到可以销毁存储的程序或数据的区域。病毒也被阻止在许多情况下引入或执行。计算机功能的整体被分解成具有相关联的能力集合的一组事件，并且根据用户在计算机系统上要做的具体工作，将不同的功能分配给每个用户。此外，安全标签放置在每个数据文件和其他系统资源以及每个进程上。此外，分配/分类标签（MAC标签）的范围被分配给每个进程以定义可应用特殊能力的子格。此外，标签的层次被划分为少数（例如3个）区域，并且在一个区域中操作的处理通常不允许跨越到另一个区域。此外，数据文件的所有者可以对文件进行限制，以便只有具有某些权限的用户可以访问该文件。

50. 发明公开

EP0750255A2 Operating system for a non-uniform memory access multiprocessor system 失效
标题翻译： Betriebssystemfürein Mehrfachrechnersystem mitungleichmässigemSpeicherzugriff
公开(公告)号：EP0750255A2
公开(公告)日：1996-12-27
申请号：EP96304598.4
申请日：1996-06-20
申请人： DATA GENERAL CORPORATION
发明人： Kimmel, Jeffrey S. , Alfieri, Robert A. , De Forest, Miles A. , McGrath, William K. , McLeod, Michael J. , O'Connell, Mark A. , Simpson, Guy A.
IPC分类号： G06F9/46 , G06F15/16
CPC分类号： G06F9/5083 , G06F9/5016
摘要： An operating system for a non-uniform memory access (NUMA) multiprocessor system that utilizes a software abstraction of the NUMA system hardware representing a hierarchical tree structure to maintain the most efficient level of affinity and to maintain balanced processor and memory loads. The hierarchical tree structure includes leaf nodes representing the job processors, a root node representing at least one system resource shared by all the job processors, and a plurality of intermediate level nodes representing resources shared by different combinations of the job processors. The operating system includes a medium term scheduler for monitoring the progress of active thread groups distributed throughout the system and for assisting languishing thread groups, and a plurality of dispatchers each associated with one of the job processors for monitoring the status of the associated job processor and for obtaining thread groups for the associated job processor to execute. The operating system further includes a memory manager for allocating virtual and physical memory using a plurality of memory pools and frame treasuries.
摘要翻译：用于非均匀存储器访问（NUMA）多处理器系统的操作系统，其利用表示层次树结构的NUMA系统硬件的软件抽象来维持最有效的亲和度水平并维持平衡的处理器和存储器负载。分层树结构包括表示作业处理器的叶节点，表示所有作业处理器共享的至少一个系统资源的根节点和表示由作业处理器的不同组合共享的资源的多个中间级节点。所述操作系统包括中期计划器，用于监视分布在整个系统中的主动线程组的进度并用于帮助线程组，以及多个调度器，每个调度器与作业处理器之一相关联，用于监视相关联的作业处理器的状态，用于获取相关作业处理器执行的线程组。操作系统还包括存储器管理器，用于使用多个存储器池和帧库来分配虚拟和物理存储器。

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