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31. 发明公开

EP1903611A2 Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：EP1903611A2
公开(公告)日：2008-03-26
申请号：EP07116351.3
申请日：2007-09-13
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD
发明人： Kudo, Chiaki Matsushita Electric Ind. Co., Ltd. , Ogawa, Hisashi Matsushita Electric Industrial Co., Ltd.
IPC分类号： H01L29/423 , H01L21/28 , H01L21/8238 , H01L21/768
CPC分类号： H01L29/42376 , H01L21/28123 , H01L21/823456 , H01L21/82385 , H01L27/0207 , H01L29/4238
摘要： A semiconductor device includes: an isolation region formed in a semiconductor substrate; an active region surrounded by the isolation region; and a first gate electrode formed on the isolation region and the active region and including a first region on the isolation region. The first region has a pattern width in a gate length direction larger than a pattern width of the first gate electrode on the active region. The first region includes a part having a film thickness different from a film thickness of the first gate electrode on the active region.
摘要翻译：一种半导体器件包括：形成在半导体衬底中的隔离区; 由隔离区域包围的有源区域; 以及第一栅电极，形成在隔离区和有源区上并且在隔离区上包括第一区。第一区域在栅极长度方向上的图案宽度大于有源区域上的第一栅极电极的图案宽度。第一区域包括具有与有源区上的第一栅电极的膜厚不同的膜厚度的部分。

32. 发明公开

EP1801858A1 Method for gate electrode height control 审中-公开
标题翻译：一种用于在栅电极的高度控制处理
公开(公告)号：EP1801858A1
公开(公告)日：2007-06-27
申请号：EP06126715.9
申请日：2006-12-20
申请人： INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM vzw (IMEC)
发明人： Veloso, Anabela
IPC分类号： H01L21/28 , H01L21/336
CPC分类号： H01L21/28097 , H01L21/28052 , H01L21/823443 , H01L21/823456 , H01L21/823835 , H01L21/82385 , H01L29/66507 , H01L29/66545
摘要： The present invention relates to a method for controlling the gate electrode in a silicidation process, comprising the steps of:
- applying a sacrificial cap layer (18) on top of each of at least one gate electrode (13), each of the at least one gate electrode deposited with a given height on a semiconductor substrate (10),
- applying an additional layer of oxide (14) on top of said sacrificial layer
- covering with a material (17) said semiconductor substrate (10) provided with said at least one gate electrode (13) having said sacrificial cap layer (18) with said additional oxide layer (14) on top,
- performing a CMP planarisation step,
- removing at least said material (17) and said additional layer of oxide (14) until on top of each of the at least one gate electrode (13) the sacrificial cap layer (18) is exposed,
- removing the sacrificial cap layer (18) from each of the at least one gate electrode (13), yielding each of the at least one gate electrode (13) still having the given height.

33. 发明公开

EP1290498A1 PROCEDE DE CREATION D'UN ETAGE DE CIRCUIT INTEGRE OU COEXISTENT DES MOTIFS FINS ET LARGES 有权
标题翻译：方法用于制造集成电路的层精细和广泛的结构
公开(公告)号：EP1290498A1
公开(公告)日：2003-03-12
申请号：EP01945431.3
申请日：2001-06-14
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE
发明人： DELEONIBUS, Simon
IPC分类号： G03F7/00
CPC分类号： H01L21/823456 , H01L21/0274 , H01L21/0277 , H01L21/823437 , Y10S438/95
摘要： The invention concerns a method which consists in successively using a radiation-sensitive resin layer at sites (4') designed to form large semiconductor patterns in a still intact layer (2), beneath at least a hard mask (3'), then a resin layer sensitive to particle bombardment (6) above the fine patterns to be formed in that same layer (2) which can be juxtaposed with the former. The first resin patterns are collectively and rapidly exposed by an exposure, while the electron bombardment enables to form fine patterns with great accuracy. Another hard mask (9) has been deposited before (6) the second resin (6) and forms flanks (10) around the large patterns, protecting them from lateral attacks during etching.

34. 发明公开

EP1225626A2 Semiconductor integrated circuit device and manufacture method therefor 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：EP1225626A2
公开(公告)日：2002-07-24
申请号：EP02250304.9
申请日：2002-01-16
申请人： FUJI ELECTRIC CO., LTD.
发明人： Kitamura, Akio
IPC分类号： H01L21/8234
CPC分类号： H01L21/8249 , H01L21/761 , H01L21/823412 , H01L21/823456 , H01L21/823493 , H01L27/0635
摘要： The object of the present invention is to mount a submicron CMOS transistor on the same substrate together with an analog CMOS transistor, a high voltage-resistance MOS transistor, a bipolar transistor, a diode, or a diffusion resistor, without degrading the characteristics of these components.
When a punch-through stopper area is formed on a main surface side of a semiconductor substrate 1, an area in which an analog CMOS transistor, a high voltage-resistance MOS transistor, a bipolar transistor, a diode, or a diffusion resistor is formed is masked, and for example, an ion injection is then carried out. Thus, a punch-through stopper area 4 is formed in the area in which a submicron CMOS transistor is formed, while preventing the formation of a punch-through stopper area in the area in which an analog CMOS transistor, a high voltage-resistance MOS transistor, a bipolar transistor, a diode, or a diffusion resistor is formed.
摘要翻译：本发明的目的是在不降低这些特性的情况下将亚微米CMOS晶体管与模拟CMOS晶体管，高耐压MOS晶体管，双极晶体管，二极管或扩散电阻器一起安装在同一衬底上组件。当在半导体衬底1的主表面侧上形成穿通阻止区域时，形成模拟CMOS晶体管，高耐压MOS晶体管，双极晶体管，二极管或扩散电阻器的区域被遮蔽，然后例如进行离子注入。因此，在形成亚微米CMOS晶体管的区域中形成穿通阻止区域4，同时防止在模拟CMOS晶体管，高电压电阻MOS的区域中形成穿通阻止区域晶体管，双极晶体管，二极管或扩散电阻器。

35. 发明公开

EP0832498A1 METHOD OF MANUFACTURING A PIC (POWER INTEGRATED CIRCUIT) DEVICE, AND A PIC DEVICE MANUFACTURED BY SUCH A METHOD 失效
标题翻译：过程中的集成电源电路
公开(公告)号：EP0832498A1
公开(公告)日：1998-04-01
申请号：EP97901235.0
申请日：1997-02-13
申请人： PHILIPS ELECTRONICS N.V.
发明人： LUDIKHUIZE, Adrianus Willem , VAN DORT, Maarten
IPC分类号： H01L21 , H01L27 , H01L29
CPC分类号： H01L29/0852 , H01L21/26586 , H01L21/823412 , H01L21/823456 , H01L21/823462 , H01L27/0922 , H01L29/0847 , H01L29/1095 , H01L29/42368 , H01L29/66681 , H01L29/7816
摘要： A deep diffusion of the back-gate region provided in a self-aligned manner with respect to the gate electrode is necessary in a DMOS transistor for obtaining a sufficiently high punch-through voltage between source and drain. The combination of a comparatively heavy back-gate implantation and a light source implantation and a heavy source implantation with spacer on the gate electrode, and the use of interstitial diffusion and accelerated diffusion owing to crystal damage render it possible to carry out said diffusion of the back-gate region at a comparatively low temperature, for example below 950 DEG C. This renders it possible to integrate a DMOST into, for example, standard VLSI CMOS where first delta Vth and channel-profile implantations are carried out, and subsequently the poly gates are provided, which means that a diffusion step at a temperature above 1,000 DEG C. of long duration is no longer allowed. The effect may be enhanced in that the doping of the back-gate region is increased during the p-type LDD implantation of a p-channel MOS and/or the p-type well implantation of an n-channel MOS.

36. 发明授权

EP0452817B1 Semiconductor device with MOS-transistors and method of manufacturing the same 失效
标题翻译：一种半导体器件，包括MOS晶体管和它的制备方法。
公开(公告)号：EP0452817B1
公开(公告)日：1995-10-11
申请号：EP91105804.8
申请日：1991-04-11
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Sawada, Shizuo, c/o Intellectual Property Division , Iwasaki, Seiko, c/o Intellectual Property Division
IPC分类号： H01L29/10 , H01L21/266
CPC分类号： H01L29/66575 , H01L21/266 , H01L21/823456 , H01L29/1041 , H01L29/1045

37. 发明公开

EP0452817A1 Semiconductor device with MOS-transistors and method of manufacturing the same 失效
标题翻译： Halbleiterbauelement mit MOS-Transistoren und Verfahren zu dessen Herstellung。
公开(公告)号：EP0452817A1
公开(公告)日：1991-10-23
申请号：EP91105804.8
申请日：1991-04-11
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Sawada, Shizuo, c/o Intellectual Property Division , Iwasaki, Seiko, c/o Intellectual Property Division
IPC分类号： H01L29/10 , H01L21/266
CPC分类号： H01L29/66575 , H01L21/266 , H01L21/823456 , H01L29/1041 , H01L29/1045
摘要： The present invention provides a semiconductor device having a well (25), formed in a semiconductor substrate by using a mask in which a mask pattern width of a portion corresponding to an opening diameter is equal to or less than twice the diffusion depth of the well layer, and a gate electrode (27) formed to have the well layer as a channel region of a MOS transistor. The well formed in this manner has a substantially semi-circular section to facilitate impurity concentration control in the substrate surface. When a plurality of types of opening patterns having small pattern widths are formed in a single mask, MOS transistors having different threshold voltages can be formed in a single process.
摘要翻译：本发明提供了一种具有阱（25）的半导体器件，其通过使用其中与开口直径相对应的部分的掩模图案宽度等于或小于阱的扩散深度的两倍的掩模形成在半导体衬底中以及形成为具有作为MOS晶体管的沟道区的阱层的栅电极（27）。以这种方式形成的阱具有基本上半圆形的部分，以促进衬底表面中的杂质浓度控制。当在单个掩模中形成具有小图案宽度的多种类型的开口图案时，可以在单个工艺中形成具有不同阈值电压的MOS晶体管。

38. 发明公开

EP0437939A1 Integratable DMOS transistor and method of making the same 失效
标题翻译： Integrierbarer DMOS-Transistor和Verfahren zu dessen Herstellung。
公开(公告)号：EP0437939A1
公开(公告)日：1991-07-24
申请号：EP90313365.0
申请日：1990-12-10
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Todd, James R. , Efland, Taylor R. , Jones, Roy C., III , Cotton, David R. , Lee, John K.
IPC分类号： H01L29/784 , H01L27/07 , H01L21/82 , H01L27/06
CPC分类号： H01L29/7802 , H01L21/823456 , H01L21/8249 , H01L27/0255 , H01L27/0623 , H01L29/66712 , H01L29/7808 , H01L29/7809
摘要： Methods and circuits of integrated DMOS, CMOS, NPN, and PNP devices include self-aligned DMOS (411) with increased breakdown voltage and ruggedness for recovery from transients including additional Zener diodes (402/474).
摘要翻译：集成DMOS，CMOS，NPN和PNP器件的方法和电路包括具有增加的击穿电压的自对准DMOS（411）和用于从包括额外的齐纳二极管（402/474）的瞬态恢复的耐用性。

39. 发明公开

EP0083783A3 Fabrication method for integrated circuit structures including field effect transistors of sub-micrometer gate length, and integrated circuit structure fabricated by this method 失效
标题翻译：用于集成电路结构的制造方法，包括副微机栅长度的场效应晶体管和本方法制成的集成电路结构
公开(公告)号：EP0083783A3
公开(公告)日：1985-01-23
申请号：EP82111970
申请日：1982-12-27
申请人： International Business Machines Corporation
发明人： de la Moneda, Francisco Homero , Dockerty, Robert Charles
IPC分类号： H01L21/82 , H01L21/76 , H01L27/08
CPC分类号： H01L21/76216 , H01L21/28132 , H01L21/823456 , H01L27/088 , Y10S438/947
摘要： For forming field effect transistors, a multilayer structure (16, 20, 21, 22, 24, 26) of different materials including a conductive layer (20) is deposited over a substrate (10). Vertical sidewalls are obtained by etching the top layers (24, 26) and a sidewall layer (30) is formed by oxidizing the sidewalls. Removing further material leaves the very fine structure of sidewall layers, which is used as a mask to etch the lower layers (22, 21, 20) so as to leave portions of the conductive layer as very fine gate electrodes, plus interconnections. Some gate electrodes of larger dimension are obtained simultaneously by covering the area between two stripes of the sidewall layer before etching down to the conductive layer.

40. 发明公开

EP0083783A2 Fabrication method for integrated circuit structures including field effect transistors of sub-micrometer gate length, and integrated circuit structure fabricated by this method 失效
标题翻译：一种用于制备结构为与栅极连接到亚微米的长度和产生由这种方法结构用于集成电路的场效应晶体管的集成电路的过程。
公开(公告)号：EP0083783A2
公开(公告)日：1983-07-20
申请号：EP82111970.8
申请日：1982-12-27
申请人： International Business Machines Corporation
发明人： de la Moneda, Francisco Homero , Dockerty, Robert Charles
IPC分类号： H01L21/82 , H01L21/76 , H01L27/08
CPC分类号： H01L21/76216 , H01L21/28132 , H01L21/823456 , H01L27/088 , Y10S438/947
摘要： For forming field effect transistors, a multilayer structure (16, 20, 21, 22, 24, 26) of different materials including a conductive layer (20) is deposited over a substrate (10). Vertical sidewalls are obtained by etching the top layers (24, 26) and a sidewall layer (30) is formed by oxidizing the sidewalls. Removing further material leaves the very fine structure of sidewall layers, which is used as a mask to etch the lower layers (22, 21, 20) so as to leave portions of the conductive layer as very fine gate electrodes, plus interconnections. Some gate electrodes of larger dimension are obtained simultaneously by covering the area between two stripes of the sidewall layer before etching down to the conductive layer.
摘要翻译：用于形成场效应晶体管，多层结构（16，20，21，22，24，26）包括导电层（20）不同的材料沉积在衬底（10）。垂直侧壁通过蚀刻顶层（24，26）和一个侧壁层（30）通过氧化侧壁形成得到。去除另外的材料离开所述非常细的结构侧壁层的，所有这一切都被用作掩模来蚀刻下层（22，21，20），以便离开导电层的部分作为非常细的栅电极，以及互连。较大尺寸的一些栅电极向下蚀刻到导电层之前由覆盖侧壁层的两个条之间的区域同时获得。

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