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21. 发明公开

EP3012975A1 ERROR RESILIENT DIGITAL SIGNAL PROCESSING DEVICE 有权
标题翻译： FEHLERFESTE DIGITALIGIGIGITUGSVORRICHTUNG
公开(公告)号：EP3012975A1
公开(公告)日：2016-04-27
申请号：EP15190088.3
申请日：2015-10-16
申请人： IMEC VZW , Katholieke Universiteit Leuven
发明人： HUANG, Yanxiang , LI, Meng , LI, Chunshu
IPC分类号： H03K3/037
CPC分类号： G06F17/5081 , G06F17/5045 , H03K3/0375
摘要： The present invention relates to an error resilient scheme for a signal processing device (100) arranged for performing an iterative processing on a clocked input data (Q) and for outputting an output data (O), the signal processing device (100) comprising: a computation circuit (20) comprising at least one computation unit circuit (21) arranged for performing one computation in each iteration on said clocked input data (Q) and for outputting a processed data (C1), and a selection circuit (30) arranged for outputting as said output signal (O) either said processed data (C1) or said clocked input data (Q), depending on a control signal (Ctrl) representative of a set-up timing error detected in an input data (D).
摘要翻译：本发明涉及一种用于信号处理设备（100）的错误弹性方案，该信号处理设备（100）被布置为对时钟输入数据（Q）执行迭代处理并输出输出数据（O），所述信号处理设备（100）包括：一种计算电路（20），包括：至少一个计算单元电路（21），用于在所述时钟输入数据（Q）上的每个迭代中进行一次计算，并输出处理数据（C1）;以及选择电路（30）用于根据表示在输入数据（D）中检测到的建立定时错误的控制信号（Ctrl），输出作为所述处理数据（C1）或所述时钟输入数据（Q）的所述输出信号（O）。

22. 发明公开

EP2965424A1 LOW LEAKAGE RETENTION REGISTER TRAY 审中-公开
标题翻译： STREUFELDARME REGISTERSCHALE
公开(公告)号：EP2965424A1
公开(公告)日：2016-01-13
申请号：EP14709162.3
申请日：2014-02-26
申请人： Qualcomm Incorporated
发明人： VILANGUDIPITCHAI, Ramaprasath , PATEL, Prayag Bhanubhai
IPC分类号： H03K3/356 , H03K3/037 , G06F1/32 , H03K19/00
CPC分类号： H03K3/012 , G06F1/32 , H03K3/57 , H03K19/0016
摘要： A particular method includes receiving a retention signal (nret). In response to receiving the retention signal, the method includes retaining state information (q internal, 310) in a non-volatile stage (302) of a retention register (300) and reducing power to a volatile stage (356) of the retention register. The non-volatile stage (302) may be powered by an external voltage source (Vdd ext). The volatile stage may be powered by an internal voltage source (Vddx).

23. 发明公开

EP2738941A1 Semiconductor device 审中-公开
标题翻译： Halbleiterbauelement
公开(公告)号：EP2738941A1
公开(公告)日：2014-06-04
申请号：EP13190845.1
申请日：2013-10-30
申请人： Renesas Electronics Corporation
发明人： Ito, Kazuyuki , Shirota, Hiroshi
IPC分类号： H03K3/037 , G01R31/317
CPC分类号： H03K3/0375 , G01R31/27 , G01R31/2832 , G01R31/31703 , G01R31/31725
摘要： If an exclusive OR circuit itself, a component of a signal delay detecting circuit, has failed to operate properly, a signal delay cannot be detected accurately. A malfunction pre-detecting circuit (12) includes a delay circuit (DL) to delay input data that is input in parallel to a data input terminal of a second flip-flop (FF1) provided in a subsequent stage of a first flip-flop (FF0), a third flip-flop (FFT) that receives output of the delay circuit (DL), and a comparator (CMP) that compares output of the second flip-flop (FF1) and output of the third flip-flop (FFT). First test data (tv1) and second test data (tv2) are input to the malfunction pre-detecting circuit (12) in an operation test mode for testing operation of the malfunction pre-detecting circuit (12). The test data (tv2) is input to the delay circuit (DL). The comparator (CMP) compares the test data (tv1) and output of the flip-flop (FFT) in the operation test mode.
摘要翻译：如果异或电路本身是信号延迟检测电路的分量，则无法正常工作，则无法准确检测信号延迟。故障预检测电路（12）包括延迟电路（DL），延迟与第一触发器的后续级中提供的第二触发器（FF1）的数据输入端并行输入的输入数据（FF0），接收延迟电路（DL）的输出的第三触发器（FFT），以及比较器（CMP），其比较第二触发器（FF1）的输出和第三触发器 FFT）。在用于测试故障预检测电路（12）的操作的操作测试模式下，将第一测试数据（tv1）和第二测试数据（tv2）输入到故障预检电路（12）。测试数据（tv2）被输入到延迟电路（DL）。比较器（CMP）在操作测试模式下比较测试数据（tv1）和触发器（FFT）的输出。

24. 发明授权

EP1533901B1 CMOS circuits with protection for a single event upset 有权
标题翻译： CMOS电离辐射与单保护电路从命中
公开(公告)号：EP1533901B1
公开(公告)日：2014-05-07
申请号：EP05000654.3
申请日：2003-03-03
申请人： Japan Aerospace Exploration Agency
发明人： Matsuda, Sumio, c/o Tsukuba Space Center , Kuboyama, Satoshi, c/o Tsukuba Space Center , Deguchi, Yasushi, c/o Tsukuba Space Center
IPC分类号： H03K19/003 , H03K3/037 , H01L27/02 , H01L27/11
CPC分类号： G11C11/4125 , H01L27/0207 , H01L27/11 , H01L27/1104 , H03K3/0375 , H03K17/08142 , H03K19/00338 , Y10S257/903

25. 发明公开

EP2538319A1 Non-volatile data processing apparatus and image forming apparatus 审中-公开
标题翻译： NichtflüchtigeDatenverarbeitungsvorrichtung und Bilderzeugungsvorrichtung
公开(公告)号：EP2538319A1
公开(公告)日：2012-12-26
申请号：EP11192739.8
申请日：2011-12-09
申请人： Fuji Xerox Co., Ltd.
发明人： Kikuta, Masayoshi , Murata, Yuji , Ikeda, Shinho , Sakamaki, Tadamasa , Liu, Binhui , Hata, Tadashi , Kasahara, Shunsuke , Hayashi, Terutake , Yamamoto, Hiroaki , Kawashita, Masakazu , Yamasaki, Hideki , Bando, Yoshifumi
IPC分类号： G06F9/30 , G06F1/24 , G06F9/44 , H03K3/037 , H03K19/20
CPC分类号： G06F9/30116 , G06F1/24 , G06F9/30141 , G06F9/4401
摘要： A data processing apparatus includes an operation unit, a writable and readable volatile register, a writable and readable nonvolatile memory, first and second writing units and a write-back unit. The operation unit performs an arithmetic operation and a logical operation. The writable and readable volatile register stores data used in the operations performed by the operation unit. The writable and readable nonvolatile memory stores the data in parallel with the volatile register. The data stored in the nonvolatile memory is the data stored in the volatile register. The first writing unit writes the data in the volatile register. The second writing unit writes the data in the nonvolatile memory in parallel with the first writing unit every time the data is written in the volatile register. The write-back unit writes back the data stored in the nonvolatile memory to the volatile register when a power supply is turned on.
摘要翻译：数据处理装置包括操作单元，可写和可读易失性寄存器，可写和可读非易失性存储器，第一和第二写单元和回写单元。操作单元执行算术运算和逻辑运算。可写和可读易失性寄存器存储由操作单元执行的操作中使用的数据。可写和可读非易失性存储器将数据与易失性寄存器并行存储。存储在非易失性存储器中的数据是存储在易失性寄存器中的数据。第一个写入单元将数据写入易失性寄存器。每当将数据写入易失性寄存器时，第二写入单元将数据与第一写入单元并行地写入非易失性存储器。当电源接通时，写回单元将存储在非易失性存储器中的数据写回到易失性寄存器。

26. 发明公开

EP2241008A1 SYSTEM AND METHOD OF CONDITIONAL CONTROL OF LATCH CIRCUIT DEVICES 有权
标题翻译：系统和方法的锁存电路装置条件控制
公开(公告)号：EP2241008A1
公开(公告)日：2010-10-20
申请号：EP09700763.7
申请日：2009-01-09
申请人： QUALCOMM Incorporated
发明人： RAO, Hari M. , ZHONG, Cheng , CHEN, Zhiqin
IPC分类号： H03K3/037
CPC分类号： H03K3/037
摘要： A circuit device includes a first input to receive a reset control signal and a second input coupled to an output of a latch. The circuit device also includes a logic circuit adapted to conditionally reset the latch based on a state of the output in response to receiving the reset control signal.

27. 发明公开

EP2234272A2 Low-power dual-edge-triggered storage cell with scan test support and clock gating circuit therefor 审中-公开
标题翻译：用扫描测试支持和时钟门电路为此低功耗Doppelflankengetriggerte存储器单元
公开(公告)号：EP2234272A2
公开(公告)日：2010-09-29
申请号：EP09160511.3
申请日：2009-05-18
申请人： Oticon A/S
发明人： Salling, Jakob
IPC分类号： H03K3/012 , H03K3/037
CPC分类号： H03K19/0013 , H03K3/012 , H03K3/037
摘要： A storage cell (1) having a pulse generator (5) and a storage element (6) is proposed. The storage element input (7) is connected to receive a data input signal (DIN). The storage element output (9) is connected to provide a data output signal (DOUT). The storage element (6) is operable in one of a data retention state and a data transfer state in response to a storage control signal (SC) received from the pulse generator (5). The pulse generator (5) is connected to receive a clock signal (CK) with rising and falling clock signal edges (13, 14) and is adapted to provide control pulses (15, 16) in the storage control signal (SC). Each control pulse (15, 16) has a leading edge (17) and a trailing edge (18). The control pulses (15, 16) have a polarity suited to invoke the data transfer state on their leading edges (17). The novel feature is that the pulse generator (5) is adapted to initiate a rising-edge control pulse (15) when receiving a rising clock signal edge (13) and to initiate a falling-edge control pulse (16) when receiving a falling clock signal edge (14). In this way, a dual-edge-triggered flip-flop may be made using only combinatorial logic circuitry and one level- or single-edge-triggered storage element (6). The storage cell (1) has low power consumption, facilitates scan testing and can be used by existing design tools and test equipment.
摘要翻译：具有脉冲发生器（5）和存储元件（6）的一个存储单元（1）的提议。存储元件输入（7）被连接以接收一个数据输入信号（DIN）。存储元件的输出（9）连接，以提供数据输出信号（DOUT）。所述存储元件（6）可操作在数据保持状态，并且响应于存储控制信号（SC）的数据传送状态的一个从脉冲发生器（5）接收。脉冲发生器（5）被连接到具有上升沿和下降沿的时钟信号的边缘（13，14）接收一个时钟信号（CK），并且是angepasst提供在所述存储控制信号（SC）的控制脉冲（15，16）。每个控制脉冲（15，16）具有前缘（17）和后缘（18）。控制脉冲（15，16）具有适于以调用数据传输状态在其前边缘（17）的极性。的新颖特征被做了脉冲发生器（5）是angepasst发起上升沿控制脉冲（15）当接收到一个上升时钟信号边缘（13），并启动下降沿控制脉冲（16）当接收到一个下降时钟信号边缘（14）。以这种方式，一个双边缘触发的触发器可以仅使用组合逻辑电路和一个电平或单边沿触发式存储元件进行（6）。所述存储单元（1）具有低功耗，便于扫描测试，并且可以通过现有的设计工具和测试设备中使用。

28. 发明授权

EP1601102B1 High-speed flip-flop circuit 有权
标题翻译：高速触发器电路
公开(公告)号：EP1601102B1
公开(公告)日：2010-04-21
申请号：EP05251091.4
申请日：2005-02-24
申请人： FUJITSU LIMITED
发明人： Kanda, Kouichi, c/o Fujitsu Limited , Matsubara, Satoshi, c/o Fujitsu LSI Solution Limited
IPC分类号： H03K3/037
CPC分类号： H03K3/356113 , H03K3/012

29. 发明公开

EP2031757A1 Sequential circuit element including a single clocked transistor 审中-公开
标题翻译： Sequentielles Schaltelement mit einem einfachgetakteten晶体管
公开(公告)号：EP2031757A1
公开(公告)日：2009-03-04
申请号：EP08006405.8
申请日：2008-03-31
申请人： Qualcomm Incorporated
发明人： Saint-Laurent, Martin , Baker, Mohammad , Bassett, Paul
IPC分类号： H03K3/037 , G06F9/38
CPC分类号： H03K3/356121 , G06F9/3869
摘要： A method is disclosed that includes propagating data via a first data path (212) of a sequential circuit element (202) in response to a clock signal received at a single clocked transistor (214) of the sequential circuit element (202). The method also includes retaining information related to the data propagated via the first path (212) at a retention circuit element (222) of a second data path (218), where the first data path (212) includes a first transistor (210) that is responsive to an output of the single clocked transistor (214). The first transistor (210) has a higher current flow capacity than a second transistor associated with the second data path.
摘要翻译：公开了一种方法，其包括响应于在顺序电路元件（202）的单个时钟控制晶体管（214）处接收的时钟信号，经由时序电路元件（202）的第一数据路径（212）传播数据。该方法还包括保持与在第二数据路径（218）的保持电路元件（222）处经由第一路径（212）传播的数据相关的信息，其中第一数据路径（212）包括第一晶体管（210）其响应于单个时钟晶体管（214）的输出。第一晶体管（210）具有比与第二数据路径相关联的第二晶体管更高的电流流动能力。

30. 发明授权

EP1112618B1 DIGITALE SCHALTUNG 有权
标题翻译：数字电路
公开(公告)号：EP1112618B1
公开(公告)日：2006-04-12
申请号：EP99953653.5
申请日：1999-09-01
申请人： Infineon Technologies AG
发明人： LE, Thoai-Thai
IPC分类号： H03K3/037
CPC分类号： H03K3/356147 , H03K3/012 , H03K3/037
摘要： The digital circuit has an input (In) for supplying an input signal by means of a first switch element (S1) and an activation input (EN) by means of which it can be switched to an activated or deactivated state. The circuit also comprises a first output (A) supplying in a non-inverted manner in the activated state the level of the input signal immediately before blocking of the switching element (S1) and a second output (/A) supplying in an inverted manner the level of the input signal immediately before blocking of the first switching element (S1). In deactivated state, it furnishes a first logical level (1) to both outputs (A, /A). The circuit also has a logical unit (L) that is connected to both outputs (A, /A) on the input side and to a control connection of the first switch element (S1) on the output side. The logical unit (L) switches the first switch element (S1) in a conductive manner, when the first logical level (1) is applied on both outputs (A, /A). It blocks the first switch element (S1) when a second logical level (0) is applied on both outputs (A, /A).

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