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21. 发明授权

EP2114014B1 Systems and methods for iterative data detection and/or decoding 有权转让
标题翻译：系统和迭代数据检测和/或解码方法
公开(公告)号：EP2114014B1
公开(公告)日：2014-06-18
申请号：EP09156925.1
申请日：2009-03-31
申请人： LSI Corporation
发明人： Yang, Shaohua , Zhong, Hao , Tan, Weijun , Rauschmayer, Richard , Xing Yuan, Lee
IPC分类号： H03M13/29 , H03M13/47 , H03M13/00 , H04L1/00 , G11B20/18 , H03M13/11 , H03M13/15 , H03M13/09 , H03M13/27 , H03M13/39 , H03M13/41
CPC分类号： H03M13/2987 , G11B20/18 , G11B2020/185 , G11B2220/2516 , H03M13/09 , H03M13/1102 , H03M13/1111 , H03M13/15 , H03M13/1515 , H03M13/27 , H03M13/3905 , H03M13/4146 , H03M13/6331 , H03M13/6337 , H04L1/005 , H04L1/0057 , H04L1/0065

22. 发明公开

EP2114014A3 Systems and methods for iterative data detection and/or decoding 有权转让
标题翻译：系统和迭代数据检测和/或解码方法
公开(公告)号：EP2114014A3
公开(公告)日：2011-12-14
申请号：EP09156925.1
申请日：2009-03-31
申请人： LSI Corporation
发明人： Yang, Shaohua , Zhong, Hao , Tan, Weijun , Rauschmayer, Richard , Xing Yuan, Lee
IPC分类号： H03M13/29 , H03M13/47 , H04L1/00 , G11B20/18 , H03M13/11 , H03M13/15 , H03M13/09 , H03M13/27 , H03M13/39 , H03M13/41
CPC分类号： H03M13/2987 , G11B20/18 , G11B2020/185 , G11B2220/2516 , H03M13/09 , H03M13/1102 , H03M13/1111 , H03M13/15 , H03M13/1515 , H03M13/27 , H03M13/3905 , H03M13/4146 , H03M13/6331 , H03M13/6337 , H04L1/005 , H04L1/0057 , H04L1/0065
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a variable iteration data processing system is disclosed that includes at least a first detector, a second detector, a decoder, and a queuing buffer. The first detector is operable to perform a data detection on an input data set at a first time. The decoder receives a derivation of an output from the first detector and performs a decoding process. Where the decoding process fails to converge, the decoder output is passed to the second detector for a subsequent detection and decoding process at a second time.

23. 发明公开

EP2114014A2 Systems and methods for iterative data detection and/or decoding 有权转让
标题翻译： Systeme und Verfahren zur iterativen Datendetektion und / oder -decodierung
公开(公告)号：EP2114014A2
公开(公告)日：2009-11-04
申请号：EP09156925.1
申请日：2009-03-31
申请人： LSI Corporation
发明人： Yang, Shaohua , Zhong, Hao , Tan, Weijun , Rauschmayer, Richard , Xing Yuan, Lee
IPC分类号： H03M13/47 , H03M13/11 , H03M13/15 , H03M13/09 , H03M13/27 , H03M13/39 , H03M13/41
CPC分类号： H03M13/2987 , G11B20/18 , G11B2020/185 , G11B2220/2516 , H03M13/09 , H03M13/1102 , H03M13/1111 , H03M13/15 , H03M13/1515 , H03M13/27 , H03M13/3905 , H03M13/4146 , H03M13/6331 , H03M13/6337 , H04L1/005 , H04L1/0057 , H04L1/0065
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a variable iteration data processing system is disclosed that includes at least a first detector, a second detector, a decoder, and a queuing buffer. The first detector is operable to perform a data detection on an input data set at a first time. The decoder receives a derivation of an output from the first detector and performs a decoding process. Where the decoding process fails to converge, the decoder output is passed to the second detector for a subsequent detection and decoding process at a second time.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，公开了包括至少第一检测器，第二检测器，解码器和排队缓冲器的可变迭代数据处理系统。第一检测器可操作以在第一时间对输入数据集执行数据检测。解码器接收来自第一检测器的输出的导出并执行解码处理。在解码过程不能收敛的情况下，解码器输出被传送到第二检测器用于随后的检测和解码过程。

24. 发明公开

EP1976128A1 Techniques for correcting errors using iterative decoding 审中-公开
标题翻译： Verfahren zur Korrektur von Fehlern mittels iterativer Dekodierung
公开(公告)号：EP1976128A1
公开(公告)日：2008-10-01
申请号：EP07254474.5
申请日：2007-11-16
申请人： Hitachi Global Storage Technologies Netherlands B.V.
发明人： Li, Zongwang , Lee, Yuan , Galbraith, Richard , Djurdjevic, Ivana , Oenning, Travis
IPC分类号： H03M13/11 , H03M13/29
CPC分类号： H03M13/112 , H03M13/1102 , H03M13/1117 , H03M13/1128 , H03M13/1515 , H03M13/2966 , H03M13/2975 , H03M13/2987 , H03M13/6331 , H03M13/658 , H04L1/005 , H04L1/0057
摘要： Techniques are provided for iteratively decoding data recorded on a data storage device. An iterative decoder decodes a stream of equalized samples that represents the data using multiple decoding iterations to correct errors. In multiple iterations of the iterative decoder, a post processing block generates soft information, and a decoder applies a minimum sum decoding algorithm to a low density parity check (LDPC) code to generate extrinsic information based on the soft information and updated soft information. At least the first interaction includes a matched Viterbi detector.
摘要翻译：提供了用于迭代地解码记录在数据存储设备上的数据的技术。迭代解码器使用多个解码迭代来解码表示数据的均衡样本流以校正错误。在迭代解码器的多次迭代中，后处理块产生软信息，并且解码器将最小和解码算法应用于低密度奇偶校验（LDPC）码，以基于软信息和更新的软信息生成外在信息。至少第一次交互包括匹配的维特比检测器。

25. 发明公开

EP1895666A1 Utilizing variable-length input blocks in an inter-sequence permutation turbo code system 审中-公开
标题翻译：涡流代码 - 系统间的交替排列（Verbendung vonEingangsblöckenmit variablerLängein einem Turbocode
公开(公告)号：EP1895666A1
公开(公告)日：2008-03-05
申请号：EP07115243.3
申请日：2007-08-29
申请人： Highdimension Ltd.
发明人： Zheng, Yan-Xiu
IPC分类号： H03M13/29
CPC分类号： H03M13/27 , H03M13/2771 , H03M13/2903 , H03M13/2957 , H03M13/2987 , H03M13/6561
摘要： The present invention relates to an inter-sequence permutation (ISP) encoder. The ISP encoder comprises: a receiving means (202) to receive an information bit sequence input; a first outputting means (207) for outputting a first code bit output; a second outputting means (208) for outputting a second code bit sequence output; a bit-adding means (203) coupled to the receiving means, the bit-adding means processing the received information bit sequence input prior to any subsequent processing in the ISP encoder; a first convolutional code encoder (205) coupled between the bit-adding means and the first outputting means; a second convolutional code encoder (206); and an inter-sequence permutation interleaver (204) coupled between the bit-adding means and the second convolutional code encoder. The second convolutional code encoder is coupled between the inter-sequence permutational interleaver and the second outputting means. Further, the ISP encoder comprises a third outputting means (209) coupled to the bit-adding means to output a third code bit output or directly coupled to the receiving means. Alternatively, the ISP encoder comprises a fourth outputting means coupled to the inter-sequence permutation interleaver to output a fourth code bit sequence output.
摘要翻译：本发明涉及一种序列间置换（ISP）编码器。 ISP编码器包括：接收装置（202），用于接收信息比特序列输入; 用于输出第一码位输出的第一输出装置（207）; 用于输出第二码位序列输出的第二输出装置（208）; 比特加法装置，耦合到所述接收装置，所述比特加法装置处理在所述ISP编码器中的任何后续处理之前输入的接收信息比特序列; 耦合在所述位加法装置和所述第一输出装置之间的第一卷积码编码器（205）第二卷积码编码器（206）; 以及耦合在所述比特加法装置和所述第二卷积码编码器之间的序列间置换交织器（204）。第二卷积码编码器耦合在片间置换交织器和第二输出装置之间。此外，ISP编码器包括耦合到比特加法装置的第三输出装置（209），以输出输出或直接耦合到接收装置的第三码比特。或者，ISP编码器包括耦合到序列间置换交织器的第四输出装置，以输出第四码位序列输出。

26. 发明公开

EP1528688A3 Architecture pour un decodeur iteratif 审中-公开
标题翻译：架构的迭代解码器
公开(公告)号：EP1528688A3
公开(公告)日：2005-06-08
申请号：EP04292102.3
申请日：2004-08-27
申请人： AGENCE SPATIALE EUROPEENNE
发明人： Martinez, Alfonso , Rovini, Massimo
IPC分类号： H03M13/29 , H03M13/37 , H04L1/00
CPC分类号： H04L1/0051 , H03M13/2978 , H03M13/2987 , H03M13/6561 , H04L1/0066
摘要： Décodeur itératif (20) comportant une pluralité de serveurs (22) qui effectuent le décodage itératif d'un bloc de données chacun, une mémoire tampon d'entrée (23) et une unité de contrôle (21) qui effectue un multiplexage statistique des données en entrée, qui sont d'abord stockées dans la mémoire tampon d'entrée (23) et successivement traitées par l'un des serveurs (22). La mémoire tampon d'entrée (23) comporte N+L emplacements de mémoire, où N et le nombre de serveurs (22) et L est le nombre d'emplacements dits supplémentaires. Chaque bloc à décoder qui est reçu pendant que tous les serveurs (22) sont occupés est stocké dans l'un des L emplacements supplémentaires éventuellement disponibles, ou il est perdu si la mémoire tampon d'entrée (23) est entièrement remplie. Le nombre L d'emplacements supplémentaires et le nombre N de serveurs sont calculés sur la base d'un modèle de file d'attente du type D/G/N/N+L de telle sorte que la probabilité P B qu'un bloc soit perdu vérifie la condition P B ≤α·FER*, où FER* est le taux d'erreur sur les blocs admis et α

27. 发明公开

EP1407555A1 LOW DENSITY PARITY CHECK CODES AND LOW DENSITY TURBO PRODUCT CODES 审中-公开
标题翻译： LITTLE密度和低密度奇偶校验Turbo乘积码
公开(公告)号：EP1407555A1
公开(公告)日：2004-04-14
申请号：EP02731730.4
申请日：2002-05-09
申请人： Comtech Telecommunications Corp.
发明人： KHANNANOV, Roman R. , MARKARIAN, Garik , ORTYUKOV, Sergey I. , PICKAVANCE, Keith , PORTNEY, Sergey L.
IPC分类号： H03M13/00
CPC分类号： H03M13/2963 , H03M13/1102 , H03M13/1105 , H03M13/2987 , H03M13/6561
摘要： A method of and apparatus for encoding a one dimensional input codeword into an output codeword, wherein the output codeword includes an output codeword bit comprising the steps of receiving the input codeword, wherein the input codeword includes an input codeword bit; creating a generator matrix (200), wherein the generator matrix includes a parity matrix (204) having a plurality of parity bits; combining the input codeword bit and a corresponding parity bit from the plurality of parity bits, thereby generating an output redundant bit associated with the output codeword bit; transmitting the input codeword bit; and transmitting the output redundant bit.

28. 发明公开

EP1248377A3 Error correction encoding method and apparatus, and error correction decoding method and apparatus 审中-公开
标题翻译：纠错编码方法和装置，以及纠错解码的方法和装置
公开(公告)号：EP1248377A3
公开(公告)日：2003-12-17
申请号：EP02006348.3
申请日：2002-03-21
申请人： MITSUBISHI DENKI KABUSHIKI KAISHA
发明人： Miyata, Yoshikuni , Fujita, Hachiro , Nakamura, Takahiko , Yoshida, Hideo
IPC分类号： H03M13/29 , H03M13/41
CPC分类号： H03M13/2987 , H03M13/2957 , H03M13/2963 , H03M13/2972 , H03M13/2981 , H03M13/3776
摘要： An error correction encoding method and apparatus, and an error correction decoding method and apparatus are provided without requiring transmission of tail bits. A turbo encoding step (ST41 - ST45) and a transmission termination processing step (ST46 → ST44 - ST47) are included. In the turbo encoding step, a transmission information bit sequence is divided into a plurality of frames. Registers in each recursive systematic convolutional encoder are initialized before turbo encoding of a first frame. After turbo encoding of the first frame is carried out, a second frame and following frames are continuously subjected to turbo encoding without initializing the registers in each recursive systematic convolutional encoder before the turbo encoding of the second frame and following frames. In a transmission termination processing step, tail bits for initializing the registers in each recursive systematic convolutional encoder are calculated only after a final frame has been subjected to turbo encoding.

29. 发明公开

EP1198894A2 A SYSTEM AND METHOD EMPLOYING A MODULAR DECODER FOR DECODING TURBO AND TURBO-LIKE CODES IN A COMMUNICATIONS NETWORK 审中-公开
标题翻译：系统和方法使用通信网络的模块化解码器DECODE TURBO和Turbo-LIKE KODEN
公开(公告)号：EP1198894A2
公开(公告)日：2002-04-24
申请号：EP01909103.2
申请日：2001-02-12
申请人： Hughes Electronics Corporation
发明人： HAMMONS, Roger , VENKARTARAMN, Bharath , EROZ, Mustafa
IPC分类号： H03M13/29 , H03M13/00
CPC分类号： H03M13/2987 , H03M13/296 , H03M13/2966 , H03M13/2981 , H03M13/6362
摘要： A system and method for decoding encoded data, employing a parser and at least one decoder. The parser receives and parses the encoded data into a plurality of parsed data streams, with each of the parsed data streams including a portion of said encoded data. The decoder decodes the parsed data streams based on at least information included in the parsed data streams to provide decoded data which includes soft decision data. The decoder can perform a respective decoding iteration on each respective one of the parsed data streams to provide the decoded data, and can perform such decoding iterations based on additional information, such as parity information, pertaining to the data in the parsed data streams. Alternatively, the decoder can include a plurality of decoders, each adapted to decode a respective one of the parsed data streams to output a respective decoded data stream as a portion of the decoded data. The system and method alternatively can be configured without a parser, and can employ at least one soft decoder module and another decoder module. The soft decoder module can perform multiple decoding iterations on the encoded data to provide soft decision data relating to the encoded data, without providing any hard decision data, and the other decoder module decodes the encoded data based on the soft decision data to provide hard decoded data representative of a decoded condition of said encoded data and/or soft decision data relating to said encoded data.

30. 发明授权

EP0735696B1 Procédé de décodage itératif, module de décodage et décodeur correspondants 失效
标题翻译：迭代解码方法，解码模块和解码器，用于
公开(公告)号：EP0735696B1
公开(公告)日：2001-07-11
申请号：EP96107690.8
申请日：1992-04-22
申请人： FRANCE TELECOM , TELEDIFFUSION DE FRANCE S.A.
发明人： Berrou, Claude
IPC分类号： H03M13/23 , H03M13/27 , H03M13/00
CPC分类号： H04L1/0066 , H03M13/23 , H03M13/27 , H03M13/2957 , H03M13/2987 , H03M13/39 , H03M13/6362 , H03M13/658 , H04L1/005 , H04L1/0068 , H04L1/0071

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