![Architecture pour un decodeur iteratif](/ep/2005/06/08/EP1528688A3/abs.jpg.150x150.jpg)
基本信息:
- 专利标题: Architecture pour un decodeur iteratif
- 专利标题(英):Architecture for an iterative decoder
- 专利标题(中):架构的迭代解码器
- 申请号:EP04292102.3 申请日:2004-08-27
- 公开(公告)号:EP1528688A3 公开(公告)日:2005-06-08
- 发明人: Martinez, Alfonso , Rovini, Massimo
- 申请人: AGENCE SPATIALE EUROPEENNE
- 申请人地址: 8-10, rue Mario Nikis F-75738 Paris Cedex 15 FR
- 专利权人: AGENCE SPATIALE EUROPEENNE
- 当前专利权人: AGENCE SPATIALE EUROPEENNE
- 当前专利权人地址: 8-10, rue Mario Nikis F-75738 Paris Cedex 15 FR
- 代理机构: Jacquard, Philippe Jean-Luc
- 优先权: FR0310261 20030828
- 主分类号: H03M13/29
- IPC分类号: H03M13/29 ; H03M13/37 ; H04L1/00
iterative decoder (20) having a plurality of servers (22) that perform iterative decoding of a data block each, an input buffer memory (23) and a control unit (21) which performs a statistical multiplexing of data input, which is first stored in the input buffer (23) and subsequently processed by one of the servers (22). The input buffer (23) has N + L memory locations, where N and the number of servers (22) and L is the number of additional locations called. Each block to be decoded is received while all servers (22) are occupied is stored in one of The additional slots may be available, or it is lost if the input buffer (23) is completely filled. The number of additional locations and the number N of servers are calculated on the basis of a queue model of type D / G / N / N + L so that the probability P that a block B or lost checks the condition P B ≤α · IRON *, where * is FER the error rate on accepted blocks and α <1; α is typically of the order of 0.01. Method of manufacturing such a iterative decoder comprising a stage of design and material manufacturing step.
公开/授权文献:
- EP1528688A2 Architecture pour un decodeur iteratif 公开/授权日:2005-05-04
IPC结构图谱:
H | 电学 |
--H03 | 基本电子电路 |
----H03M | 一般编码、译码或代码转换 |
------H03M13/00 | 用于检错或纠错的编码、译码或代码转换;编码理论基本假设;编码约束;误差概率估计方法;信道模型;代码的模拟或测试 |
--------H03M13/29 | .合并两个或多个代码或代码结构,例如乘积码、广义乘积码、链接码、内层码和外层码 |