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1. 发明授权

EP2582053B1 Systems and methods for LDPC encoding with composite codewords and sub-codewords 有权
标题翻译：系统和程序的LDPC编码联合码字和子码字
公开(公告)号：EP2582053B1
公开(公告)日：2015-11-18
申请号：EP12184427.8
申请日：2012-09-14
申请人： LSI Corporation
发明人： Xia, Haitao , Yang, Shaohua , Yen, Johnson
IPC分类号： H03M13/11 , H03M13/29 , H03M13/37 , G11B20/18
CPC分类号： H03M13/1102 , G11B20/1833 , G11B2020/185 , G11B2220/2516 , H03M13/2942 , H03M13/3761 , H03M13/6331 , H03M13/6343 , H03M13/6502

2. 发明公开

EP2744113A1 DECODING DEVICE AND DECODING METHOD 审中-公开
标题翻译： VORRICHTUNG UND VERFAHREN ZUM DEKODIEREN
公开(公告)号：EP2744113A1
公开(公告)日：2014-06-18
申请号：EP12821855.9
申请日：2012-08-01
申请人： Panasonic Corporation
发明人： FUJIMOTO, Keisuke , HINO, Yasumori
IPC分类号： H03M13/19 , G11B20/18
CPC分类号： G06F11/10 , G11B20/1833 , G11B2020/185 , G11B2220/2537 , H03M13/1111 , H03M13/1128 , H03M13/41
摘要： A control device (211) inputs reliability information on the same data block a plurality of times into a reliability storage memory (202). A reliability generating device (201) generates anew reliability information by performing computation processing based on a stochastic computation by using reliability information generated in the previous cycle that has been saved in the reliability storage memory (202) and reliability information generated in the present cycle, and saves the reliability information generated anew in the reliability storage memory (202) when the decoding is performed by using reliability information on the data block same as that in the previous cycle. A column processing computation device (204) computes a column processing output value by using the reliability information generated anew and saved in the reliability storage memory (202) and a row processing output value.
摘要翻译：控制装置（211）将相同数据块上的可靠性信息多次输入到可靠性存储存储器（202）中。可靠性生成装置（201）通过使用保存在可靠性存储器（202）中的上一个循环中生成的可靠性信息和在本周期中生成的可靠性信息，通过进行基于随机运算的计算处理，生成新的可靠性信息，并且当通过使用与前一个周期相同的数据块的可靠性信息来执行解码时，将可靠性信息重新生成在可靠性存储存储器（202）中。列处理计算装置（204）通过使用重新生成并保存在可靠性存储存储器（202）中的可靠性信息和行处理输出值来计算列处理输出值。

3. 发明公开

EP2637337A2 Systems and methods for out of order data reporting 审中-公开
标题翻译： Systeme und VerfahrenfürirreguläreDatenberichterstattung
公开(公告)号：EP2637337A2
公开(公告)日：2013-09-11
申请号：EP13152681.6
申请日：2013-01-25
申请人： LSI Corporation
发明人： Yang, Shaohua , Zhang, Fan , Han, Yang
IPC分类号： H04L1/00
CPC分类号： H04L1/0052 , G11B20/10527 , G11B2020/1062 , G11B2020/185 , G11B2220/2516 , H03M13/2957 , H03M13/6343 , H04L1/005
摘要： The present inventions are related to systems and methods for data processing, the data processing system comprising: a data processing circuit operable to: receive a first, a second and a third received data set; wherein the first data set is received prior to the second data set, and the second data set is received prior to the third data set; apply a data processing algorithm to the first received data set to yield a first output data set, apply the algorithm to the second received data set to yield a second output data set, and apply the algorithm to the third received data set to yield a third output data set; and an out of order enabling circuit operable to assert an order indicator output to indicate the second output data set is out of order when the second output data set is provided before the first output data set.
摘要翻译：本发明涉及用于数据处理的系统和方法，所述数据处理系统包括：数据处理电路，可操作以：接收第一，第二和第三接收数据集; 其中在所述第二数据集之前接收所述第一数据集，并且在所述第三数据集之前接收所述第二数据集; 将数据处理算法应用于第一接收数据集以产生第一输出数据集，将算法应用于第二接收数据集以产生第二输出数据集，并将算法应用于第三接收数据集，以产生第三数据集输出数据集; 并且当在第一输出数据集之前提供第二输出数据集时，可操作以断言指示第二输出数据集的顺序指示符输出的失序使能电路是无序的。

4. 发明公开

EP2709107A1 Systems and methods for hard decision based ITI cancellation 审中-公开
标题翻译： System-und Verfahren zum ITI-Abbruch auf Hard-Decision-Basis
公开(公告)号：EP2709107A1
公开(公告)日：2014-03-19
申请号：EP13175952.4
申请日：2013-07-10
申请人： LSI Corporation
发明人： Xiao, Jun , Haratsch, Eric F. , Zhang, Fan
IPC分类号： G11B5/012 , G11B20/10 , G11B20/24
CPC分类号： G11B20/10009 , G11B5/012 , G11B5/09 , G11B20/10046 , G11B20/1037 , G11B2020/185 , G11B2220/2516
摘要： Embodiments of the present inventions are related to systems and methods for data processing, and more particularly to systems and methods for reducing inter-track interference in relation to processing data retrieved from a storage medium.
摘要翻译：本发明的实施例涉及用于数据处理的系统和方法，更具体地涉及用于减少与从存储介质检索的处理数据相关的轨道间干扰的系统和方法。

5. 发明授权

EP2086114B1 Concatenated codes combining Reed-Solomon codes, LDPC codes and parity codes for encoding/decoding devices 有权
标题翻译：的Reed-Solomon码，LDPC码和奇偶码以进行Encodierungs- /解码装置的级联码
公开(公告)号：EP2086114B1
公开(公告)日：2014-01-15
申请号：EP08170099.9
申请日：2008-11-27
申请人： Fujitsu Limited
发明人： Kanaoka, Toshikazu , Ito, Toshio
IPC分类号： H03M13/29 , G11B20/00 , H03M13/27 , H03M13/11 , H03M13/09 , H03M13/15
CPC分类号： H03M13/2927 , G11B20/1833 , G11B20/1866 , G11B2020/1836 , G11B2020/1843 , G11B2020/185 , G11B2220/2516 , G11B2220/2537 , H03M13/098 , H03M13/1102 , H03M13/1515 , H03M13/271 , H03M13/2721 , H03M13/2778 , H03M13/2906 , H03M13/2918 , H03M13/2921 , H03M13/293 , H03M13/2957

6. 发明公开

EP2637170A1 Systems and methods for data processing including pre-equalizer noise suppression 审中-公开
标题翻译：系统与Verfahren zur Datenverarbeitung mitVorentzerrerrauschunterdrückung
公开(公告)号：EP2637170A1
公开(公告)日：2013-09-11
申请号：EP13152678.2
申请日：2013-01-25
申请人： LSI Corporation
发明人： Yang, Shaohua , Lu, Jin
IPC分类号： G11B20/10 , G11B20/18 , G11B20/12
CPC分类号： G11B20/10046 , G11B20/10379 , G11B20/1816 , G11B2020/1287 , G11B2020/183 , G11B2020/185 , G11B2220/2516 , G11B2220/415
摘要： The present inventions are related to systems and methods for pre-equalizer noise suppression in a data processing system. As an example, a data processing system is discussed that includes: a sample averaging circuit, a selector circuit, an equalizer circuit, and a mark detector circuit. The sample averaging circuit is operable to average corresponding data samples from at least a first read of a codeword and a second read of the codeword to yield an averaged output based at least in part on a framing signal. The selector circuit is operable to select one of the averaged output and the first read of the codeword as a selected output. The equalizer circuit is operable to equalize the selected output to yield an equalized output, and the mark detector circuit is operable to identify a location mark in the equalized output to yield the framing signal.
摘要翻译：本发明涉及用于数据处理系统中预均衡器噪声抑制的系统和方法。作为示例，讨论了包括：采样平均电路，选择器电路，均衡器电路和标记检测器电路的数据处理系统。采样平均电路可操作以从码字的至少第一读取和码字的第二读取来平均对应的数据样本，以产生至少部分地基于成帧信号的平均输出。选择器电路可操作以选择平均输出和码字的第一读取中的一个作为选择的输出。均衡器电路可操作以均衡所选择的输出以产生均衡的输出，并且标记检测器电路可操作以识别均衡输出中的位置标记以产生成帧信号。

7. 发明公开

EP2086114A3 Concatenated codes combining Reed-Solomon codes, LDPC codes and parity codes for encoding/decoding devices 有权
标题翻译： Verkettete码aus Reed-Solomon码，LDPC码和奇偶校验码fürEncodierungs- / Decodierungsapparate
公开(公告)号：EP2086114A3
公开(公告)日：2012-09-12
申请号：EP08170099.9
申请日：2008-11-27
申请人： Fujitsu Limited
发明人： Kanaoka, Toshikazu , Ito, Toshio
IPC分类号： H03M13/29 , G11B20/00 , H03M13/27 , H03M13/11 , H03M13/09 , H03M13/15
CPC分类号： H03M13/2927 , G11B20/1833 , G11B20/1866 , G11B2020/1836 , G11B2020/1843 , G11B2020/185 , G11B2220/2516 , G11B2220/2537 , H03M13/098 , H03M13/1102 , H03M13/1515 , H03M13/271 , H03M13/2721 , H03M13/2778 , H03M13/2906 , H03M13/2918 , H03M13/2921 , H03M13/293 , H03M13/2957
摘要： An error correction device error corrects without increasing the circuit scale. An encoder includes: a first ECC encoder (235) which interleaves a data string into n (n ≥ 2) blocks of data strings at every m (m ≥ 2) bits, and adds the error correction code parity; a parity encoder (234) which creates a parity bit at every plurality of bits of the error correction code word, and adds the parity bit to said error correction code word; and a second ECC encoder (220), which generates a second error correction encoding, which is a linear encoding using iterative decoding. Concatenated type encoded data, where a parity bit is added to every plurality of bits, is created, so an increase of circuit scale can be prevented even if a data string is interleaved into a plurality of blocks and error correction code parity is generated. The device may be applied, for example, to a long sector type hard disk.

8. 发明公开

EP2086114A2 Concatenated codes combining Reed-Solomon codes, LDPC codes and parity codes for encoding/decoding devices 有权
标题翻译： Verkettete码aus Reed-Solomon码，LDPC码和奇偶校验码fürEncodierungs- / Decodierungsapparate
公开(公告)号：EP2086114A2
公开(公告)日：2009-08-05
申请号：EP08170099.9
申请日：2008-11-27
申请人： Fujitsu Limited
发明人： Kanaoka, Toshikazu , Ito, Toshio
IPC分类号： H03M13/29 , H03M13/11 , H03M13/09 , H03M13/15
CPC分类号： H03M13/2927 , G11B20/1833 , G11B20/1866 , G11B2020/1836 , G11B2020/1843 , G11B2020/185 , G11B2220/2516 , G11B2220/2537 , H03M13/098 , H03M13/1102 , H03M13/1515 , H03M13/271 , H03M13/2721 , H03M13/2778 , H03M13/2906 , H03M13/2918 , H03M13/2921 , H03M13/293 , H03M13/2957
摘要： An error correction device error corrects without increasing the circuit scale. An encoder includes: a first ECC encoder (235) which interleaves a data string into n (n ≥ 2) blocks of data strings at every m (m ≥ 2) bits, and adds the error correction code parity; a parity encoder (234) which creates a parity bit at every plurality of bits of the error correction code word, and adds the parity bit to said error correction code word; and a second ECC encoder (220), which generates a second error correction encoding, which is a linear encoding using iterative decoding. Concatenated type encoded data, where a parity bit is added to every plurality of bits, is created, so an increase of circuit scale can be prevented even if a data string is interleaved into a plurality of blocks and error correction code parity is generated. The device may be applied, for example, to a long sector type hard disk.
摘要翻译：错误纠正装置错误在不增加电路规模的情况下进行纠正。编码器包括：以每m（m‰2）位为单位将数据串交织成n（n‰）个数据串的第一ECC编码器，并将误差校正码奇偶校验相加; 奇偶编码器（234），其在纠错码字的每个多个位产生奇偶校验位，并将奇偶校验位加到所述纠错码字; 以及第二ECC编码器（220），其生成使用迭代解码的线性编码的第二纠错编码。创建了将奇偶校验位添加到每个多个位的级联型编码数据，因此即使将数据串交错为多个块并且生成纠错码奇偶校验，也可以防止电路规模的增加。该装置可以例如应用于长扇形硬盘。

9. 发明公开

EP2307960A4 ERROR-FLOOR MITIGATION OF CODES USING WRITE VERIFICATION 有权
标题翻译：码与写入验证错误平台还原
公开(公告)号：EP2307960A4
公开(公告)日：2013-01-16
申请号：EP09843763
申请日：2009-04-21
申请人： AGERE SYSTEMS INC
发明人： GRAEF NILS , GUNMAN KIRAN
IPC分类号： G06F11/00 , G06F11/10
CPC分类号： H03M13/1102 , G06F11/1012 , G11B20/1833 , G11B2020/1823 , G11B2020/185 , G11B2220/2516 , G11B2220/61 , H03M13/1108 , H03M13/1142 , H03M13/455
摘要： Executed when a channel input (e.g., LDPC) codeword is written to a storage medium, a write-verification method (i) compares the channel input codeword to the written codeword, (ii) identifies any erroneous bits, and (iii) stores the erroneous-bit indices to a record in a table. At some later time, the written codeword is read and sent to a decoder. If the decoder fails with a near codeword, a write-error recovery process searches the table and retrieves the erroneous-bit information. The codeword bits at those indices are adjusted, and the modified codeword is submitted to further processing.

10. 发明公开

EP2347416A4 SYSTEMS AND METHODS FOR NOISE REDUCED DATA DETECTION 审中-公开
标题翻译：系统和方法噪声降低的数据检测
公开(公告)号：EP2347416A4
公开(公告)日：2012-05-30
申请号：EP09827908
申请日：2009-04-17
申请人： LSI CORP
发明人： YANG SHAOHUA , LEE YUAN XING , RAUSCHMAYER RICHARD , SONG HONGWEI , LIU JINGFENG , TAN WEIJUN
IPC分类号： G11B20/18 , G11B20/10 , G11B20/24 , H04L1/00 , H04L1/16
CPC分类号： G11B20/24 , G11B20/10037 , G11B20/10194 , G11B20/10527 , G11B20/1833 , G11B20/1879 , G11B2020/1062 , G11B2020/10685 , G11B2020/10694 , G11B2020/10759 , G11B2020/183 , G11B2020/185 , G11B2220/2516 , H03M13/1105 , H03M13/2948 , H03M13/3746 , H03M13/6343 , H04L1/005 , H04L1/0057

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