专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明公开

EP2586127A4 TRANSMISSION GATE CIRCUITRY FOR HIGH VOLTAGE TERMINAL 审中-公开
标题翻译：传输的基础之上电路对高压端子
公开(公告)号：EP2586127A4
公开(公告)日：2014-02-12
申请号：EP11807201
申请日：2011-05-09
申请人： FREESCALE SEMICONDUCTOR INC
发明人： STOCKINGER MICHAEL A , CAMARENA JOSE A , ZHANG WENZHONG
IPC分类号： H03K17/16 , H03K17/10 , H03K19/003
CPC分类号： H03K17/102

22. 发明公开

EP2691854A1 A METHOD AND APPARATUS FOR CONTROLLING FETCH-AHEAD IN A VLES PROCESSOR ARCHITECTURE 审中-公开
标题翻译：方法和装置预加载控制研究VLES处理器架构
公开(公告)号：EP2691854A1
公开(公告)日：2014-02-05
申请号：EP11862267.9
申请日：2011-03-30
申请人： Freescale Semiconductor, Inc.
发明人： VASKEVICH, Lev , ELNEKAVE, Mark , PELED, Yuval , ROZENBERG, Idan
IPC分类号： G06F9/38
CPC分类号： G06F9/3802 , G06F9/3814 , G06F9/3853
摘要： There is provided a method for controlling fetch-ahead of Fetch Sets into a decoupling First In First Out (FIFO) buffer of a Variable Length Execution Set (VLES) processor architecture, wherein a Fetch Set comprises at least a portion of a VLES group available for dispatch to processing resources within the VLES processor architecture, comprising, for each cycle, determining a number of VLES groups available for dispatch from previously pre-fetched Fetch Sets, and only requesting a fetch-ahead of a next Fetch Set in the next cycle if any one or more of the following is asserted: the number of VLES groups available for dispatch is less than a predetermined starvation threshold, OR the number of VLES groups available for dispatch is indicative of going below a predetermined upper limit threshold, OR the number of VLES groups available for dispatch is indicative of being between the predetermined starvation threshold and the predetermined upper limit threshold, and a fetch-ahead of a Fetch Set occurred in an immediately previous cycle.

23. 发明公开

EP2676369A1 OVERCURRENT PROTECTION DEVICE AND METHOD OF OPERATING A POWER SWITCH 审中-公开
标题翻译：过流保护装置和操作电源开关的方法
公开(公告)号：EP2676369A1
公开(公告)日：2013-12-25
申请号：EP11754552.5
申请日：2011-02-18
申请人： Freescale Semiconductor, Inc.
发明人： SYNGAEVSKIY, Vasily Alekseyevich , GUILLOT, Laurent , ROSADO, Philippe , SHUVALOV, Denis Sergeevich , SOLDATOV, Alexander Petrovich
IPC分类号： H03K17/082
CPC分类号： H02H3/093 , H03K17/082
摘要： An overcurrent protection device comprises a maximum-allowed-current unit and a power switch. The maximum-allowed-current unit determines a maximum allowed current in real-time. The maximum allowed current is determined at least partially on an instantaneous level of a load voltage. The load voltage is a voltage across a load to be powered. The power switch is connectable with a switch input to a voltage supply and with a switch output to the load, for providing power to said load. The power switch has a conductive state and a nonconductive state, and is arranged to assume the nonconductive state in response to an indication that a current through the power switch is exceeding the maximum allowed current. A method of operating a power switch is also described.
摘要翻译：过电流保护装置包括最大允许电流单元和电源开关。最大允许电流单位实时确定最大允许电流。最大允许电流至少部分地在负载电压的瞬时电平上确定。负载电压是要通电的负载两端的电压。电源开关可连接到电源的开关输入和开关输出到负载，以向所述负载提供电力。功率开关具有导通状态和非导通状态，并且被布置为响应于通过功率开关的电流超过最大允许电流的指示而呈现非导通状态。还描述了操作电源开关的方法。

24. 发明公开

EP2263254A4 DUAL GATE LATERAL DIFFUSED MOS TRANSISTOR 审中-公开
标题翻译：两个栅极LATERALDIFFUSIONS MOS晶体管
公开(公告)号：EP2263254A4
公开(公告)日：2013-12-25
申请号：EP09727967
申请日：2009-02-05
申请人： FREESCALE SEMICONDUCTOR INC
发明人： YANG HONGNING , ZUO JIANG-KAI
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L27/0705 , H01L29/1045 , H01L29/1083 , H01L29/402 , H01L29/41775 , H01L29/66659 , H01L29/7831 , H01L29/7835
摘要： A disclosed power transistor, suitable for use in a switch mode converter that is operable with a switching frequency exceeding, for example, 5 MHz or more, includes a gate dielectric layer overlying an upper surface of a semiconductor substrate and first and second gate electrodes overlying the gate dielectric layer. The first gate electrode is laterally positioned overlying a first region of the substrate. The first substrate region has a first type of doping, which may be either n-type or p-type. A second gate electrode of the power transistor overlies the gate dielectric and is laterally positioned over a second region of the substrate. The second substrate region has a second doping type that is different than the first type. The transistor further includes a drift region located within the substrate in close proximity to an upper surface of the substrate and laterally positioned between the first and second substrate regions.

25. 发明公开

EP2672486A2 Clocked memory with word line activation during a first portion of the clock cycle 审中-公开
标题翻译： Getaktete Speicher mit Wortzeilenaktivierungwährendeines Ersten Teils des Taktzyklus
公开(公告)号：EP2672486A2
公开(公告)日：2013-12-11
申请号：EP13169553.8
申请日：2013-05-28
申请人： Freescale Semiconductor, Inc.
发明人： Ramamurthy, Hema , Ramaraju, Ravindraraj
IPC分类号： G11C8/08 , G11C8/18 , G11C7/22
CPC分类号： G11C8/10 , G11C7/222 , G11C8/08 , G11C8/18
摘要： A memory (10) includes a plurality of latching predecoders (20, 22, 24, 26), each including a first transistor (30, 136) coupled between a power supply voltage and a latch and having a control electrode coupled to a clock signal; a second transistor (32, 108) coupled to the first transistor and having a control electrode coupled to a first address bit signal; a third transistor (34, 110) coupled to the second transistor and having a control electrode coupled to a second address bit signal; a fourth transistor (36, 112) coupled to the third transistor and having a control electrode coupled to a delayed and inverted version of the clock signal; a fifth transistor (38, 114) coupled between the fourth transistor and ground and having a control electrode coupled to the clock signal; and an output which provides a predecode value (A6A7b) during a first portion of a clock cycle of the clock signal and a predetermined logic level during a second portion of the clock cycle.
摘要翻译：存储器（10）包括多个锁存预解码器（20,22,24,26），每个锁存预解码器包括耦合在电源电压和锁存器之间并具有耦合到时钟信号的控制电极的第一晶体管（30,136） ; 耦合到所述第一晶体管并且具有耦合到第一地址位信号的控制电极的第二晶体管（32,108）耦合到所述第二晶体管并且具有耦合到第二地址位信号的控制电极的第三晶体管（34,110）第四晶体管（36,112），其耦合到所述第三晶体管并具有耦合到所述时钟信号的延迟和反相形式的控制电极; 第五晶体管（38,114），耦合在所述第四晶体管和地之间并且具有耦合到所述时钟信号的控制电极; 以及在时钟周期的第二部分期间在时钟信号的时钟周期的第一部分和预定逻辑电平期间提供预解码值（A6A7b）的输出。

26. 发明公开

EP2671227A1 INTEGRATED CIRCUIT DEVICE, VOLTAGE REGULATION CIRCUITRY AND METHOD FOR REGULATING A VOLTAGE SUPPLY SIGNAL 审中-公开
标题翻译：集成电路器件的电压环路和一种用于控制电源信号
公开(公告)号：EP2671227A1
公开(公告)日：2013-12-11
申请号：EP11857657.8
申请日：2011-01-31
申请人： Freescale Semiconductor, Inc.
发明人： PRIEL, Michael , KUZMIN, Dan , ROZEN, Anton
IPC分类号： G11C5/14
CPC分类号： G05F1/462 , G11C5/147 , G11C7/04 , G11C16/30
摘要： An integrated circuit (IC) device is provided that includes at least one internal voltage regulator arranged to receive a voltage supply signal at a first input thereof, receive a control signal at a second input thereof, regulate the received voltage supply signal in accordance with the received control signal, and provide a regulated voltage supply signal at an output thereof. The IC device further includes at least one voltage regulation power control module operably coupled to the second input of the at least one internal voltage regulator and arranged to provide the control signal thereto. The voltage regulation power control module is further arranged to receive at least one IC device conditional indication, and generate the control signal for the at least one internal voltage regulator based at least partly on an available thermal power budget for the IC device corresponding to the at least one IC device conditional indication.
摘要翻译：一种集成电路（IC）装置设置确实包括布置在第一输入，用于接收电压供应信号其在第二输入接收控制信号其在雅舞的调节接收电压供应信号的至少一个内部电压调节器接收的控制信号，并在它们的输出端提供调节的电压供应信号。所述IC器件包括：至少一个另外的电压调节功率控制模块可操作地耦合到所述至少一个内部电压调节器的第二输入端和布置成提供所述控制信号于此。电压调节功率控制模块被进一步设置成接收至少一个集成电路设备条件指示，并产生用于至少部分地基于上可用的热功率预算IC装置在对应于所述至少一个内部电压调节器的控制信号至少一个IC装置的条件指示。

27. 发明公开

EP2669807A2 Processor resource and execution protection methods and apparatus 有权
标题翻译：处理器资源和执行保护的方法和装置
公开(公告)号：EP2669807A2
公开(公告)日：2013-12-04
申请号：EP13169521.5
申请日：2013-05-28
申请人： Freescale Semiconductor, Inc.
发明人： McCarthy, Daniel M. , Circello, Joseph , Hausman, Kirsten A.
IPC分类号： G06F12/14
CPC分类号： G06F12/1491 , G06F9/30181 , G06F9/30189 , G06F9/321 , G06F9/3802 , G06F9/3804 , G06F12/023 , G06F12/1441 , G06F2212/1044 , G06F2212/1052
摘要： Embodiments include processing systems (110) that determine (308), based on an instruction address range indicator stored in a first register (132, 212), whether a next instruction fetch address corresponds to a location within a first memory region (216, 218) associated with a current privilege state or within a second memory region (216, 218) associated with a different privilege state. When the next instruction fetch address is not within the first memory region (216, 218), the next instruction is allowed to be fetched (314) only when a transition to the different privilege state is legal (310). In a further embodiment, when a data access address is generated for an instruction (316), a determination is made (320), based on a data address range indicator stored in a second register (133, 222), whether access to a memory location corresponding to the data access address is allowed. The access is allowed (318) when the current privilege state is a privilege state in which access to the memory location is allowed.

28. 发明公开

EP2482456A3 Multiple function domain level shifter 审中-公开
标题翻译：具有多种功能的电源域电平转换器
公开(公告)号：EP2482456A3
公开(公告)日：2013-11-27
申请号：EP12151642.1
申请日：2012-01-18
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： Jarrar, Anis M. , Singhania, Anuj , Weston, Bryan T.
IPC分类号： H03K19/0185 , H03K3/356
CPC分类号： H03K19/018521 , H03K3/356182
摘要： A level shifter (300) including input (VDDIN) and output (VDDOUT) power nodes, input (VSSIN) and output (VSSOUT) reference nodes, input (IN) and output (OUT) signal nodes, and a lever shifter network (405,410,415,420,425,430,440). The input power and input reference nodes operate within a first power domain (202, 204, 206) and the output power and output reference nodes operate within a second power domain (202,204,206). The level shifter network receives an input signal operable within the first power domain, performs voltage shifting between the input and output power nodes and between the input and output reference nodes, and provides an output signal output signal indicative of the input signal that operates within the second power domain. The level shifter may include power (BYP_VDD) and/or ground (BYP_VSS) bypass such that either one or both of power and ground voltage shifting may be bypassed for faster switching. The level shifter may include an isolation input (ISO) to assert the output to a known level.

29. 发明公开

EP2643705A1 INTEGRATED CIRCUIT DEVICE AND METHOD FOR DETECTING AN EXCESSIVE VOLTAGE STATE 审中-公开
标题翻译：集成电路器件及其检测方法的涌浪状况的
公开(公告)号：EP2643705A1
公开(公告)日：2013-10-02
申请号：EP10859964.8
申请日：2010-11-22
申请人： Freescale Semiconductor, Inc.
发明人： ROBERTSON, Alistair , CULSHAW, Carl , DEVINE, Alan
IPC分类号： G01R19/165 , H03M1/12
CPC分类号： H02H3/20 , G01R19/0084 , G01R19/165 , H03M1/12 , H03M1/129
摘要： An integrated circuit device (100) comprising at least one analogue to digital converter (ADC) (110). The at least one ADC (110) comprises at least one input (115) operably coupled to at least one external contact (105) of the integrated circuit device (100). The integrated circuit device (100) further comprises detection circuitry (120) comprising at least one detection module (130). The at least one detection module (130) being arranged to receive at a first input (132) thereof an indication (140) of a voltage level at the at least one input (115) of the at least one ADC (110), compare the received indication (140) to a threshold value (145), and if the received indication (140) exceeds the threshold value (145), output (135) an indication that an excessive voltage state at the at least one input (115) of the at least one ADC (110) has been detected.

30. 发明公开

EP2480976A4 MEMORY DEVICE AND METHOD 审中-公开
标题翻译：存储装置及方法
公开(公告)号：EP2480976A4
公开(公告)日：2013-08-07
申请号：EP10817624
申请日：2010-08-16
申请人： FREESCALE SEMICONDUCTOR INC
发明人： BORRACINI EVANDRO JOSE PITARO , ARAUJO MARCELO DEL FIORE DE , BASTREGHI JEFFERSON , SCOULLER ROSS SINCLAIR
IPC分类号： G06F13/10 , G06F12/02 , G06F12/06 , G06F13/16 , G06F13/38
CPC分类号： G06F12/0246 , G06F12/0607 , G06F13/1647 , G06F2212/7201

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式