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1. 发明公开

EP2669807A2 Processor resource and execution protection methods and apparatus 有权
标题翻译：处理器资源和执行保护的方法和装置
公开(公告)号：EP2669807A2
公开(公告)日：2013-12-04
申请号：EP13169521.5
申请日：2013-05-28
申请人： Freescale Semiconductor, Inc.
发明人： McCarthy, Daniel M. , Circello, Joseph , Hausman, Kirsten A.
IPC分类号： G06F12/14
CPC分类号： G06F12/1491 , G06F9/30181 , G06F9/30189 , G06F9/321 , G06F9/3802 , G06F9/3804 , G06F12/023 , G06F12/1441 , G06F2212/1044 , G06F2212/1052
摘要： Embodiments include processing systems (110) that determine (308), based on an instruction address range indicator stored in a first register (132, 212), whether a next instruction fetch address corresponds to a location within a first memory region (216, 218) associated with a current privilege state or within a second memory region (216, 218) associated with a different privilege state. When the next instruction fetch address is not within the first memory region (216, 218), the next instruction is allowed to be fetched (314) only when a transition to the different privilege state is legal (310). In a further embodiment, when a data access address is generated for an instruction (316), a determination is made (320), based on a data address range indicator stored in a second register (133, 222), whether access to a memory location corresponding to the data access address is allowed. The access is allowed (318) when the current privilege state is a privilege state in which access to the memory location is allowed.

2. 发明授权

EP2669807B1 Processor resource and execution protection methods and apparatus 有权
标题翻译： Prozessorressource和Ausführungungschutzverfahrenund Vorrichtung
公开(公告)号：EP2669807B1
公开(公告)日：2015-07-08
申请号：EP13169521.5
申请日：2013-05-28
申请人： Freescale Semiconductor, Inc.
发明人： McCarthy, Daniel M. , Circello, Joseph , Hausman, Kirsten A.
IPC分类号： G06F12/14 , G06F9/38 , G06F9/32 , G06F9/30
CPC分类号： G06F12/1491 , G06F9/30181 , G06F9/30189 , G06F9/321 , G06F9/3802 , G06F9/3804 , G06F12/023 , G06F12/1441 , G06F2212/1044 , G06F2212/1052
摘要： Embodiments include processing systems (110) that determine (308), based on an instruction address range indicator stored in a first register (132, 212), whether a next instruction fetch address corresponds to a location within a first memory region (216, 218) associated with a current privilege state or within a second memory region (216, 218) associated with a different privilege state. When the next instruction fetch address is not within the first memory region (216, 218), the next instruction is allowed to be fetched (314) only when a transition to the different privilege state is legal (310). In a further embodiment, when a data access address is generated for an instruction (316), a determination is made (320), based on a data address range indicator stored in a second register (133, 222), whether access to a memory location corresponding to the data access address is allowed. The access is allowed (318) when the current privilege state is a privilege state in which access to the memory location is allowed.
摘要翻译：实施例包括处理系统（110），其基于存储在第一寄存器（132,212）中的指令地址范围指示符来确定（308）下一个指令获取地址是否对应于第一存储器区域内的位置（216,218））与当前特权状态相关联或在与不同特权状态相关联的第二存储器区域（216,218）内。当下一个指令获取地址不在第一存储器区域（216,218）内时，只有当向不同特权状态的转换合法时才允许下一条指令被取出（314）（310）。在另一实施例中，当为指令（316）生成数据访问地址时，基于存储在第二寄存器（133,222）中的数据地址范围指示符，确定（320）是否访问存储器允许与数据访问地址对应的位置。当当前特权状态是允许访问内存位置的权限状态时，允许访问（318）。

3. 发明公开

EP2669807A3 Processor resource and execution protection methods and apparatus 有权
标题翻译：处理器资源和执行保护的方法和装置
公开(公告)号：EP2669807A3
公开(公告)日：2014-03-19
申请号：EP13169521.5
申请日：2013-05-28
申请人： Freescale Semiconductor, Inc.
发明人： McCarthy, Daniel M. , Circello, Joseph , Hausman, Kirsten A.
IPC分类号： G06F12/14 , G06F9/38 , G06F9/30
CPC分类号： G06F12/1491 , G06F9/30181 , G06F9/30189 , G06F9/321 , G06F9/3802 , G06F9/3804 , G06F12/023 , G06F12/1441 , G06F2212/1044 , G06F2212/1052
摘要： Embodiments include processing systems (110) that determine (308), based on an instruction address range indicator stored in a first register (132, 212), whether a next instruction fetch address corresponds to a location within a first memory region (216, 218) associated with a current privilege state or within a second memory region (216, 218) associated with a different privilege state. When the next instruction fetch address is not within the first memory region (216, 218), the next instruction is allowed to be fetched (314) only when a transition to the different privilege state is legal (310). In a further embodiment, when a data access address is generated for an instruction (316), a determination is made (320), based on a data address range indicator stored in a second register (133, 222), whether access to a memory location corresponding to the data access address is allowed. The access is allowed (318) when the current privilege state is a privilege state in which access to the memory location is allowed.

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