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11. 发明公开

EP0142298A2 Calibration apparatus for systems such as analog to digital converters 失效
标题翻译： EichgerätfürSysteme，所以al-AD-Wandler。
公开(公告)号：EP0142298A2
公开(公告)日：1985-05-22
申请号：EP84307269.5
申请日：1984-10-22
申请人： JOHN FLUKE MFG. CO., INC.
发明人： Duryee, Peter Schuyler , Anholm, John Milford, Jr.
IPC分类号： H03M1/40
CPC分类号： H03M1/069 , H03M1/403
摘要： A calibration circuit for a recirculation of remainder analog-to-digital (A/D) converter heuristically solves a multi- plevariable conversion equation. Input analog calibration and analog reference signals are compared in a comparator (40), and when the two signals have a predetermined relationship, the comparator (40) generates an indicator signal. A microprocessor (15) determines (a) a first pattern of digital reference signals that, together with digital calibration signals generated by the microprocessor, causes the comparator (40) to generate the indicator signal and (b) a second pattern of digital reference signalsthat,together with the inputanalog calibration signals, causes the comparator to generate the indicator signal. The difference between the first and second patterns of digital reference signals is stored as conversion coefficients.
摘要翻译：用于余数模数（A / D）转换器的再循环的校准电路启发式地求解多变量转换方程。输入模拟校正和模拟参考信号在比较器（40）中进行比较，当两个信号具有预定的关系时，比较器（40）产生指示信号。微处理器（15）确定（a）数字参考信号的第一模式，连同由微处理器产生的数字校准信号一起使得比较器（40）产生指示信号，和（b）第二模式的数字参考信号与输入模拟校准信号一起使比较器产生指示信号。数字参考信号的第一和第二模式之间的差被存储为转换系数。

12. 发明授权

EP4258554B1 DISCRETE-TIME OFFSET CORRECTION CIRCUIT EMBEDDED IN A RESIDUE AMPLIFIER IN A PIPELINED ANALOG-TO-DIGITAL CONVERTER (ADC) 有权
公开(公告)号：EP4258554B1
公开(公告)日：2024-09-04
申请号：EP22198554.2
申请日：2022-09-28
IPC分类号： H03M1/16 , H03M1/40 , H03M1/46
CPC分类号： H03M1/167 , H03M1/403 , H03M1/468

13. 发明公开

EP3343775A1 INTERLEAVING SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER WITH NOISE SHAPING 审中-公开
公开(公告)号：EP3343775A1
公开(公告)日：2018-07-04
申请号：EP17209103.5
申请日：2017-12-20
申请人： MediaTek Inc.
发明人： LIU, Chun-Cheng
IPC分类号： H03M1/08 , H03M1/12 , H03M1/40 , H03M3/00 , H03M1/46
CPC分类号： H03M1/0854 , H03M1/12 , H03M1/1215 , H03M1/38 , H03M1/403 , H03M1/462 , H03M1/468
摘要： An interleaving successive approximation analog-to-digital converter (SAR ADC) with noise shaping having a first SAR block, a second SAR block, and a noise-shaping circuit is provided. The first and second SAR blocks take turns to sample an input voltage for successive approximation of the input voltage and observation of a digital representation of the input voltage. The noise-shaping circuit receives a first residue voltage from the first SAR block and receives a second residue voltage from the second SAR block alternately, and outputs a noise-shaping signal to be fed into the first SAR block and the second SAR block.

14. 发明公开

EP2571169A4 A/D CONVERTER 有权
标题翻译：模拟数字转换器
公开(公告)号：EP2571169A4
公开(公告)日：2016-03-16
申请号：EP11780708
申请日：2011-05-13
申请人： UNIV SHIZUOKA NAT UNIV CORP
发明人： KAWAHITO SHOJI
IPC分类号： H03M1/14 , H03M1/16 , H03M1/40 , H03M1/56 , H04N5/357 , H04N5/378
CPC分类号： H03M1/12 , H03M1/145 , H03M1/162 , H03M1/403 , H03M1/56 , H04N5/357 , H04N5/3575 , H04N5/378
摘要： An object is to provide an A/D converter which uses a plurality of A/D converter circuits and can lower the A/D conversion accuracy in the A/D converter circuit for a lower digit by employing a cyclic A/D conversion scheme for an upper digit thereof. An A/D converter 101 comprises a first cyclic A/D converter circuit 103 and an A/D converter circuit 105. The A/D converter 101 includes a record circuit 107 for storing conversion results from the A/D converter circuits 103, 105. The record circuit 107 includes an upper-bit record circuit 107a and a lower-bit circuit 107b. The cyclic A/D converter circuit 103 receives an analog value SA and generates a first digital value SD1 indicating the analog value SA and a residue value RD. The A/D converter circuit 105 receives the residue value RD and generates a second digital value SD2 having lower M bits indicating the residue value RD. The conversion accuracy in the A/D converter circuit 105 can be lowered to 1/2 L that in the A/D converter circuit 103.

15. 发明公开

EP2557693A1 DATA CONVERSION METHOD BASED ON NEGATIVE -MAP 有权
标题翻译：基于在负BETA-MAP数据转换方法
公开(公告)号：EP2557693A1
公开(公告)日：2013-02-13
申请号：EP11765199.2
申请日：2011-03-22
申请人： Japan Science and Technology Agency
发明人： HORIO, Yoshihiko , JINNO, Kenya , KOHDA, Tohru , AIHARA, Kazuyuki
IPC分类号： H03M1/08
CPC分类号： H03M1/0692 , H03M1/403
摘要： There is provided a data conversion method based on negative β-map suited for an A/D converter or chaos generator, that is adapted to an integrated circuit and capable of providing stable operation of the circuit. The data conversion method based on negative β-map includes a discrete time integrator 1 having an amplification coefficient s and a damping factor β, a quantizer 2 connected in series to the discrete time integrator 1, and a feedback circuit connected from an output of the quantizer 2 to an input of the discrete time integrator 1.

16. 发明授权

EP1759461B1 METHOD OF CYCLICALLY CONVERTING AN ANALOG SIGNAL TO A MULTI-BIT DIGITAL OUTPUT SIGNAL AND CONVERTER FOR PERFORMING THE METHOD 有权
标题翻译： METHOD FOR循环的模拟信号转换成多比特数字输出和变频器用于执行该方法
公开(公告)号：EP1759461B1
公开(公告)日：2008-12-24
申请号：EP05745163.5
申请日：2005-06-08
申请人： NXP B.V.
发明人： KARAVIDAS, Dimitrios , DE CREMOUX, Guillaume , RISTIC, Sasa , CHRISTOFOROU, Yovgos
IPC分类号： H03M1/40
CPC分类号： H03M1/403 , H03M1/1014
摘要： Method and arrangement for cyclically AD converting an analog signal with a sampler capacitance and an integrator capacitance, comprising the steps of generating a difference signal multiplied by the ratio of said capacitances from the analog signal and a reference signal, deriving a digital bit from said difference signal, doubling the difference signal multiplied by said ratio, shifting said doubled signal by the reference signal multiplied by said ratio and using the shifted signal as difference signal multiplied by said ratio for the next cycle.

17. 发明公开

EP0847626A1 DISPOSITIF DE TRAITEMENT NUMERIQUE D'UN SIGNAL ANALOGIQUE DEVANT ETRE RESTITUE SOUS FORME ANALOGIQUE 失效
标题翻译：用于数字信号处理的模拟装置WHO BACK采取模拟形式核发才
公开(公告)号：EP0847626A1
公开(公告)日：1998-06-17
申请号：EP96929325.0
申请日：1996-08-26
申请人： Soprintel S.A.
发明人： HEUBI, Alexandre
IPC分类号： H03M1
CPC分类号： H03M1/667 , H03M1/403
摘要： A device includes a converter implementing a three decision range conversion algorithm involving ternary digital values bi, with bi = 1, 0 or -1. The converter has a reference voltage source (Vr), and computing means (MC; MC-A) for establishing, during each iteration of a series of successive iterations of the algorithm, a voltage value derived from the sum of a value determined on the basis of the voltage calculated at the preceding iteration and a value which is the product of the ternary value obtained during the preceding iteration and said reference voltage. Said computing means include switched capacitors (Cr, C1, C2) connected as a unidirectional assembly and co-operating with a unique operational amplifier (11) providing the voltage value to each of said iterations. The device is particularly useful for hearing aids.

18. 发明公开

EP0709793A2 Semiconductor device and operating device, signal converter, and signal processing system using the semiconductor device 失效
标题翻译： Halbleiterschaltung和ihre Anwendung在einer Operationsschaltung，einem Signalwandler und einem Signalverarbeitungssystem
公开(公告)号：EP0709793A2
公开(公告)日：1996-05-01
申请号：EP95117009.1
申请日：1995-10-27
申请人： CANON KABUSHIKI KAISHA
发明人： Kochi, Tetsunobu, Canon K.K.
IPC分类号： G06J1/00 , H03M1/42 , H03M1/80
CPC分类号： H03M1/403 , G06F7/00 , G06F7/026 , G06F17/15 , G06F2207/025 , G06T7/223 , G06T2207/10016 , H03M1/804
摘要： In a semiconductor device in which one terminal of each of capacitor (2) is connected to a corresponding one of multiple input terminals via switch (3), and the remaining terminals of the capacitor (2) are commonly connected to a sense amplifier (5), the output from the sense amplifier (5) is connected to at least one of the multiple input terminals, thereby reducing the circuit scale, improving the operation speed, and saving the consumption power.
摘要翻译：在半导体器件中，电容器（2）中的每一个的一个端子经由开关（3）连接到多个输入端子中的相应一个，并且电容器（2）的其余端子共同连接到读出放大器（5）），读出放大器（5）的输出端连接到多个输入端子中的至少一个，从而减小电路规模，提高运算速度，节省消耗电力。

19. 发明授权

EP0145312B1 Precision voltage reference for systems such as analog to digital converters 失效
标题翻译：用于数字转换器模拟的系统的精度电压参考
公开(公告)号：EP0145312B1
公开(公告)日：1991-01-16
申请号：EP84307856.9
申请日：1984-11-13
申请人： JOHN FLUKE MFG. CO., INC.
发明人： Eng, Benjamin, Jr.
IPC分类号： G05F3/16
CPC分类号： G05F3/18 , G05F1/56 , H03M1/403 , Y10S323/907

20. 发明授权

EP0145313B1 Bootstrap power regulator for systems such as analog to digital converters 失效
标题翻译：用于系统的BOOTSTRAP功率调节器，如用于数字转换器的模拟
公开(公告)号：EP0145313B1
公开(公告)日：1989-12-27
申请号：EP84307857.7
申请日：1984-11-13
申请人： JOHN FLUKE MFG. CO., INC.
发明人： Eng, Benjamin, Jr.
IPC分类号： G05F1/56
CPC分类号： H03F3/45479 , H03M1/403

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