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11. 发明公开

EP0338251A1 Method of manufacturing metal-semiconductor field effect transistors 失效
标题翻译： Feldeffekttransistoren enthaltendes Bauelement und dessen Herstellungsverfahren。
公开(公告)号：EP0338251A1
公开(公告)日：1989-10-25
申请号：EP89104703.7
申请日：1989-03-16
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Iwasaki, Hiroshi c/o Patent Division K.K. Toshiba
IPC分类号： H01L27/06 , H01L21/82
CPC分类号： H01L29/66878 , H01L21/8252 , H01L27/0611 , H01L29/1029
摘要： A semiconductor device which comprises a semi-insulating substrate (1) and a plurality of field effect transistors (FETs) formed on the semi-insulating substrate (1). An epitaxial layer (2)of one conductivity type is formed on the semi-insulating substrate by a crystal growth technique which is capable of controlling a film thickness at an atomic level. At least some of channel active layers of the FETs have different threshold voltages one another due to a difference in thickness of the epitaxial layer (2) and/or due to an additional ion implantation region selectively formed in the epitaxial layer (2). A manufacturing method of the semiconductor device is also disclosed, wherein a portion of the epitaxial layer (2) corresponding to the channel active layer of a FET is thickened by the repetition of an epitaxial growth, thinned by the etching of the epitaxial layer or ion implanted thereby obtaining a different threshold voltage from that of another FET.
摘要翻译：一种半导体器件，包括半绝缘衬底（1）和形成在半绝缘衬底（1）上的多个场效应晶体管（FET）。通过能够以原子级控制膜厚度的晶体生长技术，在半绝缘基板上形成一种导电类型的外延层（2）。由于外延层（2）的厚度差异和/或由于在外延层（2）中选择性地形成的另外的离子注入区域，FET的至少一些沟道有源层彼此具有不同的阈值电压。还公开了半导体器件的制造方法，其中对应于FET的沟道有源层的外延层（2）的一部分通过外延生长的重复而增厚，通过蚀刻外延层或离子而变薄植入，从而获得与另一FET的阈值电压不同的阈值电压。

12. 发明公开

EP0226106A3 Method of fabricating semiconductor device having low resistance non-alloyed contact layer 失效
标题翻译：制造具有低电阻非合金接触层的半导体器件的方法
公开(公告)号：EP0226106A3
公开(公告)日：1988-03-23
申请号：EP86116617
申请日：1986-11-29
申请人： ALLIED CORPORATION
发明人： Aina, Olaleye Adetoro Allied Corporation , Lakhani, Amir Alimohamed Allied Corporation
IPC分类号： H01L21/265 , H01L21/285
CPC分类号： H01L29/66863 , H01L21/2656 , H01L21/28575 , H01L21/28581 , H01L29/66878 , Y10S148/14 , Y10S438/951
摘要： A method of forming a semiconductor device having a non-alloyed contact (26a,26b) layer. An active region (4) is formed in a substrate (2) and the non-alloyed contact layer (26a,26b) is formed in the active region (4) the barrier height of source and drain electrodes (36,38) for the non-alloyed contact layer (26a,26b) being lower than the barrier height of the source and drain electrodes (36,38) for the active region (4) or the substrate (2). The preferred method of forming the non-alloyed contact layer (26a,26b) is high dose implantation of an element selected in accordance with the substrate (2) material. For example, if the substrate (2) is GaAs the non-alloyed contact layer (26a,26b) is formed by implanting In, and if the substrate (2) is InP the non-alloyed contact layer (26a,26b) is formed by implanting As or Sb.

13. 发明公开

EP0175864A3 Self-aligned metal-semiconductor field effect transistor 失效
标题翻译：自对准的金属半导体场效应晶体管
公开(公告)号：EP0175864A3
公开(公告)日：1986-12-03
申请号：EP85108697
申请日：1985-07-12
申请人： International Business Machines Corporation
发明人： Codella, Christopher Frank , Ogura, Seiki
IPC分类号： H01L29/08 , H01L29/80 , H01L21/265
CPC分类号： H01L29/66878 , H01L29/0891 , H01L29/1075 , H01L29/812 , Y10S257/90
摘要： Disclosed is a self-aligned GaAs, lightly doped drain metal-semiconductor field effect transistor. The device (70) consists of a shallow n- active channel region (53A) formed on a GaAs substrate (50), a Schottky gate (54) overlying the n- region and highly doped and deep n* source (64) and drain (65) regions formed on either side of the gate. In the channel regions between the gate edges and the source/drain regions are positioned n-type source/drain extensions (57A, 58A) which have an intermediate depth and doping concentration to minimize the device series resistance, suppress short channel effects and permit channel length reduction to submicron levels. In addition, p-type pockets (59A, 60A) are provided under the source/drain extensions (57A, 58A) to better control the device threshold voltage and further reduce the channel length.

14. 发明公开

EP0181091A3 Schottky gate field effect transistor and manufacturing method thereof 失效
标题翻译：肖特门式场效应晶体管及其制造方法
公开(公告)号：EP0181091A3
公开(公告)日：1986-11-26
申请号：EP85307110
申请日：1985-10-03
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Terada, Toshiyuki c/o Patent Division K.K. Toshiba , Hirose, Mayumi c/o Patent Division K.K. Toshiba , Ishida, Kenji c/o Patent Division K.K. Toshiba
IPC分类号： H01L29/08 , H01L29/80 , H01L21/265
CPC分类号： H01L29/66878 , H01L29/1029 , H01L29/1075 , H01L29/812
摘要： In a GaAs field effect transistor of the invention, a gate layer (14) is formed on a semi-insulative substrate (10). The gate layer (14) is made of a conductive material forming a Schottky junction between the substrate (10) and the gate layer. Source and drain regions (16, 18) are formed in the substrate (10) to have a first conductivity type. Barrier layers (24, 26) are formed in the substrate (10) to have a second conductivity type. The barrier layers (24, 26) are formed to surround the source and drain regions (16,18), and suppress a current component from leaking from the source and drain regions (16, 18) to the substrate (10) when the field effect transistor is operative.

15. 发明公开

EP0152615A3 Semiconductor device and a method of manufacturing the same 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：EP0152615A3
公开(公告)日：1985-09-25
申请号：EP84116098
申请日：1984-12-21
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Ishii, Tetsuo c/o Patent Division
IPC分类号： H01L29/64 , H01L21/28 , H01L29/80
CPC分类号： H01L29/66878 , H01L21/28132 , H01L21/2815 , H01L21/28593 , H01L29/475 , H01L29/812
摘要： This Schottky barrier gate field effect transistor has N +- type source and drain regions (48, 50) formed in the surface area of a GaAs semi-insulation substrate (30), a channel region (52) formed between the source and drain regions (48, 50), and a gate electrode (47) formed on this channel region (52). Particularly, in this Schottky barrier gate field effect transistor, the gate electrode (47) has a first metal portion (46), which is preferably in Schottky contact with the channel region (52), and a second metal portion (40), which stably affixes to the first metal portion (46). The first and second metal portions (46, 40) are fixed to an insulative portion (44) formed on the channel region (52).
摘要翻译：该肖特基势垒栅场效应晶体管具有形成在GaAs半绝缘衬底（30）的表面区域中的N +型源极和漏极区域（48,50），形成在源极和漏极区域之间的沟道区域（52）以及形成在该沟道区域（52）上的栅电极（47）。特别地，在该肖特基势垒栅场效应晶体管中，栅电极（47）具有优选与沟道区（52）肖特基接触的第一金属部分（46）和第二金属部分（40）稳定地附连到第一金属部分（46）。第一和第二金属部分（46,40）固定到形成在沟道区域（52）上的绝缘部分（44）。

16. 发明授权

EP0055932B1 Schottky gate electrode for a compound semiconductor device, and method of manufacturing it 失效
标题翻译：用于化合物半导体器件的肖特基门电极及其制造方法
公开(公告)号：EP0055932B1
公开(公告)日：1985-09-11
申请号：EP81306151.2
申请日：1981-12-24
申请人： FUJITSU LIMITED
发明人： Yokoyama, Naoki
IPC分类号： H01L29/64 , H01L21/28
CPC分类号： H01L29/66878 , H01L29/475 , H01L29/80 , H01L29/812

17. 发明公开

EP0152615A2 Semiconductor device and a method of manufacturing the same 失效
标题翻译：肖特基场效应晶体管和方法，用于其生产。
公开(公告)号：EP0152615A2
公开(公告)日：1985-08-28
申请号：EP84116098.9
申请日：1984-12-21
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Ishii, Tetsuo c/o Patent Division
IPC分类号： H01L29/64 , H01L21/28 , H01L29/80
CPC分类号： H01L29/66878 , H01L21/28132 , H01L21/2815 , H01L21/28593 , H01L29/475 , H01L29/812
摘要： This Schottky barrier gate field effect transistor has N +- type source and drain regions (48, 50) formed in the surface area of a GaAs semi-insulation substrate (30), a channel region (52) formed between the source and drain regions (48, 50), and a gate electrode (47) formed on this channel region (52). Particularly, in this Schottky barrier gate field effect transistor, the gate electrode (47) has a first metal portion (46), which is preferably in Schottky contact with the channel region (52), and a second metal portion (40), which stably affixes to the first metal portion (46). The first and second metal portions (46, 40) are fixed to an insulative portion (44) formed on the channel region (52).

18. 发明公开

EP0057605A2 A Schottky-barrier gate field effect transistor and a process for the production of the same 失效
标题翻译：肖特基门-Feldeffekttransistor和Verfahren zu seiner Herstellung。
公开(公告)号：EP0057605A2
公开(公告)日：1982-08-11
申请号：EP82300499.9
申请日：1982-01-29
申请人： SUMITOMO ELECTRIC INDUSTRIES LIMITED
发明人： Kikuchi, Kenichi , Ebata, Toshiki , Iiyama, Michitomo , Hayashi, Hideki
IPC分类号： H01L29/10 , H01L29/80 , H01L21/265
CPC分类号： H01L29/66871 , H01L21/28587 , H01L29/1029 , H01L29/475 , H01L29/66878 , H01L29/812
摘要： This invention is concerned with an improved Schottky-barrier gate field effect transistor, which comprises a semi-insulating semiconductor substrate (21), an active layer (22) formed on the surface of the semi-conductor substrate and a source electrode (23), Schottky-barrier gate electrode (25) and drain electrode (24) formed on the active layer, in which the active layer has a first part (22') having such a thickness as to give a predetermined pinch-off voltage and being formed near the gate electrode (25) and a second part (22") having a substantially similar carrier concentration to that of the first part (22') and a larger thickness than the first part and being formed between the Schottky-barrier gate electrode (25) and source electrode (23), and the upper surfaces of the first part and second part of the active layer are in a same plane.
摘要翻译：本发明涉及一种改进的肖特基势垒场效应晶体管，其包括半绝缘半导体衬底（21），形成在半导体衬底的表面上的有源层（22）和源电极（23），形成在有源层上的肖特基势垒栅电极（25）和漏电极（24），其中有源层具有第一部分（22分钟），该第一部分具有预定的夹断电压并形成靠近栅电极（25）的第二部分（22sec）和与第一部分（22分钟）基本相似的载流子浓度的第二部分（22秒），并且具有比第一部分更大的厚度，并形成在肖特基势垒栅电极 25）和源电极（23），并且第一部分和第二部分的上表面的有源层处于同一平面。

19. 发明公开

EP0710989A3 Field-effect transistor and method of producing same 失效
标题翻译：场效应晶体管和其制备方法
公开(公告)号：EP0710989A3
公开(公告)日：1998-07-01
申请号：EP95117280
申请日：1995-11-02
申请人： TOYOTA MOTOR CO LTD
发明人： OHNISHI TOYOKAZU
IPC分类号： H01L29/872 , H01L21/265 , H01L21/28 , H01L21/285 , H01L21/338 , H01L29/08 , H01L29/423 , H01L29/47 , H01L29/812 , H01L21/335
CPC分类号： H01L29/66878 , H01L21/2815 , H01L21/28587 , H01L29/0891 , H01L29/42316
摘要： A field-effect transistor has its gate length made to be minute, and a short channel effect is prevented. The field-effect transistor which attains the above objects has first and second semiconductor regions having different impurity concentrations disposed so as to be adjacent to each other. A source electrode (38) is disposed on the second semiconductor region (30) with a high impurity concentration, a drain electrode (40) on the first semiconductor region (20) with a low impurity concentration, and a gate electrode (26) on the first semiconductor region (20) side of the second semiconductor region (30). To produce the above field-effect transistor, a production method comprises a step of forming a first semiconductor region (20) on the major surface of a semiconductor substrate, a step of forming a gate electrode (26) to divide the first semiconductor region, and a step of doping impurities in the first semiconductor region (20) on one side of the gate electrode (26) with the gate electrode (26) as the mask, to form a second semiconductor region (30) which is of the same conductive type with the first semiconductor region (20) and has a different impurity concentration from the first semiconductor region (20).

20. 发明公开

EP0649167A3 Method of manufacturing an ohmic electrode having a multi-layered structure 失效
标题翻译：一种制备电阻电极的具有多层结构的方法。
公开(公告)号：EP0649167A3
公开(公告)日：1997-09-24
申请号：EP94114616.9
申请日：1994-09-16
申请人： SONY CORPORATION
发明人： Uchibori, Chihiro, c/o Faculty of Engineering , Murakami, Masanori, c/o Faculty of Engineering , Otsuki, Akira, c/o Faculty of Engineering , Oku, Takeo, c/o Faculty of Engineering , Wada, Masaru, c/o Sony Corporation
IPC分类号： H01L21/285 , H01L29/45 , H01L21/337 , H01L21/338
CPC分类号： H01L29/66924 , H01L21/28575 , H01L21/28581 , H01L29/0891 , H01L29/452 , H01L29/66878
摘要： An ohmic electrode for III-V compound semiconductors such as GaAs semiconductors which has practically satisfactory characteristics is disclosed. A non-single crystal InAs layer, Ni film, WSi film and W film are sequentially deposited on an n + -type GaAs substrate by sputtering, etc. and subsequently patterned by lift-off, etc. to make a multi-layered structure for fabricating ohmic electrodes. The structure is then annealed first at, e.g. 300°C for 30 minutes and next at, e.g. 650°C for one second to fabricate an ohmic electrode.

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