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11. 发明公开

EP1287527A4 PROGRAMMING OF NONVOLATILE MEMORY CELLS 审中-公开
标题翻译： PROGRAMMIERUNG NICHTFL CHTIGER SPEICHERZELLEN
公开(公告)号：EP1287527A4
公开(公告)日：2006-02-08
申请号：EP01929943
申请日：2001-05-03
申请人： SAIFUN SEMICONDUCTORS LTD
发明人： BLOOM ILAN , EITAN BOAZ , COHEN ZEEV , FINZI DAVID , MAAYAN EDUARDO
IPC分类号： G11C5/00 , G11C16/02 , G11C11/56 , G11C16/04 , G11C16/34 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/3481 , G11C11/5671 , G11C16/0475 , G11C16/3454 , G11C16/3468
摘要： A method for programming an NROM cell which includes the steps of applying a drain (VD), a source (VS) and a gate voltage (VG) to the cell and verifying a programmed or a non-programmed state of the cell. If the cell is in the non-programmed state, the method includes the steps of increasing the drain voltage and maintaining the gate voltage at a constant level during at least a part of the step of increasing. The steps of applying, verifying, increasing and maintaining are repeated until the cell reaches the programmed state.
摘要翻译：一种用于对NROM单元进行编程的方法，其包括向单元施加漏极（VD），源极（VS）和栅极电压（VG）并验证单元的编程或未编程状态的步骤。如果单元处于未编程状态，则该方法包括在增加步骤的至少一部分期间增加漏极电压并将栅极电压保持在恒定电平的步骤。重复施加，验证，增加和维护的步骤，直到细胞达到编程状态。

12. 发明公开

EP1227501A3 Programming and erasing methods for an NROM array 审中-公开
标题翻译：编程和擦除方法的NROM存储
公开(公告)号：EP1227501A3
公开(公告)日：2003-07-30
申请号：EP01309290.3
申请日：2001-11-01
申请人： Saifun Semiconductors Ltd.
发明人： Avni, Dror , Eitan, Boaz
IPC分类号： G11C16/34 , G11C16/10 , G11C16/14
CPC分类号： G11C11/5671 , G11C16/0475 , G11C16/10 , G11C16/14 , G11C16/28 , G11C16/3468 , G11C16/3481
摘要： A method for programming and erasing a memory array includes the step of adapting programming or erase pulses to the current state of the memory array. In one embodiment, the step of adapting includes the steps of determining the voltage level of the programming pulse used to program a fast bit of the memory array and setting an initial programming level of the memory array to a level in the general vicinity of the programming level of the fast bit. For erasure, the method includes the steps of determining erase conditions of the erase pulse used to erase a slowly erasing bit of said memory array and setting initial erase conditions of said memory array to the general vicinity of said erase conditions of said slowly erasing bit. In another embodiment of the array, the step of adapting includes the steps of measuring the current threshold level of a bit to within a given range and selecting an incremental voltage level of a next programming or erase pulse for the bit in accordance with the measured current threshold level.

13. 发明授权

EP0863514B1 Low current programming of floating gate memory 失效
标题翻译：低功耗编程浮栅记忆
公开(公告)号：EP0863514B1
公开(公告)日：2003-05-28
申请号：EP98301649.4
申请日：1998-03-05
申请人： Macronix International Co., Ltd.
发明人： Chen, Han-Sung , Shiau, Tzeng-Huei , Lin, Yu-Shen , Tsai, Chung-Cheng , Lin, Jin-Lien , Wan, Ray-Lin , Liu, Yuan-Chang , Hung, Chun Hsiung
IPC分类号： G11C16/06
CPC分类号： G11C16/3486 , G11C16/10 , G11C16/3459 , G11C16/3468

14. 发明公开

EP0763829A2 Method for programming a nonvolatile memory 失效
标题翻译： Verfahren zum programmieren einesnichflüchtigenSpeicher
公开(公告)号：EP0763829A2
公开(公告)日：1997-03-19
申请号：EP96113461.6
申请日：1996-08-22
申请人： LG Semicon Co., Ltd.
发明人： Choi, Woong-Lim
IPC分类号： G11C16/06
CPC分类号： G11C16/3486 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/10 , G11C16/3468 , G11C2211/5624
摘要： A method for programming a nonvolatile memory cell having a control gate (1), a floating gate (2), a drain (5), a sour e (3), and a channel region (4) disposed between the drain (5) and source (3), the method includes the steps of applying a first voltage to the control gate (1) to form an inversion layer in the channel region (4), the first voltage being varied to program at least two threshold levels of the memory cell, applying a second voltage to the drain (5) and a third voltage to the source (3), the second voltage being greater than the third voltage, monitoring a current flowing between the drain (5) and the source (3) during the programming of the at least two threshold levels, and terminating any one of the first voltage, the second voltage, and the third voltage when the monitored current reaches a preset reference current to thereby stop the programming of the at least two threshold levels.
摘要翻译：用于编程具有设置在漏极和源极之间的控制栅极，浮置栅极，漏极，源极和沟道区域的非易失性存储器单元的方法包括：向所述控制栅极施加第一电压以在所述控制栅极，通道区域。改变第一电压以对存储器单元的至少两个阈值电平进行编程。向漏极施加第二电压，向源极施加第三电压，第二电压大于第三电压。在对至少两个阈值电平进行编程期间，监视在漏极和源极之间流动的电流。当监视的电流达到预设的参考电流以停止对至少两个阈值电平的编程时，终止第一电压，第二电压和第三电压中的任何一个。参考电流在至少两个阈值电平的编程期间具有固定值。

15. 发明公开

EP0052566A2 Electrically erasable programmable read-only memory 失效
标题翻译： Elektrischlöschbarer，程式师Festwertspeicher。
公开(公告)号：EP0052566A2
公开(公告)日：1982-05-26
申请号：EP81401794.3
申请日：1981-11-13
申请人： FAIRCHILD CAMERA & INSTRUMENT CORPORATION
发明人： Tickle, Andrew C.
IPC分类号： G11C17/00
CPC分类号： G11C16/3486 , G11C8/12 , G11C16/0408 , G11C16/08 , G11C16/16 , G11C16/3459 , G11C16/3468 , G11C2216/28
摘要： An electrically erasable programmable read-only memory (E 2 PROM) is provided which utilizes an inhibit voltage applied to unselected word lines during writing to prevent writing in unselected rows. In the preferred embodiment, each memory cell of the E 2 PROM array consists of a single floating gate field effect transistor. The E 2 PROM of the present invention provides for row erasure and single bit writing.
摘要翻译：提供了一种电可擦除可编程只读存储器（E2PROM），其在写入期间利用施加到未选择字线的禁止电压以防止在未选择的行中写入。在优选实施例中，E2PROM阵列的每个存储单元由单个浮栅场效应晶体管组成。本发明的E2PROM提供行擦除和单位写入。

16. 发明公开

EP2737483A4 EFFICIENT DATA-STORAGE DEVICES THAT INCLUDE MEMORY ELEMENTS CHARACTERIZED BY POTENTIALLY LARGE SWITCHING LATENCIES 审中-公开
标题翻译：具有潜在的高效的数据存储的设备通过较长时间的延迟开关时间表征存储元件
公开(公告)号：EP2737483A4
公开(公告)日：2015-05-06
申请号：EP11870039
申请日：2011-07-27
申请人： HEWLETT PACKARD DEVELOPMENT CO
发明人： ORDENTLICH ERIK , SEROUSSI GADIEL
IPC分类号： G11C13/00 , G06F11/10 , G11C7/04 , G11C7/10 , G11C7/22 , G11C16/34
CPC分类号： G06F11/10 , G06F11/1008 , G11C7/04 , G11C7/1006 , G11C13/0007 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C16/3468 , G11C2211/5624

17. 发明公开

EP2737482A4 METHOD AND SYSTEM FOR REDUCING WRITE-BUFFER CAPACITIES WITHIN MEMRISTOR-BASED DATA-STORAGE DEVICES 审中-公开
标题翻译：方法和系统用于降低写入缓冲容量AT忆阻器为基础的数据存储
公开(公告)号：EP2737482A4
公开(公告)日：2015-05-06
申请号：EP11869906
申请日：2011-07-27
申请人： HEWLETT PACKARD DEVELOPMENT CO
发明人： ORDENTLICH ERIK , SEROUSSI GADIEL
IPC分类号： G11C13/00 , G06F11/10 , G11C7/10 , G11C16/34
CPC分类号： G06F11/10 , G06F11/1048 , G11C7/1006 , G11C7/1078 , G11C13/0007 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C16/3468 , G11C2211/5624

18. 发明授权

EP2351041B1 PROGRAMMING NON-VOLATILE MEMORY WITH HIGH RESOLUTION VARIABLE INITIAL PROGRAMMING PULSE 有权
标题翻译：非挥发性存储器以高分辨率变量初始编程脉冲编程
公开(公告)号：EP2351041B1
公开(公告)日：2015-01-07
申请号：EP09793147.1
申请日：2009-09-29
申请人： SanDisk Technologies Inc.
发明人： HEMINK, Gerrit, Jan
IPC分类号： G11C11/56 , G11C16/04 , G11C16/10 , G11C16/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3468 , G11C16/3486 , G11C2211/5621 , G11C2211/5648

19. 发明公开

EP2704150A2 Non-volatile memory (NVM) that uses soft programming 审中-公开
标题翻译： NichtflüchtigerSpeicher mit Softprogrammierung
公开(公告)号：EP2704150A2
公开(公告)日：2014-03-05
申请号：EP13179567.6
申请日：2013-08-07
申请人： Freescale Semiconductor, Inc.
发明人： Mu, Fuchen , Wang, Yanzhuo
IPC分类号： G11C16/34
CPC分类号： G11C16/3468
摘要： A semiconductor memory device (10) comprises a memory controller (12), and an array of memory cells (20) coupled to communicate with the memory controller. The memory controller is configured to perform a first soft program operation (56) using first soft program voltages and a first soft program verify level, and determine whether a first charge trapping threshold has been reached (54). When the first charge trapping threshold has been reached, a second soft program operation (56) is performed using second soft program voltages and a second soft program verify level.
摘要翻译：半导体存储器件（10）包括存储器控制器（12）和耦合以与存储器控制器通信的存储器单元阵列（20）。存储器控制器被配置为使用第一软编程电压和第一软程序验证电平来执行第一软编程操作（56），并且确定是否已经达到第一电荷捕获阈值（54）。当达到第一电荷捕获阈值时，使用第二软编程电压和第二软程序验证电平来执行第二软编程操作（56）。

20. 发明公开

EP1622165A3 Non-volatile memory 有权
标题翻译：非易失性存储器
公开(公告)号：EP1622165A3
公开(公告)日：2007-08-29
申请号：EP05077355.5
申请日：2002-08-23
申请人： MICRON TECHNOLOGY, INC.
发明人： Keays, Brady L.
IPC分类号： G11C16/14 , G11C16/34
CPC分类号： G11C16/14 , G11C16/16 , G11C16/344 , G11C16/3468 , G11C2216/18
摘要： A method and apparatus for erase operations of a flash memory block.
In one embodiment, a flash memory device comprising:
a memory array having a plurality of blocks of flash memory cells, wherein the memory cells in each block are arranged in rows;
a controller to control memory operations to the memory array; and
a register coupled to the controller to track the erase status of each row of memory cells.

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