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11. 发明公开

EP1287527A4 PROGRAMMING OF NONVOLATILE MEMORY CELLS 审中-公开
标题翻译： PROGRAMMIERUNG NICHTFL CHTIGER SPEICHERZELLEN
公开(公告)号：EP1287527A4
公开(公告)日：2006-02-08
申请号：EP01929943
申请日：2001-05-03
申请人： SAIFUN SEMICONDUCTORS LTD
发明人： BLOOM ILAN , EITAN BOAZ , COHEN ZEEV , FINZI DAVID , MAAYAN EDUARDO
IPC分类号： G11C5/00 , G11C16/02 , G11C11/56 , G11C16/04 , G11C16/34 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/3481 , G11C11/5671 , G11C16/0475 , G11C16/3454 , G11C16/3468
摘要： A method for programming an NROM cell which includes the steps of applying a drain (VD), a source (VS) and a gate voltage (VG) to the cell and verifying a programmed or a non-programmed state of the cell. If the cell is in the non-programmed state, the method includes the steps of increasing the drain voltage and maintaining the gate voltage at a constant level during at least a part of the step of increasing. The steps of applying, verifying, increasing and maintaining are repeated until the cell reaches the programmed state.
摘要翻译：一种用于对NROM单元进行编程的方法，其包括向单元施加漏极（VD），源极（VS）和栅极电压（VG）并验证单元的编程或未编程状态的步骤。如果单元处于未编程状态，则该方法包括在增加步骤的至少一部分期间增加漏极电压并将栅极电压保持在恒定电平的步骤。重复施加，验证，增加和维护的步骤，直到细胞达到编程状态。

12. 发明公开

EP1227501A3 Programming and erasing methods for an NROM array 审中-公开
标题翻译：编程和擦除方法的NROM存储
公开(公告)号：EP1227501A3
公开(公告)日：2003-07-30
申请号：EP01309290.3
申请日：2001-11-01
申请人： Saifun Semiconductors Ltd.
发明人： Avni, Dror , Eitan, Boaz
IPC分类号： G11C16/34 , G11C16/10 , G11C16/14
CPC分类号： G11C11/5671 , G11C16/0475 , G11C16/10 , G11C16/14 , G11C16/28 , G11C16/3468 , G11C16/3481
摘要： A method for programming and erasing a memory array includes the step of adapting programming or erase pulses to the current state of the memory array. In one embodiment, the step of adapting includes the steps of determining the voltage level of the programming pulse used to program a fast bit of the memory array and setting an initial programming level of the memory array to a level in the general vicinity of the programming level of the fast bit. For erasure, the method includes the steps of determining erase conditions of the erase pulse used to erase a slowly erasing bit of said memory array and setting initial erase conditions of said memory array to the general vicinity of said erase conditions of said slowly erasing bit. In another embodiment of the array, the step of adapting includes the steps of measuring the current threshold level of a bit to within a given range and selecting an incremental voltage level of a next programming or erase pulse for the bit in accordance with the measured current threshold level.

13. 发明授权

EP0863514B1 Low current programming of floating gate memory 失效
标题翻译：低功耗编程浮栅记忆
公开(公告)号：EP0863514B1
公开(公告)日：2003-05-28
申请号：EP98301649.4
申请日：1998-03-05
申请人： Macronix International Co., Ltd.
发明人： Chen, Han-Sung , Shiau, Tzeng-Huei , Lin, Yu-Shen , Tsai, Chung-Cheng , Lin, Jin-Lien , Wan, Ray-Lin , Liu, Yuan-Chang , Hung, Chun Hsiung
IPC分类号： G11C16/06
CPC分类号： G11C16/3486 , G11C16/10 , G11C16/3459 , G11C16/3468

14. 发明公开

EP0763829A2 Method for programming a nonvolatile memory 失效
标题翻译： Verfahren zum programmieren einesnichflüchtigenSpeicher
公开(公告)号：EP0763829A2
公开(公告)日：1997-03-19
申请号：EP96113461.6
申请日：1996-08-22
申请人： LG Semicon Co., Ltd.
发明人： Choi, Woong-Lim
IPC分类号： G11C16/06
CPC分类号： G11C16/3486 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/10 , G11C16/3468 , G11C2211/5624
摘要： A method for programming a nonvolatile memory cell having a control gate (1), a floating gate (2), a drain (5), a sour e (3), and a channel region (4) disposed between the drain (5) and source (3), the method includes the steps of applying a first voltage to the control gate (1) to form an inversion layer in the channel region (4), the first voltage being varied to program at least two threshold levels of the memory cell, applying a second voltage to the drain (5) and a third voltage to the source (3), the second voltage being greater than the third voltage, monitoring a current flowing between the drain (5) and the source (3) during the programming of the at least two threshold levels, and terminating any one of the first voltage, the second voltage, and the third voltage when the monitored current reaches a preset reference current to thereby stop the programming of the at least two threshold levels.
摘要翻译：用于编程具有设置在漏极和源极之间的控制栅极，浮置栅极，漏极，源极和沟道区域的非易失性存储器单元的方法包括：向所述控制栅极施加第一电压以在所述控制栅极，通道区域。改变第一电压以对存储器单元的至少两个阈值电平进行编程。向漏极施加第二电压，向源极施加第三电压，第二电压大于第三电压。在对至少两个阈值电平进行编程期间，监视在漏极和源极之间流动的电流。当监视的电流达到预设的参考电流以停止对至少两个阈值电平的编程时，终止第一电压，第二电压和第三电压中的任何一个。参考电流在至少两个阈值电平的编程期间具有固定值。

15. 发明公开

EP0052566A2 Electrically erasable programmable read-only memory 失效
标题翻译： Elektrischlöschbarer，程式师Festwertspeicher。
公开(公告)号：EP0052566A2
公开(公告)日：1982-05-26
申请号：EP81401794.3
申请日：1981-11-13
申请人： FAIRCHILD CAMERA & INSTRUMENT CORPORATION
发明人： Tickle, Andrew C.
IPC分类号： G11C17/00
CPC分类号： G11C16/3486 , G11C8/12 , G11C16/0408 , G11C16/08 , G11C16/16 , G11C16/3459 , G11C16/3468 , G11C2216/28
摘要： An electrically erasable programmable read-only memory (E 2 PROM) is provided which utilizes an inhibit voltage applied to unselected word lines during writing to prevent writing in unselected rows. In the preferred embodiment, each memory cell of the E 2 PROM array consists of a single floating gate field effect transistor. The E 2 PROM of the present invention provides for row erasure and single bit writing.
摘要翻译：提供了一种电可擦除可编程只读存储器（E2PROM），其在写入期间利用施加到未选择字线的禁止电压以防止在未选择的行中写入。在优选实施例中，E2PROM阵列的每个存储单元由单个浮栅场效应晶体管组成。本发明的E2PROM提供行擦除和单位写入。

16. 发明公开

EP2760026A4 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：不挥发半导体存储器件
公开(公告)号：EP2760026A4
公开(公告)日：2015-03-25
申请号：EP12833384
申请日：2012-09-18
申请人： FLOADIA CORP
发明人： SHINAGAWA YUTAKA , KASAI HIDEO , TANIGUCHI YASUHIRO
IPC分类号： G11C16/04 , G11C16/02 , G11C16/24 , G11C16/34
CPC分类号： H01L27/11517 , G11C16/0416 , G11C16/0483 , G11C16/24 , G11C16/3468

17. 发明公开

EP2737483A1 EFFICIENT DATA-STORAGE DEVICES THAT INCLUDE MEMORY ELEMENTS CHARACTERIZED BY POTENTIALLY LARGE SWITCHING LATENCIES 审中-公开
标题翻译：具有潜在的高效的数据存储的设备通过较长时间的延迟开关时间表征存储元件
公开(公告)号：EP2737483A1
公开(公告)日：2014-06-04
申请号：EP11870039.2
申请日：2011-07-27
申请人： Hewlett-Packard Development Company, L.P.
发明人： ORDENTLICH, Erik , SEROUSSI, Gadiel
IPC分类号： G11C7/10 , G11C7/22
CPC分类号： G06F11/10 , G06F11/1008 , G11C7/04 , G11C7/1006 , G11C13/0007 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C16/3468 , G11C2211/5624
摘要： One example disclosed in the application is an electronic data-storage device comprising one or more arrays of memory elements that each includes a data-storage medium that is switched between two different states by application of a switching-inducing force or gradient to the data-storage medium, a top control element and a bottom control element through which the switching-inducing force or gradient is applied, and a feedback signal. The data-storage device also includes an error-control-coding encoder that encodes received data and a READ/WRITE controller that writes encoded data received from the error-control-coding encoder to a number of memory elements by applying the switching-inducing force to the one or more arrays of memory elements until feedback signals indicate that the WRITE operation has completed or until the switching-inducing force or gradient has been applied for a maximum application time.

18. 发明公开

EP2369593A1 Channel hot electron injection programming method and related device 有权转让
标题翻译： Kanalverfahren mitheißerElektroneinspritzprogrammierung undzugehörigeVorrichtung
公开(公告)号：EP2369593A1
公开(公告)日：2011-09-28
申请号：EP11150599.6
申请日：2011-01-11
申请人： EMemory Technology Inc.
发明人： Chen, Ying-Je , Ting, Yun-Jen , Sun, Wein-Town , Hsiao, Kai-Yuan , Liu, Cheng-Jye
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C16/3468
摘要： A nonvolatile memory device for reducing programming current and improving reliability comprises a memory cell array, a write circuit, and a verification circuit. The memory cell array comprises memory cells (10) arranged at crossing points of a bit-line and word-line matrix of the memory cell array. The write circuit provides multiple variable pulses to each word-line for programming. The multiple variable pulses have predetermined amplitude for keeping gate injection current roughly maximum while lowering conduction current during programming operation. The verification circuit senses variation of the conduction current during the programming operation, and disables the programming operation if the sensed conduction current during the programming operation reaches a predetermined value.
摘要翻译：用于减少编程电流和提高可靠性的非易失性存储器件包括存储单元阵列，写入电路和验证电路。存储单元阵列包括布置在存储单元阵列的位线和字线矩阵的交叉点处的存储单元（10）。写电路为每个字线提供多个可变脉冲进行编程。多个可变脉冲具有预定的幅度，用于在编程操作期间降低导通电流，保持栅极注入电流大致最大。验证电路在编程操作期间感测导通电流的变化，并且如果在编程操作期间感测到的传导电流达到预定值，则禁止编程操作。

19. 发明公开

EP2306463A1 Word line compensation in non-volatile memory erase operations 有权转让
标题翻译： Ausgleich von Wortleitungen在Löschvorgängen在nichtflüchtigenSpeichern
公开(公告)号：EP2306463A1
公开(公告)日：2011-04-06
申请号：EP10012052.6
申请日：2005-12-15
申请人： SanDisk Corporation
发明人： Wan, Jun , Pang, Chan-sui , Lutze, Jeffrey W.
IPC分类号： G11C16/16 , G11C16/04 , G11C16/34
CPC分类号： G11C8/08 , G11C16/0483 , G11C16/16 , G11C16/3468
摘要： Compensation voltage(s) are applied to a non-volatile memory system during erase operations to equalize the erase behavior of memory cells. Compensation voltages can compensate for voltages capacitively coupled to memory cells of a NAND string from other memory cells and/or select gates. A compensation voltage can be applied to one or more memory cells to substantially normalize the erase behavior of the memory cells. A compensation voltage can be applied to end memory cells of a NAND string to equalize their erase behavior with interior memory cells of the NAND string. A compensation voltage can also be applied to interior memory cells to equalize their erase behavior with end memory cells. Additionally, a compensation voltage can be applied to one or more select gates of a NAND string to compensate for voltages coupled to one or more memory cells from the select gate(s). Various compensation voltages can be used.
摘要翻译：在擦除操作期间，将补偿电压施加到非易失性存储器系统以均衡存储器单元的擦除行为。补偿电压可以补偿电容耦合到来自其他存储器单元和/或选择门的NAND串的存储器单元的电压。可以将补偿电压施加到一个或多个存储器单元，以基本上规范化存储器单元的擦除行为。可以将补偿电压施加到NAND串的末端存储单元，以使其与NAND串的内部存储单元的擦除行为相等。还可以将补偿电压施加到内部存储器单元，以使其与末端存储器单元的擦除行为相等。另外，补偿电压可以施加到NAND串的一个或多个选择栅极，以补偿耦合到来自选择栅极的一个或多个存储器单元的电压。可以使用各种补偿电压。

20. 发明授权

EP1788582B1 ERASING METHOD FOR NONVOLATILE STORAGE, AND NONVOLATILE STORAGE 有权
标题翻译：灭火方法的非易失性存储器以及非易失性存储器
公开(公告)号：EP1788582B1
公开(公告)日：2010-04-28
申请号：EP04772442.2
申请日：2004-08-30
申请人： Spansion LLc , Spansion Japan Limited
发明人： TAOKA, Hideho, SPANSION JAPAN LIMITED , SUZUMURA, Yoshihiro, SPANSION JAPAN LIMITED , HIRANO, Kanji, SPANSION JAPAN LIMITED , KAWAMOTO, Satoru, SPANSION JAPAN LIMITED
IPC分类号： G11C16/34
CPC分类号： G11C16/16 , G11C16/107 , G11C16/3409 , G11C16/3445 , G11C16/3468 , G11C2216/18

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