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11. 发明授权

EP1653374B1 Method and apparatus for coordinating memory operations among diversely-located memory components 有权
标题翻译：用于协调不同布置的存储元件之间的存储器操作的方法和装置
公开(公告)号：EP1653374B1
公开(公告)日：2010-01-06
申请号：EP05022021.9
申请日：2002-04-23
申请人： Rambus, Inc.
发明人： Ware, Frederick A. , Tsern, Ely K. , Perego, Richard E. , Hampel, Craig E.
IPC分类号： G06F13/16
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A specific address and control bus, and a data bus (108), are connected to a memory controller (102) and a memory module (103). The data bus using differential signaling, has symbol time lesser than specific address and control bus symbol time.

12. 发明公开

EP1653374A3 Method and apparatus for coordinating memory operations among diversely-located memory components 有权
标题翻译：用于协调不同布置的存储元件之间的存储器操作的方法和装置
公开(公告)号：EP1653374A3
公开(公告)日：2006-07-26
申请号：EP05022021.9
申请日：2002-04-23
申请人： Rambus, Inc.
发明人： Ware, Frederick A. , Tsern, Ely K. , Perego, Richard E. , Hampel, Craig E.
IPC分类号： G06F13/16
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A method and apparatus for coordinating memory operations among diversely-located memory components is described. In accordance with an embodiment of the invention, wave-pipelining is implemented for an address bus coupled, to a plurality of memory components. The plurality of memory components are configured according to coordinates relating to the address bus propagation delay and the data bus propagation delay. A timing signal associated with address and/or control signals which duplicates the propagation delay of these signals is used to coordinate memory operations.
摘要翻译：一个特定的地址和控制总线和数据总线（108）连接到存储器控制器（102）和存储器模块（103）。使用差分信令数据总线，具有符号时间比特定地址和控制总线符号时间较少。

13. 发明公开

EP1327991A3 Apparatus and method for pipelined memory operations 审中-公开
标题翻译：装置和方法，用于管线式存储器操作
公开(公告)号：EP1327991A3
公开(公告)日：2005-05-11
申请号：EP03001005.2
申请日：1998-09-09
申请人： Rambus Inc.
发明人： Barth, Richard M. , Tsern, Ely K. , Horowitz, Mark A. , Stark, Donald C. , Hampel, Craig E. , Ware, Frederick A. , Dillon, John B.
IPC分类号： G11C7/00 , G06F13/16 , G11C7/10
CPC分类号： G11C7/1039 , G11C7/10
摘要： A memory device has interface circuitry and a memory core which make up the stages of a pipeline, each stage being a step in a universal sequence associated with the memory core. The memory device has a plurality of operation units such as precharge, sense, read and write, which handle the primitive operations of the memory core to which the operation units are coupled. The memory device further includes a plurality of transport units configured to obtain information from external connections specifying an operation for one of the operation units and to transfer data between the memory core and the external connections. The transport units operate concurrently with the operation units as added stages to the pipeline, thereby creating a memory device which operates at high throughput and with low service times under the memory reference stream of common applications.

14. 发明公开

EP1327991A2 Apparatus and method for pipelined memory operations 审中-公开
标题翻译： Vorrichtung und VerfahrenfürPipeline-Speicheroperationen
公开(公告)号：EP1327991A2
公开(公告)日：2003-07-16
申请号：EP03001005.2
申请日：1998-09-09
申请人： Rambus Inc.
发明人： Barth, Richard M. , Tsern, Ely K. , Horowitz, Mark A. , Stark, Donald C. , Hampel, Craig E. , Ware, Frederick A. , Dillon, John B.
IPC分类号： G11C7/10
CPC分类号： G11C7/1039 , G11C7/10
摘要： A memory device has interface circuitry and a memory core which make up the stages of a pipeline, each stage being a step in a universal sequence associated with the memory core. The memory device has a plurality of operation units such as precharge, sense, read and write, which handle the primitive operations of the memory core to which the operation units are coupled. The memory device further includes a plurality of transport units configured to obtain information from external connections specifying an operation for one of the operation units and to transfer data between the memory core and the external connections. The transport units operate concurrently with the operation units as added stages to the pipeline, thereby creating a memory device which operates at high throughput and with low service times under the memory reference stream of common applications.
摘要翻译：存储器件具有构成流水线阶段的接口电路和存储器核心，每个阶段是与存储器核心相关联的通用序列中的步骤。存储器件具有多个操作单元，例如预充电，感测，读和写，其处理操作单元耦合到的存储器核的原始操作。存储装置还包括多个传输单元，其被配置为从外部连接获取信息，指定操作单元之一的操作并且在存储器核心和外部连接之间传送数据。传输单元与操作单元同时运行，作为流水线的附加阶段，从而创建一种在常规应用的存储器参考流下以高吞吐量和低服务时间运行的存储器件。

15. 发明授权

EP3139277B1 METHOD AND APPARATUS FOR COORDINATING MEMORY OPERATIONS AMONG DIVERSELY-LOCATED MEMORY COMPONENTS 有权
公开(公告)号：EP3139277B1
公开(公告)日：2019-11-27
申请号：EP16188273.3
申请日：2002-04-23
申请人： Rambus Inc.
发明人： Ware, Frederick , Tsern, Ely K. , Perego, Richard E. , Hampel, Craig E.
IPC分类号： G06F13/16

16. 发明授权

EP2849075B1 Method and apparatus for coordinating memory operations among diversely-located memory components 有权
标题翻译：用于协调不同布置的存储元件之间的存储器操作的方法和装置
公开(公告)号：EP2849075B1
公开(公告)日：2016-10-19
申请号：EP14196752.1
申请日：2002-04-23
申请人： Rambus Inc.
发明人： Ware, Frederick , Tsern, Ely K. , Perego, Richard E. , Hampel, Craig E.
IPC分类号： G06F13/16
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A specific address and control bus, and a data bus (108), are connected to a memory controller (102) and a memory module (103). The data bus using differential signaling, has symbol time lesser than specific address and control bus symbol time.

17. 发明授权

EP2275943B1 Method and apparatus for coordinating memory operations among diversely-located memory components 有权
标题翻译：用于协调不同布置的存储元件之间的存储器操作的方法和装置
公开(公告)号：EP2275943B1
公开(公告)日：2015-03-11
申请号：EP10179117.6
申请日：2002-04-23
申请人： Rambus Inc.
发明人： Ware, Frederick , Tsern, Ely K. , Perego, Richard E. , Hampel, Craig E.
IPC分类号： G06F13/16
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A specific address and control bus, and a data bus (108), are connected to a memory controller (102) and a memory module (103). The data bus using differential signaling, has symbol time lesser than specific address and control bus symbol time.

18. 发明授权

EP1981033B1 Apparatus and method for pipelined memory operations with write mask 有权
标题翻译：装置和方法，用于与写掩码流水线存储器操作
公开(公告)号：EP1981033B1
公开(公告)日：2011-08-24
申请号：EP08153150.1
申请日：1998-09-09
申请人： Rambus Inc.
发明人： Barth, Richard M. , Tsern, Ely K. , Horowitz, Mark A. , Stark, Donald C. , Hampel, Craig E. , Ware, Frederick A. , Dillon, John B.
IPC分类号： G11C7/00 , G06F13/16 , G11C7/10
CPC分类号： G11C7/1006 , G06F13/1615 , G11C7/10 , G11C7/1039 , G11C8/12 , G11C11/4076

19. 发明授权

EP1253521B1 Method and apparatus for signaling between devices of a memory system 有权
标题翻译：对存储系统的设备之间的信令的方法和装置
公开(公告)号：EP1253521B1
公开(公告)日：2011-01-26
申请号：EP02009031.2
申请日：2002-04-23
申请人： Rambus Inc.
发明人： Ware, Frederick A. , Tsern, Ely K. , Perego, Richard E. , Hampel, Craig E.
IPC分类号： G06F13/16 , G06F13/42
CPC分类号： G06F13/1689 , G11C29/02 , G11C29/028 , G11C29/50008 , G11C29/50012

20. 发明公开

EP1895538A1 Apparatus and method for pipelined memory operations 审中-公开
标题翻译： Vorrichtung und VerfahrenfürPipeline-Speicherbetrieb
公开(公告)号：EP1895538A1
公开(公告)日：2008-03-05
申请号：EP07120842.5
申请日：1998-09-09
申请人： Rambus, Inc.
发明人： Barth, Richard M. , Tsern, Ely K. , Horowitz, Mark A. , Stark, Donald C. , Hampel, Craig E. , Ware, Frederick A. , Dillon, John B.
IPC分类号： G11C7/00 , G06F13/16 , G11C7/10
CPC分类号： G06F13/1615 , G11C7/10 , G11C7/1039
摘要： A memory device has interface circuitry and a memory core which make up the stages of a pipeline, each stage being a step in a universal sequence associated with the memory core. The memory device has a plurality of operation units such as precharge, sense, read and write, which handle the primitive operations of the memory core to which the operation units are coupled. The memory device further includes a plurality of transport units configured to obtain information from external connections specifying an operation for one of the operation units and to transfer data between the memory core and the external connections. The transport units operate concurrently with the operation units as added stages to the pipeline, thereby creating a memory device which operates at high throughput and with low service times under the memory reference stream of common applications.
摘要翻译：存储器件具有构成流水线阶段的接口电路和存储器核心，每个阶段是与存储器核心相关联的通用序列中的步骤。存储器件具有多个操作单元，例如预充电，感测，读和写，其处理操作单元耦合到的存储器核的原始操作。存储装置还包括多个传输单元，其被配置为从外部连接获取信息，指定操作单元之一的操作并且在存储器核心和外部连接之间传送数据。传输单元与操作单元同时运行，作为流水线的附加阶段，从而创建一种在常规应用的存储器参考流下以高吞吐量和低服务时间运行的存储器件。

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