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11. 发明公开

EP2408006A2 Method for forming 3D-interconnect structures with airgaps 有权转让
标题翻译： Verfahren zur Herstellung von 3D-Interconnectstrukturen mit Luftspalten
公开(公告)号：EP2408006A2
公开(公告)日：2012-01-18
申请号：EP11174114.6
申请日：2011-07-15
申请人： IMEC
发明人： Sabuncuoglu Tezcan, Deniz , Civale, Yann , Beyne, Eric
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L21/76898 , H01L21/7682 , H01L23/481 , H01L2224/0401 , H01L2224/05 , H01L2224/13025 , H01L2224/131 , H01L2924/12044 , H01L2924/1461 , H01L2924/014 , H01L2924/00
摘要： Ultra-low capacitance interconnect structures, preferably Through Silicon Via interconnects and methods for fabricating said interconnects are disclosed. The fabrication method comprises the steps of providing a substrate (1) having a first main surface (S1), producing at least one hollow trench-like structure (R1) therein from the first main surface (S1), said trench-like structure surrounding an inner pillar structure (22) of substrate material, depositing a dielectric liner (24) which pinches off said hollow trench-like structure (R1) at the first main surface (S1) such that an airgap is created in the center of hollow trench-like structure (R1) and further creating a TSV hole (23) and filling it at least partly with conductive material.
摘要翻译：公开了超低电容互连结构，优选通过硅通孔互连和用于制造所述互连的方法。该制造方法包括以下步骤：提供具有第一主表面（S1）的基板（1），从第一主表面（S1）至少形成一个中空沟槽状结构（R1），所述沟槽状结构围绕衬底材料的内柱结构（22），沉积在第一主表面（S1）处夹住所述中空沟槽状结构（R1）的电介质衬垫（24），使得在中空沟槽的中心产生气隙（R1），并且进一步产生TSV孔（23）并且至少部分地用导电材料填充TSV孔。

12. 发明公开

EP2339627A1 Window interposed die packaging 审中-公开
标题翻译： Chipverkapselung mit Fenster-Zwischenstück
公开(公告)号：EP2339627A1
公开(公告)日：2011-06-29
申请号：EP09180763.6
申请日：2009-12-24
申请人： IMEC
发明人： Beyne, Eric , Limaye, Paresh
IPC分类号： H01L23/538 , H01L25/065
CPC分类号： H01L23/5389 , H01L21/568 , H01L23/3128 , H01L23/36 , H01L23/562 , H01L24/97 , H01L25/0657 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2224/73253 , H01L2224/81005 , H01L2224/83005 , H01L2224/94 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01016 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01075 , H01L2924/014 , H01L2924/07811 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15787 , H01L2924/15788 , H01L2924/181 , H01L2924/18161 , H01L2924/351 , H01L2924/00 , H01L2224/81 , H01L2224/83
摘要： A semiconductor device is described advantageously making use of the interposer principle. The semiconductor device comprises at least one semiconductor die (130), a window substrate (110) being an inorganic substrate comprising at least one window-shaped cavity (120) for mounting the at least one semiconductor die (130), the window substrate (110) having interconnect structures (140). Furthermore, the at least one semiconductor die is positioned inside the at least one cavity and is connected to the interconnect structures, providing connections to another level of assembly or packaging of the semiconductor device (100). The invention also relates to a method of manufacturing such a semiconductor device.
摘要翻译：利用插入器原理有利地描述了半导体器件。所述半导体器件包括至少一个半导体管芯（130），窗口衬底（110），其是无机衬底，所述无机衬底包括至少一个用于安装所述至少一个半导体管芯（130）的窗形空腔（120），所述窗口衬底 110）具有互连结构（140）。此外，至少一个半导体管芯位于至少一个空腔的内部，并连接到互连结构，提供与半导体器件（100）的另一组装或封装的连接。本发明还涉及一种制造这种半导体器件的方法。

13. 发明授权

EP0742639B1 Microwave oscillator, an antenna therefor and methods of manufacture 失效
标题翻译：微波振荡器天线为此，及其制备方法
公开(公告)号：EP0742639B1
公开(公告)日：2002-07-03
申请号：EP96107063.8
申请日：1996-05-06
申请人： IMEC vzw
发明人： Brebels, Steven , Fobelets, Kristel , Pieters, Philip , Beyne, Eric , Borghs, Gustaaf
IPC分类号： H03B5/18 , H01L27/06
CPC分类号： H01Q23/00 , H01L21/8252 , H01L23/5222 , H01L27/0605 , H01L2223/6627 , H01L2224/45144 , H01L2224/83894 , H01L2924/01079 , H01L2924/01322 , H01L2924/1903 , H01L2924/19032 , H01L2924/3011 , H03B7/08 , H03B9/141 , H01L2924/00

14. 发明公开

EP4391049A1 A MICRO-ELECTRONIC COMPONENT COMBINING POWER DELIVERY AND COOLING FROM THE BACK SIDE 审中-公开
公开(公告)号：EP4391049A1
公开(公告)日：2024-06-26
申请号：EP22216219.0
申请日：2022-12-22
申请人： Imec VZW
发明人： Oprins, Herman , Van der Plas, Geert , Beyne, Eric , Woeltgens, Pieter
IPC分类号： H01L23/528 , H01L23/367 , H01L23/48 , H01L23/535
CPC分类号： H01L23/5286 , H01L23/481 , H01L23/535 , H01L23/473
摘要： A micro-electronic component (1) according to the invention, for example an integrated circuit chip (1), comprises a front-end-of-line (FEOL) portion and a back-end-of-line (BEOL) portion at its front side. A back side power delivery network (PDN) is furthermore present at the back side of the component, with via connections (49) connecting the PDN to the FEOL and BEOL portions. The back side PDN is different from prior art designs, in that it comprises a 'dry part' and a 'wet part' : the dry part includes multiple interconnect levels of the PDN embedded in a dielectric material (57), as known in the art. The 'wet part' comprises the remaining PDN levels which are however not embedded in a dielectric but which are part of a manifold structure configured to receive therein a flow of cooling fluid in order to remove heat generated by the devices in the FEOL portion.

15. 发明授权

EP3171399B1 METHOD FOR SINGULATING A STACK OF SEMICONDUCTOR WAFERS 有权
公开(公告)号：EP3171399B1
公开(公告)日：2020-06-03
申请号：EP15195145.6
申请日：2015-11-18
申请人： IMEC VZW
发明人： De Vos, Joeri , Beyne, Eric
IPC分类号： H01L21/683 , H01L21/768 , H01L21/78 , H01L23/48 , H01L25/065 , H01L21/98

16. 发明公开

EP3640979A1 A METHOD FOR PACKAGING SEMICONDUCTOR DIES 审中-公开
公开(公告)号：EP3640979A1
公开(公告)日：2020-04-22
申请号：EP18200483.8
申请日：2018-10-15
申请人： IMEC vzw
发明人： Beyne, Eric
IPC分类号： H01L23/31 , H01L23/473 , H01L21/56 , H01L23/00
摘要： The invention is related to a method for packaging semiconductor dies (4) by overmolding, wherein the dies are embedded in a substrate of a mold material, and wherein cavities are produced in the mold substrate by producing 3D structures (9) of a sacrificial material prior to the overmolding step. Afterwards, the sacrificial material is removed to thereby create cavities in the mold substrate. According to the invention, 3D structures (8) of a non-sacrificial material are produced which are in contact with the sacrificial structures (9) and which are embedded in the mold substrate together with the sacrificial structures. After removal of the sacrificial structures, complex cavity shapes can thereby be created.

17. 发明授权

EP3029725B1 CHUCK FOR COLLECTIVE BONDING OF SEMICONDUCTOR DIES, METHOD OF MAKING THE SAME AND METHODS OF USING THE SAME 有权
公开(公告)号：EP3029725B1
公开(公告)日：2019-10-30
申请号：EP15185025.2
申请日：2015-09-14
申请人： IMEC VZW
发明人： Wang, Teng , Daily, Robert , Rebibis, Kenneth June , Beyne, Eric
IPC分类号： H01L23/00 , H01L21/67 , H01L21/60

18. 发明公开

EP3293757A1 A METHOD FOR BONDING AND INTERCONNECTING INTEGRATED CIRCUIT DEVICES 审中-公开
标题翻译：一种集成电路器件的结合和互连方法
公开(公告)号：EP3293757A1
公开(公告)日：2018-03-14
申请号：EP16187668.5
申请日：2016-09-07
申请人： IMEC VZW
发明人： Beyne, Eric , De Vos, Joeri , Van Huylenbroeck, Stefaan
IPC分类号： H01L21/768 , H01L23/48 , H01L25/065
CPC分类号： H01L25/0657 , H01L21/3065 , H01L21/76831 , H01L21/76877 , H01L21/76898 , H01L23/481 , H01L24/08 , H01L24/89 , H01L25/50 , H01L2224/08146 , H01L2224/80125 , H01L2224/80895 , H01L2224/80896 , H01L2225/06541 , H01L2225/06565 , H01L2225/06593 , H01L2924/14
摘要： The present invention is related to a method for bonding and interconnecting two or more IC devices (10a,10b) arranged on substrates such as silicon wafers (1a, 1b), wherein the wafers are bonded by a direct bonding technique to form a wafer assembly, and wherein the multiple IC devices are provided with metal contact structures (4a,4b). At least the upper substrate is provided prior to bonding with a cavity (16) in its bonding surface. A TSV (Through Semiconductor Via) (18) is produced through the bonded wafer assembly and an aggregate opening (25,52) is formed comprising the TSV opening (18) and the cavity (16). After the formation of an isolation liner on at least part of the sidewalls of the aggregate opening (i.e. at least on the part where the liner isolates the aggregate opening from semiconductor material), a TSV interconnection plug is produced in the aggregate opening.
摘要翻译：本发明涉及用于将布置在诸如硅晶片（1a，1b）的基板上的两个或更多IC器件（10a，10b）接合和互连的方法，其中晶片通过直接接合技术接合以形成晶片组件并且其中多个IC器件设置有金属接触结构（4a，4b）。在与其结合表面中的空腔（16）结合之前至少提供上基板。通过接合的晶片组件形成TSV（穿透半导体通孔）（18），并形成包括TSV开口（18）和空腔（16）的聚合物开口（25,52）。在聚集体开口的侧壁的至少一部分上（即，至少在衬里将聚集体开口与半导体材料隔离的部分上）形成隔离衬里之后，在聚集体开口中形成TSV互连插塞。

19. 发明公开

EP3035369A1 Plasma treatment method 有权
标题翻译： Plasmabehandlungsverfahren
公开(公告)号：EP3035369A1
公开(公告)日：2016-06-22
申请号：EP14198833.7
申请日：2014-12-18
申请人： IMEC VZW
发明人： Babaei Gavan, Khashayar , Paraschiv, Vasile , Xu, Kaidong , Beyne, Eric
IPC分类号： H01L21/02 , H01L21/768 , H01L21/311
CPC分类号： H01L21/31116 , H01L21/02063 , H01L21/76831 , H01L21/76898
摘要： A plasma treatment method (400) for etching a portion (112) of an isolating layer (106) present on a surface (110) of an opening in a semiconductor structure (100) is provided. The method (400) comprising: providing (402) a semiconductor structure (100) comprising an opening (102) in an external surface (104), wherein the external surface (104) of the semiconductor structure (100) and surfaces (108,110, 114) defining the opening (102) are at least partially covered by the isolating layer (106), introducing (404) a treatment gas to the semiconductor structure (100) and the isolating layer (106), the treatment gas comprising a first component providing forming of a protective polymer during plasma treatment and second component providing etching of the isolating layer (106) during plasma treatment, and treating (406) the semiconductor structure (100) and the isolating layer (106) by inducing a plasma in the treatment gas, such that a protective polymer layer (118) is formed on at least portions (1 06a) of the isolating layer (106) present on the external surface (104) of the semiconductor structure (100) and on at least portions (1 06b) of the isolating layer (106) present on upper portions of sidewalls (114) of the opening (102), thereby protecting the portions (106a, 1 06b) of the isolating layer (106) where the protective polymer layer (118) is being formed, from the plasma, wherein portions (112) of the isolating layer (106) being exposed to the plasma are etched.
摘要翻译：提供了用于蚀刻存在于半导体结构（100）中的开口的表面（110）上的隔离层（106）的部分（112）的等离子体处理方法（400）。所述方法（400）包括：在外表面（104）中提供（402）包括开口（102）的半导体结构（100），其中半导体结构（100）的外表面（104）和表面（108,110，限定开口（102）的至少一部分（114）至少部分地被隔离层（106）覆盖，将处理气体引入（404）到半导体结构（100）和隔离层（106），处理气体包括第一组分在等离子体处理期间提供形成保护性聚合物，并且在等离子体处理期间提供隔离层（106）的蚀刻的第二部件，以及通过在处理中诱导等离子体来处理（406）半导体结构（100）和隔离层（106）气体，使得在半导体结构（100）的外表面（104）上存在的隔离层（106）的至少部分（106a）上形成保护性聚合物层（118），并且至少部分（1 06b）（隔离层 106）存在于开口（102）的侧壁（114）的上部，从而保护形成有保护聚合物层（118）的隔离层（106）的部分（106a，106b）与等离子体，其中暴露于等离子体的隔离层（106）的部分（112）被蚀刻。

20. 发明授权

EP2704187B1 METHOD FOR PRODUCING ELECTRICAL THROUGH HOLE INTERCONNECTS AND corresponding DEVICE 有权
标题翻译：一种用于生产电通孔的和如此制备设备过程
公开(公告)号：EP2704187B1
公开(公告)日：2015-08-19
申请号：EP13194159.3
申请日：2004-04-02
申请人： IMEC
发明人： Beyne, Eric , Labie, Riet
IPC分类号： H01L21/768 , H01L23/48 , H01L23/00 , H01L23/31 , H01L25/065
CPC分类号： H01L21/76898 , H01L21/76831 , H01L23/3114 , H01L23/481 , H01L2224/0401 , H01L2224/05572 , H01L2224/13025 , H01L2224/16 , H01L2924/00014 , H01L2924/0002 , H01L2924/01019 , H01L2924/01057 , H01L2924/01078 , H01L2924/10253 , H01L2924/00 , H01L2924/00012 , H01L2224/05552

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