专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

EP0386337B1 Multistep planarized chemical vapor deposition process 失效转让
标题翻译：多级从气相平坦化化学沉积
公开(公告)号：EP0386337B1
公开(公告)日：1996-03-06
申请号：EP89123195.3
申请日：1989-12-15
申请人： APPLIED MATERIALS INC.
发明人： Maydan, Dan , Wang, David Nin-Kou
IPC分类号： H01L21/311 , H01L21/768
CPC分类号： H01L21/02164 , H01L21/02126 , H01L21/02129 , H01L21/022 , H01L21/02271 , H01L21/02274 , H01L21/31051 , H01L21/31055 , H01L21/31625 , H01L21/76819 , Y10S148/133 , Y10S438/908

12. 发明授权

EP0179665B1 Apparatus and method for magnetron-enhanced plasma-assisted chemical vapor deposition 有权
标题翻译：用于通过一个由磁控管等离子体增强手段从气相化学沉积方法和设备。
公开(公告)号：EP0179665B1
公开(公告)日：1994-12-28
申请号：EP85307699.0
申请日：1985-10-24
申请人： APPLIED MATERIALS, INC.
发明人： Foster, Robert , Wang, David Nin-Kou , Somekh, Sasson , Maydan, Dan
IPC分类号： C23C16/50 , H01J37/32
CPC分类号： H01J37/32623 , C23C16/045 , C23C16/4558 , C23C16/509 , C23C16/517 , H01J37/3266 , H01J37/32935 , H01J2237/3327

13. 发明公开

EP0612861A1 Apparatus and method for magnetron-enhanced plasma-assisted chemical vapor deposition 失效
标题翻译：用于通过一个由磁控管等离子体增强手段从气相化学沉积方法和设备。
公开(公告)号：EP0612861A1
公开(公告)日：1994-08-31
申请号：EP94104745.8
申请日：1985-10-24
申请人： APPLIED MATERIALS, INC.
发明人： Foster, Robert , Wang, David Nin-Kou , Somekh, Sasson , Maydan, Dan
IPC分类号： C23C16/50 , H01J37/32
CPC分类号： H01J37/32623 , C23C16/045 , C23C16/4558 , C23C16/509 , C23C16/517 , H01J37/3266 , H01J37/32935 , H01J2237/3327
摘要： A plasma CVD reactor (30) and associated process use magnetic field (B) enhancement (54-55) to provide high quality, very high deposition rate metal, dielectric and conformal semiconductor films (5). The reactor and process are designed for automated, high-throughput, in-line small dimension VLSI integrated circuit fabrication, and are applicable to multistep in-situ processing.
摘要翻译：等离子体CVD反应器（30）和相关联的过程中使用的磁场（B）增强（54-55），以提供高品质，非常高的沉积速率金属，电介质和半导体保形膜（5）。的反应器和方法被设计用于自动化，高通量，直列小维VLSI集成电路制造，并且适用于多步原位处理。

14. 发明公开

EP0566220A2 Magnetic field enhanced plasma etch reactor 失效
标题翻译： PlasmaätzvorrichtungmitMagnetfeldverstärkung。
公开(公告)号：EP0566220A2
公开(公告)日：1993-10-20
申请号：EP93201991.2
申请日：1987-12-18
申请人： APPLIED MATERIALS, INC.
发明人： Cheng, David , Maydan, Dan , Somekh, Sasson , Stalder, Kenneth R. , Andrews, Dana L. , Chang, Mei , White, John M. , Wong, Jerry Yuen Kui , Zeitlin, Vladimir J. , Wang, David Nin-Kou
IPC分类号： H01J37/32 , H01L21/306 , C23C16/50
CPC分类号： H01L21/67069 , H01J37/32477 , H01J37/32623 , H01J37/32743 , H01J37/32788 , H01J37/32862
摘要： A magnetic field enhanced single wafer plasma etch reactor (60) is disclosed. The features of the reactor include an electrically-controlled stepped magnetic field for providing high rate uniform etching at high pressures; temperature controlled reactor surfaces including heated anode surfaces (walls and gas manifold) and a cooled wafer supporting pedestal/cathode (70,72); and a unitary wafer exchange mechanism (74) comprising wafer lift pins (79) which extend through the pedestal and a wafer clamp ring (78). The lift pins and clamp ring are moved vertically by a one-axis lift mechanism (140) to accept the wafer from a co-operating external robot blade (76), clamp the wafer to the pedestal and return the wafer to the blade. The electrode cooling combines water cooling for the body of the electrode (70) and a thermal conductivity-enhancing gas interface between the wafer and electrode for keeping the wafer surface cooled despite the high power densities applied to the electrode. A gas feed-through device (114, 175, 176) applies the cooling gas to the RF powered electrode (72) without breakdown of the gas. Protective coatings/layers (81,83) of materials such as quartz are provided for surfaces such as the clamp ring and gas manifold. The combination of these features provides a wide pressure regime, high etch rate, high throughput single wafer etcher wich provides uniformity, directionality and selectivity at high gas pressure, operates cleanly and incorporates in-situ self-cleaning capability.
摘要翻译：公开了一种磁场增强型单晶片等离子体蚀刻反应器（60）。反应器的特征包括用于在高压下提供高速均匀蚀刻的电控步进磁场; 温度控制的反应器表面包括加热的阳极表面（壁和气体歧管）和冷却的晶片支撑基座/阴极（70,72）; 以及包括延伸穿过基座的晶片提升销（79）和晶片夹紧环（78）的整体晶片更换机构（74）。提升销和夹紧环通过单轴提升机构（140）垂直移动，以从合作的外部机器人叶片（76）接收晶片，将晶片夹紧到基座并将晶片返回到叶片。电极冷却结合了用于电极（70）的主体的水冷却和晶片和电极之间的热导率增强气体界面，用于保持晶片表面冷却，尽管施加到电极的高功率密度。气体馈通装置（114,175,176）将冷却气体施加到RF供电的电极（72），而不会破坏气体。为诸如夹紧环和气体歧管的表面提供诸如石英的材料的保护涂层/层（81,83）。这些特征的组合提供了广泛的压力方案，高蚀刻速率，高通量单晶硅蚀刻器，其在高气体压力下提供均匀性，方向性和选择性，干净地操作并且并入原位自清洁能力。

15. 发明公开

EP0386337A3 Multistep planarized chemical vapor deposition process 失效转让
标题翻译： MULTISTEP平面化学气相沉积工艺
公开(公告)号：EP0386337A3
公开(公告)日：1991-01-16
申请号：EP89123195.3
申请日：1989-12-15
申请人： APPLIED MATERIALS INC.
发明人： Maydan, Dan , Wang, David Nin-Kou
IPC分类号： H01L21/311 , H01L21/768
CPC分类号： H01L21/02164 , H01L21/02126 , H01L21/02129 , H01L21/022 , H01L21/02271 , H01L21/02274 , H01L21/31051 , H01L21/31055 , H01L21/31625 , H01L21/76819 , Y10S148/133 , Y10S438/908
摘要： An improved planarization process is disclosed which comprises depositing over a patterned integrated circuit structure (2) on a semiconductor wafer (10) a conformal insulation layer (20) by ECR plasma deposition of an insulation materia. The ECR plasma deposition is carried out until the trenches or low regions between adjacent raised portions of the structure are completely filled with insulation material. A planarization layer (30) of a low melting glass material, such as a boron oxide glass, is then formed over the integrated circuit structure (2) to a depth or thickness sufficient to cover the highest portions of the ECR plasma deposited insulation layer (20). This planarization layer (30) is then anisotropically etched back sufficiently to provide a planarized surface on the ECR plasma deposited insulation layer. A further layer (40) of insulation material may then be conventionally CVD deposited over the planarized ECR plasma deposited insulation layer (30) which acts to encapsulate any remaining portions of the planarizing layer (30).

16. 发明公开

EP0386337A2 Multistep planarized chemical vapor deposition process 失效转让
标题翻译： Mehrstufig planarisierte chemische Abscheidung aus der Gasphase。
公开(公告)号：EP0386337A2
公开(公告)日：1990-09-12
申请号：EP89123195.3
申请日：1989-12-15
申请人： APPLIED MATERIALS INC.
发明人： Maydan, Dan , Wang, David Nin-Kou
IPC分类号： H01L21/311 , H01L21/768
CPC分类号： H01L21/02164 , H01L21/02126 , H01L21/02129 , H01L21/022 , H01L21/02271 , H01L21/02274 , H01L21/31051 , H01L21/31055 , H01L21/31625 , H01L21/76819 , Y10S148/133 , Y10S438/908
摘要： An improved planarization process is disclosed which comprises depositing over a patterned integrated circuit structure (2) on a semiconductor wafer (10) a conformal insulation layer (20) by ECR plasma deposition of an insulation materia. The ECR plasma deposition is carried out until the trenches or low regions between adjacent raised portions of the structure are completely filled with insulation material. A planarization layer (30) of a low melting glass material, such as a boron oxide glass, is then formed over the integrated circuit structure (2) to a depth or thickness sufficient to cover the highest portions of the ECR plasma deposited insulation layer (20). This planarization layer (30) is then anisotropically etched back sufficiently to provide a planarized surface on the ECR plasma deposited insulation layer. A further layer (40) of insulation material may then be conventionally CVD deposited over the planarized ECR plasma deposited insulation layer (30) which acts to encapsulate any remaining portions of the planarizing layer (30).
摘要翻译：公开了一种改进的平坦化工艺，其包括通过ECR等离子体沉积绝缘材料在半导体晶片（10）上沉积保形绝缘层（20）上的图案化集成电路结构（2）。执行ECR等离子体沉积，直到结构的相邻凸起部分之间的沟槽或低区域被绝缘材料完全填充。然后，在集成电路结构（2）上形成低熔点玻璃材料（例如氧化硼玻璃）的平坦化层（30），其深度或厚度足以覆盖ECR等离子体沉积绝缘层的最高部分 20）。然后将该平坦化层（30）充分地各向异性地回蚀以在ECR等离子体沉积绝缘层上提供平坦化的表面。然后可以将平均化的ECR等离子体沉积绝缘层（30）上的常规CVD沉积到另外的绝缘材料层（40）上，该隔离层用于封装平坦化层（30）的任何剩余部分。

17. 发明授权

EP0078161B1 Materials and methods for plasma etching of oxides and nitrides of silicon 有权
标题翻译：用于等离子体蚀刻氧化物和硅的氮的材料和方法
公开(公告)号：EP0078161B1
公开(公告)日：1989-08-23
申请号：EP82305616.3
申请日：1982-10-21
申请人： APPLIED MATERIALS, INC.
发明人： Wang, David Nin-Kou , Egitto, Frank D. , Maydan, Dan
IPC分类号： H01L21/306 , H01L21/31 , C23F1/02
CPC分类号： H01L21/31116 , C23F4/00 , Y10S148/131

18. 发明公开

EP0078161A3 Materials and methods for plasma etching of oxides and nitrides of silicon 有权
标题翻译：氧化物和硅氧化物等离子体蚀刻的材料和方法
公开(公告)号：EP0078161A3
公开(公告)日：1985-05-15
申请号：EP82305616
申请日：1982-10-21
申请人： APPLIED MATERIALS, INC.
发明人： Wang, David Nin-Kou , Egitto, Frank D. , Maydan, Dan
IPC分类号： H01L21/306 , H01L21/31 , C23F01/02
CPC分类号： H01L21/31116 , C23F4/00 , Y10S148/131
摘要： A method for etching a layer of inorganic insulating material 55 formed on a semiconductor wafer 50 and containing silicon as the principal metallic element. The method involves disposing a wafer 50 on one of a pair of electrode structures 261 in a closed chamber 260. A reactive gas 266 mixture comprising principally a fluorocarbon gas doped with a preselected quantity of carbon dioxide is supplied to the chamber 260. Radio frequency 263 electrical energy is supplied to one of the electrode structures 261 to create a plasma of the reactive gas mixture for chemically attacking the insulating material 55.

19. 发明公开

EP0689231A3 Process for deposition of a tungsten layer on a semi-conductor wafer 失效
标题翻译： Verfahren zur Abscheidung einer Wolfram-Schicht au e einer Halbleiterscheibe
公开(公告)号：EP0689231A3
公开(公告)日：1997-06-04
申请号：EP95114144.9
申请日：1990-08-24
申请人： APPLIED MATERIALS INC.
发明人： Chang, Mei , Leung, Cissy , Wang, David Nin-Kou , Cheng, David
IPC分类号： H01L21/285
CPC分类号： H01L21/76838 , H01L21/28556 , H01L21/32051 , Y10S148/025
摘要： A process is disclosed for the deposition of a layer of tungsten on a semiconductor wafer in a vacuum chamber wherein the improvement comprises forming an insulating layer on said wafer over an integrated circuit structure formed on said wafer, forming an intermediate layer of titanium nitride over said insulating layer, forming a cvd tungsten nucleation layer over said intermediate layer of titanium nitride, and depositing tungsten on said nucleation layer.
摘要翻译：公开了一种用于在真空室中在半导体晶片上沉积钨层的方法，其中改进包括在氮气存在下在半导体晶片上沉积钨以改善所得到的钨层的表面的反射率; 将真空室保持在约20至760托的压力下，以提高钨的沉积速率，并提高钨表面的反射率; 以及在需要时，在半导体晶片上沉积钨的步骤之前在半导体层上形成成核层的附加步骤，以提高沉积的钨层的均匀性。

20. 发明授权

EP0441653B1 Improvements in process for planarizing an integrated circuit structure using low melting inorganic material 失效
标题翻译：的方法的改进使用具有低熔点的无机材料平坦化的集成电路装置
公开(公告)号：EP0441653B1
公开(公告)日：1996-03-20
申请号：EP91301048.4
申请日：1991-02-08
申请人： APPLIED MATERIALS, INC.
发明人： Marks, Jeffrey , Wang, David Nin-Kou , Law, Kam Shing , Maydan, Dan
IPC分类号： H01L21/311 , H01L21/314 , H01L21/768
CPC分类号： H01L21/31051 , H01L21/3105 , H01L21/31116 , H01L21/31604 , H01L21/76819 , H01L23/3157 , H01L2924/0002 , H01L2924/00

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式