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101. 发明公开

EP1497868A4 STRUCTURE AND METHOD FOR AN EMITTER BALLAST RESISTOR IN AN HBT 审中-公开
标题翻译：结构与程序IN A HBT发射极镇流电阻
公开(公告)号：EP1497868A4
公开(公告)日：2008-07-16
申请号：EP03719526
申请日：2003-04-01
申请人： SKYWORKS SOLUTIONS INC
发明人： HONG KYUSHIK , BURTON RICHARD S , MATINE NOUREDDINE , GREEN DEBORA L , KRUMM CHARLES F
IPC分类号： H01L21/331 , H01L29/73 , H01L29/737
CPC分类号： H01L29/66318 , H01L29/7304 , H01L29/7371
摘要： According to one exemplary embodiment, a heterojunction bipolar transistor (200) comprises an emitter (216). The heterojunction bipolar transistor (200) further comprises a first emitter cap (218) comprising a first high-doped layer (204), a low-doped layer (206), and a second high-doped layer (208), where the first high-doped layer (204) is situated on the emitter (216), the low-doped layer (206) is situated on the first high-doped layer (204), and the second high-doped layer (208) is situated on the low-doped layer (206). The first high-doped layer (204), the low-doped layer (206), and the second high-doped layer (208) form an emitter ballast resistor. According to this exemplary embodiment, the low-doped layer has a thickness and a dopant concentration level such that the resistance of the low-doped layer (206) is substantially independent of the dopant concentration level, but corresponds to the thickness of the low-doped layer (206).

102. 发明公开

EP1459376A4 METHOD AND STRUCTURE FOR A HETEROJUNCTION BIPOLAR TRANSISTOR 审中-公开
标题翻译：方法与结构的异质双极结型晶体管
公开(公告)号：EP1459376A4
公开(公告)日：2007-10-31
申请号：EP02786741
申请日：2002-11-18
申请人： SKYWORKS SOLUTIONS INC
发明人： BURTON RICHARD S , SAMELIS APOSTOLOS , KYUSHIK HONG
IPC分类号： H01L29/737 , H01L21/331 , H01L29/08
CPC分类号： H01L29/0821 , H01L29/66318 , H01L29/7371
摘要： According to one disclosed embodiment, a heavily doped subcollector (210) is formed. Subsequently, a collector (230) is fabricated over the heavily-doped subcollector (210), wherein the collector (230) comprises a medium-doped collector layer (232) adjacent to the subcollector (210) and a low-doped collector layer (234) over the medium-doped collector layer (232). Both the medium-doped collector layer (232) and the low-doped collector layer (234) can comprise gallium-arsenide doped with silicon at between approximately 5x1016 cm-3 and approximately 1x1018 cm-3, and at between approximately 1x1016 cm-3 and approximately 3x1016 cm-3, respectively. Thereafter, a base (212) is grown over the collector (230), and an emitter (214) is deposited over the base (212). The collector (230) of the HBT prevents the depletion region from reaching the subcollector (210) without unduly impeding the expansion of the depletion region. As a result, filamentation in the subcollector (210) is prevented, but the HBT's performance remains optimal.

103. 发明公开

EP1710841A2 Gallium nitride based semiconductor device and method of manufacturing same 审中-公开
标题翻译： Halbleiteranordnung auf Galliumnitrid Basis und Verfahren zur Herstellung
公开(公告)号：EP1710841A2
公开(公告)日：2006-10-11
申请号：EP06007200.6
申请日：2006-04-05
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Sugawara, Hideto c/o Intellectual Prop. Div. , Hongo, Chie c/o Intellectual Prop. Div.
IPC分类号： H01L29/20 , H01L29/205 , H01L29/778 , H01L21/335
CPC分类号： H01L29/7371 , H01L21/02389 , H01L21/02458 , H01L21/0254 , H01L21/02579 , H01L21/0262 , H01L29/2003 , H01L29/207 , H01L29/36 , H01L29/66318 , H01L29/66462 , H01L33/025 , H01L33/305 , H01S5/22 , H01S5/32341
摘要： A gallium nitride based semiconductor device comprises:
a first gallium nitride based semiconductor film (12) doped with magnesium; and a second gallium nitride based semiconductor film (14) provided on the first gallium nitride based semiconductor film and doped with magnesium. The first gallium nitride based semiconductor film (12) has substantially flat distributions of magnesium concentration and hydrogen atom concentration, and the magnesium concentration is higher than the hydrogen atom concentration. The second gallium nitride based semiconductor film (14) has a first region (B) in which the magnesium concentration decreases and the hydrogen atom concentration increases toward the surface, and
the magnesium concentration in the first region is higher than the hydrogen atom concentration in the first region and higher than the magnesium concentration in the first gallium nitride based semiconductor film.
摘要翻译：一种氮化镓基半导体器件包括：掺杂有镁的第一氮化镓基半导体膜（12）以及设置在第一氮化镓基半导体膜上并掺杂有镁的第二氮化镓基半导体膜（14）。第一氮化镓基半导体膜（12）具有镁浓度和氢原子浓度基本平坦的分布，并且镁浓度高于氢原子浓度。第二氮化镓系半导体膜（14）具有第一区域（B），其中镁浓度降低并且氢原子浓度朝向表面增加，并且第一区域中的镁浓度高于第一区域中的氢原子浓度并且高于第一氮化镓基半导体膜中的镁浓度。

104. 发明公开

EP1659634A2 Transistor bipolaire et procédé de fabrication de ce transistor 审中-公开
标题翻译：双极晶体管和Herstellungsverfahren死了晶体管
公开(公告)号：EP1659634A2
公开(公告)日：2006-05-24
申请号：EP05110847.0
申请日：2005-11-17
申请人： ALCATEL
发明人： Blayac, Sylvain , Scavennec, André
IPC分类号： H01L29/737 , H01L21/331 , H01L29/201 , H01L29/205
CPC分类号： H01L29/205 , H01L29/201 , H01L29/66318 , H01L29/7371
摘要： L'invention propose un transistor bipolaire, comprenant un substrat, des couches d'émetteur, de base et de collecteur et, le cas échéant, des couches de contact. La couche de base est en un matériau GaAsSb. Le transistor présente en outre au moins une couche de transition en un matériau GaInP, entre la couche d'émetteur et la couche de base. La présence et la composition de la couche de transition permettent de modeler le dessin de la bande de conduction du transistor de sorte à en optimiser les performances. En outre, la composition de la couche de transition facilite la fabrication par gravure sélective du transistor.
L'invention concerne également un circuit comprenant un transistor bipolaire selon l'invention.
L'invention propose en outre un procédé de fabrication d'un transistor selon l'invention
摘要翻译：双极晶体管包括：（A）磷化铟（InP）材料的衬底; （B）InP材料的收集层; （C）锑砷化镓（GaAsSb）材料的基层; （D）InP材料的发射极层; 和（E）在发射极层和基极层之间的至少一个磷化铟镓（GaInP）材料的过渡层。还包括独立权利要求：（A）并入该晶体管的电路; 和（B）该晶体管的制造。

105. 发明公开

EP1494274A3 Verfahren zur Herstellung von InP-basierten Heterostruktur-Bipolartransistoren auf der Grundlage von III/V-Halbleitern 有权
标题翻译：一种用于基于InP基异质结双极型晶体管的制造的III / V族半导体的基础上处理
公开(公告)号：EP1494274A3
公开(公告)日：2006-03-15
申请号：EP04090232.2
申请日：2004-06-14
申请人： Forschungsverbund Berlin e.V.
发明人： Kim, Seon-Ohk , Würfl, Joachim , Wittrich, Harald
IPC分类号： H01L21/331 , H01L21/3213
CPC分类号： H01L29/66318 , H01L21/28587 , H01L21/28593 , H01L21/30617 , H01L21/32134 , H01L29/045
摘要： Mit bekannten Ätzverfahren beobachtet man beim Herstellungsprozess von Bipolartransistoren ein stark anisotropes, das heißt von der Kristallorientierung abhängiges Ätzverhalten.
Vorgeschlagen wird, dass später wegzuätzende Bereiche des III/V-Halbleitermaterials durch Ionenimplantation gezielt geschädigt und anschließend durch nasschemisches Ätzen entfernt werden. Die damit mögliche dreidimensionale Strukturierung der Halbleitergebiete ermöglicht einen hohen Grad an Designfreiheit.

106. 发明公开

EP1353362A3 Process for fabricating a semiconductor 审中-公开
标题翻译： Halbleiterherstellungsverfahren
公开(公告)号：EP1353362A3
公开(公告)日：2006-03-08
申请号：EP03007967.7
申请日：2003-04-09
申请人： NORTHROP GRUMMAN CORPORATION
发明人： Grundbacher, Ronald W. , Liu, Po-Hsin , Dia, Rosalinda M.
IPC分类号： H01L21/027 , H01L21/331 , H01L21/335
CPC分类号： H01L29/66318 , H01L21/0272 , H01L29/66462
摘要： A process or improving the yield of semiconductors, such as high electron mobility transistors (HEMTs), which are susceptible to damage during conventional metal lift-off techniques. In accordance with an important aspect of the invention, damage to relatively fragile structures, such as submicron dimensioned structures on semiconductors are minimized by utilizing an adhesive tape to peel off undesired metal in close proximity to submicron dimension structures. By using an adhesive tape to peel off undesired metal, damage to submicron dimension structures is minimized thus improving the yield.
摘要翻译：在常规金属剥离技术中易受损害的半导体（例如高电子迁移率晶体管（HEMT））的产率的提高或提高。根据本发明的一个重要方面，通过利用粘合带将非常接近亚微米尺寸结构的不需要的金属剥离，对相对脆弱的结构（例如半导体上的亚微米尺寸的结构）的损坏最小化。通过使用胶带剥离不需要的金属，亚微米尺寸结构的损伤最小化，从而提高产量。

107. 发明公开

EP1291923A3 Heterojunction bipolar transistor and production process therefore 有权
标题翻译：异质结双极型晶体管及其制造方法
公开(公告)号：EP1291923A3
公开(公告)日：2005-04-13
申请号：EP02020240.4
申请日：2002-09-10
申请人： SHARP KABUSHIKI KAISHA
发明人： Fujita, Koichiro , Kishimoto, Katsuhiko , Yamashita, Masaharu
IPC分类号： H01L29/737 , H01L21/331
CPC分类号： H01L29/66318 , H01L29/1004 , H01L29/42304 , H01L29/7371
摘要： A heterojunction bipolar transistor (100) comprising a collector layer (104) of a first conductivity type, a base layer (105) of a second conductivity type, and an emitter layer (107) of the first conductivity type, which are formed on a semiconductor substrate (101) in this order, and further a collector electrode (113) directly or indirectly connected to the collector layer (104), a base electrode (112) directly or indirectly connected to the base layer (105), and an emitter electrode (111) directly or indirectly connected to the emitter layer (107), wherein a semiconductor protecting layer (106) is formed on the base layer (105) and extended outside an edge of the base layer (105), the base electrode (112) is formed on the semiconductor protecting layer (106), and at least a region under the semiconductor protecting layer (106) is filled with an organic insulator (114).

108. 发明公开

EP1191599A3 Interstitial diffusion barrier 审中-公开
标题翻译：间质性扩散阻挡
公开(公告)号：EP1191599A3
公开(公告)日：2004-12-15
申请号：EP01119652.4
申请日：2001-08-21
申请人： Northrop Grumman Corporation
发明人： Chin, Patrick T. , Gutierrez-Aitken, Augusto L. , Kaneshiro, Eric N.
IPC分类号： H01L29/737 , H01L29/08 , H01L21/22
CPC分类号： H01L29/66318 , H01L29/0821 , H01L29/207 , H01L29/7371
摘要： A heterojunction bipolar transistor is doped in the sub-collector layer (20) with phosphorus (24). The presence of the phosphorus causes any interstitial gallium (22) to be bonded (26) to the phosphorus (24) and move to a lattice site. The result is that the interstitial gallium does not diffuse to the base layer and thus does not cause the beryllium to be displaced and diffused. Instead of doping with phosphorus, a layer including phosphorus can also be utilized.

109. 发明公开

EP1468450A1 WIDE BANDGAP BIPOLAR TRANSISTORS 有权
标题翻译：宽带BIPOLAR TRANSISTORS
公开(公告)号：EP1468450A1
公开(公告)日：2004-10-20
申请号：EP02805835.2
申请日：2002-12-23
申请人： Qinetiq Limited
发明人： PHILLIPS, Timothy Jonathan,Qinetiq Limited
IPC分类号： H01L29/10 , H01L29/737
CPC分类号： H01L29/66318 , H01L29/1004 , H01L29/7371
摘要： A bipolar transistor with vertical geometry comprises a base region (1) provided with a base contact (21), emitter and collector regions (2, 3) arranged to extract minority carriers from the base region, and an excluding structure for counteracting entry of minority carriers into the base region via the base contact, wherein the base region has a bandgap of greater than 0.5 eV and a doping level greater than 1017 cm-3. As shown the base includes an excluding heterojunction (4) preventing entry of carriers from the base contact (21), but alternatively the base region could comprise a 'high-low' doping homojunction. The construction shows improved resistance to thermal runaway even in multi-finger transistors. It is particularly useful for high power, high frequency transistors, e.g. base on gallium indium arsenide. The collector region preferably has a heterostructure.
摘要翻译：具有垂直几何形状的双极晶体管包括：具有基极触点（21）的基极区域（1），布置成从基极区域提取少数载流子的发射极和集电极区域（2,3），以及用于抵消少数载流子载流子经由所述基极触点而进入所述基极区域，其中所述基极区域具有大于0.5eV的带隙以及大于1017cm -3的掺杂水平。如图所示，基极包括排除异质结（4），以防止载流子从基极接点（21）进入，但是备选地，基极区可以包括“高低”掺杂同质结。即使在多指晶体管中，该结构也显示出改善的耐热失控性。它对高功率，高频率晶体管例如特别有用。基于镓铟砷。集电极区域优选具有异质结构。

110. 发明公开

EP1464079A1 ION-IMPLANTATION AND SHALLOW ETCHING TO PRODUCE EFFECTIVE EDGE TERMINATION IN HIGH-VOLTAGE HETEROJUNCTION BIPOLAR TRANSISTORS 有权
标题翻译：离子注入表面蚀刻以及用于在HOCHSPANNUNGSBIPOLARTRANSISTOR异质结AN EFFECTIVE ERSEUGUNG RAND财务报表
公开(公告)号：EP1464079A1
公开(公告)日：2004-10-06
申请号：EP03731896.1
申请日：2003-01-10
申请人： Raytheon Company
发明人： HUSSAIN, Tahir,Raytheon Co.2000 E. El Segundo Bl. , MONTES, M.C.Raytheon Co.2000 E. El Segundo Bl.
IPC分类号： H01L21/331 , H01L29/737 , H01L21/76
CPC分类号： H01L29/66318
摘要： A method is provided for improving edge terminations (42) in a semiconductor device (100) while maintaining breakdown voltage of said semiconductor device (100) at or near its theoretical limit. The method comprises: employing ion-implantation (40) to create a compensated region (140) around the semiconductor device (100), fol-lowed by wet chemical etching to form a mesa (114) on the order of 0.2 to 0.3 µm. The method provides a simple but novel approach to fabricate edge terminations (42) in semiconductor devices (100) in general and in devices employing p-n junctions such as in a GaAs heterojunction bipolar transistor (HBT) to achieve near-ideal electrical characteristics at the device edge (42). Instead of traditional edge beveling techniques such as those involving grinding, sandblasting, or mesa-etching using masks, the technique disclosed herein utilizes ion-implantation (40) to create a compensated region (140) around the device (100) and wet chemical etching to make a shallow mesa (114).

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