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91. 发明公开

EP2304819A1 DISPOSITIF MEMOIRE ET MEMOIRE CBRAM A FIABILITE AMELIOREE 有权
公开(公告)号：EP2304819A1
公开(公告)日：2011-04-06
申请号：EP09802497.9
申请日：2009-07-27
申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives
发明人： DRESSLER, Cyril , SOUSA, Véronique
IPC分类号： H01L45/00
CPC分类号： H01L45/1233 , G11C13/0011 , H01L45/085 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/1658 , H01L45/1675
摘要： A memory device including: one inert electrode including an electrically conductive material, a part of at least one material of resistivity higher than that of the material of the inert electrode, positioned around the inert electrode, a solid electrolyte positioned on at least one part of the inert electrode and of the part of electrically insulating material, and including metal ions originating from an ionizable metal part positioned on the solid electrolyte. The ratio between the coefficient of electrical resistivity of the material of resistivity higher than that of the material of the inert electrode and the coefficient of electrical resistivity of the material of the inert electrode is equal to or higher than approximately 100, and the coefficient of thermal conductivity of the electrically insulating material is equal to or higher than approximately 10 W·m−1·K−1.
摘要翻译：一种存储器件，包括：一个惰性电极，包括导电材料，至少一种电阻率高于惰性电极材料电阻率的材料的一部分，位于惰性电极周围，固体电解质位于电极的至少一部分上惰性电极和部分电绝缘材料，并且包括源自位于固体电解质上的可电离金属部分的金属离子。电阻率比惰性电极材料的电阻率系数和惰性电极材料的电阻率系数之间的比率等于或大于约100，并且热系数电绝缘材料的导电率等于或大于约10W·m -1; 1·K -1; 1。

92. 发明公开

EP2279523A1 MEMORY CELLS, MEMORY CELL CONSTRUCTIONS AND MEMORY CELL PROGRAMMING METHODS 有权
标题翻译：电阻变存储器
公开(公告)号：EP2279523A1
公开(公告)日：2011-02-02
申请号：EP09751110.9
申请日：2009-04-29
申请人： Micron Technology, Inc.
发明人： MOULI, Chandra
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L45/145 , G11C11/02 , G11C13/0002 , G11C13/003 , G11C2213/72 , H01L27/101 , H01L27/1021 , H01L27/2418 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/146
摘要： Some embodiments include memory cells including a memory component having a first conductive material, a second conductive material, and an oxide material between the first conductive material and the second conductive material. A resistance of the memory component is configurable via a current conducted from the first conductive material through the oxide material to the second conductive material. Other embodiments include a diode comprising metal and a dielectric material and a memory component connected in series with the diode. The memory component includes a magnetoresistive material and has a resistance that is changeable via a current conducted through the diode and the magnetoresistive material.

93. 发明授权

EP1851809B1 SNSE-BASED LIMITED REPROGRAMMABLE CELL 有权
标题翻译： LIMITED重新编程的细胞上在SNSE BASE
公开(公告)号：EP1851809B1
公开(公告)日：2010-12-22
申请号：EP06735332.6
申请日：2006-02-17
申请人： Micron Technology, Inc.
发明人： CAMPBELL, Kristy, A.
IPC分类号： H01L45/00 , G11C16/02
CPC分类号： H01L45/085 , G11C13/0011 , G11C13/0069 , G11C2013/009 , G11C2213/56 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/1675
摘要： Methods and apparatus for providing a memory device that can be programmed a limited number of times. According to exemplary embodiments, a memory device and its method of formation provide a first electrode, a second electrode and a layer of a chalcogenide or germanium comprising material between the first electrode and the second electrode. The memory device further includes a tin-chalcogenide layer between the chalcogenide or germanium comprising material layer and the second electrode.

94. 发明授权

EP1536474B1 Memory device and storage apparatus 有权
标题翻译：存储器设备和存储设备
公开(公告)号：EP1536474B1
公开(公告)日：2010-05-05
申请号：EP04028129.7
申请日：2004-11-26
申请人： Sony Corporation
发明人： Aratani, Katsuhisa Sony Corporation , Maesaka, Akihiro Sony Corporation , Kouchiyama, Akira Sony Corporation , Tsushima, Tomohito Sony Corporation
IPC分类号： H01L27/10 , H01L27/24 , H01L45/00
CPC分类号： G11C13/0011 , G11C13/0007 , G11C2213/11 , G11C2213/15 , G11C2213/33 , G11C2213/34 , G11C2213/56 , G11C2213/72 , H01L27/2409 , H01L27/2436 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/143 , H01L45/144 , H01L45/145 , H01L45/146 , H01L45/1625
摘要： A memory device 10 has an arrangement in which a memory thin film 4 is sandwiched between first and second electrodes 2 and 6, the memory thin film 6 contains at least rare earth elements, the memory thin film 4 or a layer 3 in contact with the memory thin film 4 contains any one of elements selected from Cu, Ag, Zn and the memory thin film 4 or the layer 3 in contact with the memory thin film 4 contains any one of elements selected from Te, S, Se. The memory device can record and read information with ease stably, and this memory device can be manufactured easily by a relatively simple manufacturing method.

95. 发明公开

EP1780728A3 Electrode structure for use in an integrated circuit 有权
标题翻译：电极结构用在集成电路
公开(公告)号：EP1780728A3
公开(公告)日：2010-03-03
申请号：EP07002959.0
申请日：2002-11-19
申请人： Micron Technology, Inc.
发明人： Moore, John T. , Brooks, Joseph F.
IPC分类号： G11C13/02 , H01L21/768 , H01L23/485 , H01L27/24 , H01L45/00
CPC分类号： H01L24/05 , G11C13/0011 , G11C2213/79 , H01L21/76823 , H01L21/76838 , H01L21/76867 , H01L24/03 , H01L45/085 , H01L45/124 , H01L45/143 , H01L45/1658 , H01L45/1683 , H01L2224/05006 , H01L2224/05546 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01028 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/01057 , H01L2924/01074 , H01L2924/01082 , H01L2924/05042 , H01L2924/13091 , H01L2924/14 , H01L2924/19043 , H01L2924/3011 , Y10S438/957 , H01L2924/00
摘要： A memory cell, comprising:
a first layer (202) of conductive material;
a dielectric layer (204) formed on a surface of the first layer;
an opening (206) formed in the dielectric layer to expose a portion of the surface of the first layer;
a binding layer (210') formed on the dielectric layer and on the exposed portion of the surface of the first layer;
a second layer (212) of conductive material formed on the binding layer;
a layer (214) of doped chalcogenide material formed on the second layer of conductive material; and
a third layer (216') of conductive material formed on the layer of doped chalcogenide material.

96. 发明公开

EP2051309A1 Procede de fabrication d'une memoire CBRAM ayant une fiabilite amelioree 有权
标题翻译： Herstellungsverfahrenfüreinen CBRAM Speicher mit verbesserterZuverlässigkeit
公开(公告)号：EP2051309A1
公开(公告)日：2009-04-22
申请号：EP08166441.9
申请日：2008-10-13
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE
发明人： Sousa, Véronique , Dressler, Cyril
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L45/141 , H01L27/2436 , H01L27/2463 , H01L45/085 , H01L45/1266 , H01L45/128 , H01L45/142 , H01L45/143 , H01L45/1641 , H01L45/1675
摘要： L'invention concerne un procédé de réalisation d'une pluralité de mémoires de type CBRAM, comportant chacune une cellule mémoire en un électrolyte solide de type chalcogénure, une anode, et une cathode, ce procédé comportant la mise en oeuvre d'une sous-couche (30) de matériau de conductivité thermique élevée, supérieure à 1,3W/m/K, qui recouvre l'ensemble des contacts (28), puis la formation, sur ladite sous-couche d'un tricouche (32, 34, 36), comportant une couche de chalcogénure (32), puis une couche d'anode (34), et une couche de deuxièmes contacts (36), et enfin une étape de gravure.
摘要翻译：该方法包括在半导体支撑件（20）上形成绝缘层（22），并在层中形成触点（28）。在层（22）和触点上形成子层（30），其中子层由导热率高于100瓦/米开尔文的材料制成并覆盖触点。在子层上形成具有硫族化物层（32），阳极层（34）和接触层（36）的三层。在位于触点上方的区域之间进行蚀刻处理，以形成彼此电绝缘的各个存储点。

97. 发明公开

EP1908110A2 NONVOLATILE MEMORY CELL COMPRISING SWITCHABLE RESISTOR AND TRANSISTOR 有权转让
标题翻译：与切换电阻，而晶体管非易失性存储器单元
公开(公告)号：EP1908110A2
公开(公告)日：2008-04-09
申请号：EP06774623.0
申请日：2006-07-11
申请人： Sandisk 3D LLC
发明人： SCHEUERLEIN, Roy, E.
IPC分类号： H01L27/24
CPC分类号： H01L45/1233 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C2213/31 , G11C2213/33 , G11C2213/71 , G11C2213/79 , H01L27/2436 , H01L27/2454 , H01L27/2463 , H01L45/085 , H01L45/1266 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/1641 , H01L45/1675
摘要： A rewriteable nonvolatile memory cell is taught comprising a thin film transistor and a switchable resistor memory element in series. The switchable resistor element decreases resistance when subjected to a set voltage magnitude applied in a first direction, and increases resistance when subjected to a reset voltage magnitude applied in a second direction opposite the first. In preferred embodiments the memory cell is formed in an array, preferably a monolithic three dimensional memory array in which multiple memory levels are formed above a single substrate. In preferred embodiments a thin film transistor and a switchable resistor memory element are electrically disposed between a data line and a reference line which are parallel. Preferably a select line extending perpendicular to the data line and reference line controls the transistor.

98. 发明公开

EP1863092A2 Memory device, in particular phase change random access memory, with nanowire transistor and method for fabricating the memory device 审中-公开
标题翻译：存储装置，特别是相变存储器与随机访问，以纳米线晶体管及其制造存储器件的方法
公开(公告)号：EP1863092A2
公开(公告)日：2007-12-05
申请号：EP07008964.4
申请日：2007-05-03
申请人： Qimonda AG
发明人： Seidl, Harald
IPC分类号： H01L27/24
CPC分类号： H01L27/2463 , H01L27/2454 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/143 , H01L45/144 , Y10S977/762 , Y10S977/773 , Y10S977/932 , Y10S977/936
摘要： The invention relates to a memory device, in particular to a resistively switching memory device such as a Phase Change Random Access Memory ("PCRAM"), with a transistor. Further, the invention relates to a method for fabricating a memory device. According to an aspect of the invention, a memory device is provided, comprising at least one nanowire or nanotube or nanofibre access transistor (4). Preferably, the nanowire or nanotube or nanofibre access transistor directly contacts an active switching material (2) of the memory device. According to an additional aspect, a memory device comprises at least one access transistor with a vertically arranged Si nanowire (40).
摘要翻译：本发明涉及存储器设备，尤其涉及一种电阻性开关存储器设备：如相变存储器（“PCRAM”），其中的晶体管。此外，本发明涉及一种用于制造存储器装置的方法。。根据对本发明的方面，提供了一种存储器装置，其包括至少一个纳米线或纳米管或纳米纤维存取晶体管（4）。优选地，有源开关材料的纳米线或纳米管或纳米纤维存取晶体管直接接触（2）的存储器设备。纳米线。据在额外方面中，一种存储器设备包括至少一个存取晶体管与竖直布置的硅（40）。

99. 发明公开

EP1856747A1 METHOD FOR MANUFACTURING AN ELECTROLYTE MATERIAL LAYER IN SEMICONDUCTOR MEMORY DEVICES 审中-公开
标题翻译：方法用于在半导体存储设备的电解质材料层
公开(公告)号：EP1856747A1
公开(公告)日：2007-11-21
申请号：EP06708059.8
申请日：2006-02-07
申请人： Qimonda AG
发明人： PINNOW, Cay-Uwe , UFERT, Klaus-Dieter
IPC分类号： H01L45/00
CPC分类号： H01L45/085 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/146 , H01L45/1616 , H01L45/1625 , H01L45/1641
摘要： The object to develop a nonvolatile resistively switching memory system that can be manufactured on the basis of CMOS technology is solved by the present invention a method for manufacturing an electrolyte material layer with a chalcogenide material incorporated or deposited therein for using in semiconductor memory devices, in particular resistively switching memory devices or components, the method comprising at least the steps of producing a semiconductor substrate, depositing a binary chalcogenide layer onto the semiconductor substrate, depositing a sulfur containing layer onto the binary chalcogenide layer, and creating a ternary chalcogenide layer comprising at least two different chalcogenide compounds ASexSy, wherein one component A of the chalcogenide compounds ASexSy is constituted by materials of the IV elements main group, e.g. Ge, Si or of a transition metal, preferably of the group consisting of Zn, Cd, Hg, or a combination thereof.

100. 发明公开

EP1801898A2 Integrated circuit device and fabrication using metal-doped chalcogenide materials 有权
标题翻译： Integrierte Schaltungsvorrichtung und Herstellung unter Verwendung von metalldotierten Chalkogenidmaterialien
公开(公告)号：EP1801898A2
公开(公告)日：2007-06-27
申请号：EP07006928.1
申请日：2002-08-30
申请人： MICRON TECHNOLOGY, INC.
发明人： Li, Jiutao , McTeer, Allen
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： C23C14/5846 , C23C14/0623 , C23C14/544 , H01L27/2409 , H01L45/085 , H01L45/1233 , H01L45/141 , H01L45/143 , H01L45/1658
摘要： A method of forming a chalcogenide memory element having a first electrode, a second electrode, and a doped chalcogenide layer interposed between the first electrode and the second electrode, the method comprising:
forming a chalcogenide layer on the first electrode;
sputtering metal onto the chalcogenide layer using a first plasma containing at least one component gas selected from the group consisting of neon and helium,
thereby forming the doped chalcogenide layer, wherein the first plasma emits a UV component sufficient to induce diffusion of the sputtered metal into the chalcogenide layer; and
sputtering metal onto the doped chalcogenide layer using a second plasma containing at least one component gas having an atomic weight higher than an atomic weight of neon, thereby forming the second electrode.
摘要翻译：一种形成具有第一电极，第二电极和插入在第一电极和第二电极之间的掺杂硫族化物层的硫族化物存储元件的方法，所述方法包括：在所述第一电极（210）上形成硫族化物层（215） ; 使用包含选自氖和氦中的至少一种成分气体的第一等离子体将溅射金属（240）溅射到硫族化物层上，从而形成掺杂的硫族化物层（230），其中第一等离子体发射足以诱导将溅射的金属扩散到硫族化物层中; 以及使用具有原子量高于氖原子量的至少一种组分气体的第二等离子体将溅射金属（245）涂覆到掺杂的硫族化物层上，从而形成第二电极（250）。

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