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91. 发明公开

EP1884999A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：EP1884999A1
公开(公告)日：2008-02-06
申请号：EP06756859.2
申请日：2006-05-25
申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA
发明人： SUGIMOTO, Masahiro, TOYOTA JIDOSHA K.K. , KACHI, Tetsu, K.K. TOYOTA CHUO KENKYUSHO , UESUGI, Tsutomu, K.K. TOYOTA CHUO KENKYUSHO , UEDA, Hiroyuki, K.K. TOYOTA CHUO KENKYUSHO , SOEJIMA, Narumasa, K.K. TOYOTA CHUO KENKYUSHO
IPC分类号： H01L29/12 , H01L21/336 , H01L29/78 , H01L29/786
CPC分类号： H01L29/207 , H01L29/0623 , H01L29/0649 , H01L29/0653 , H01L29/2003 , H01L29/66462 , H01L29/7787 , H01L29/7788 , H01L29/7828 , H01L29/7832
摘要： The present invention aims to suppress the diffusion of p-type impurities (typically magnesium), included in a semiconductor region of a III-V compound semiconductor, into an adjoining different semiconductor region. A semiconductor device 10 of the present invention comprises a first semiconductor region 28 of gallium nitride (GaN) including p-type impurities that consist of magnesium, a second semiconductor region 34 of gallium nitride, and an impurity diffusion suppression layer 32 of silicon oxide (SiO 2 ) located between the first semiconductor region 28 and the second semiconductor region 34.
摘要翻译：本发明旨在抑制包含在III-V族化合物半导体的半导体区中的p型杂质（通常为镁）扩散到邻接的不同半导体区中。本发明的半导体装置10包括由镁构成的p型杂质的氮化镓（GaN）的第一半导体区域28，氮化镓的第二半导体区域34和氧化硅的杂质扩散抑制层32 SiO2）位于第一半导体区域28和第二半导体区域34之间。

92. 发明公开

EP1803159A2 MOS-GATED TRANSISTOR WITH REDUCED MILLER CAPACITANCE 有权
标题翻译：能力降低MILLER MOS栅极晶体管
公开(公告)号：EP1803159A2
公开(公告)日：2007-07-04
申请号：EP05802949.7
申请日：2005-10-04
申请人： Fairchild Semiconductor Corporation
发明人： SHENOY, Praveen, Muraleedharan , KOCON, Christopher, Boguslaw
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/7813 , H01L29/0623 , H01L29/0696 , H01L29/1095 , H01L29/66734
摘要： A trench MOS-gated transistor is formed as follows. A first region of a first conductivity type is provided. A well region of a second conductivity type is then formed in an upper portion of the first region. A trench is formed which extends through the well region and terminates within the first region. Dopants of the second conductivity type are implanted along predefined portions of the bottom of the trench to form regions along the bottom of the trench which are contiguous with the well region such that when the transistor is in an on state the deeper portion of the well region prevents a current from flowing through those channel region portions located directly above the deeper portion of the well region.

93. 发明公开

EP1745517A2 INSULATED GATE SEMICONDUCTOR DEVICE 有权
标题翻译：半导体绝缘栅
公开(公告)号：EP1745517A2
公开(公告)日：2007-01-24
申请号：EP05740925.2
申请日：2005-05-11
申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA , DENSO CORPORATION
发明人： TAKAYA, Hidefumi; TOYOTA JIDOSHA KABUSHIKI KAISHA , OKURA, Yasushi; c/o DENSO CORPORATION, , KUROYANAGI, Akira; c/o DENSO CORPORATION, , TOKURA, Norihito; c/o DENSO CORPORATION,
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0623 , H01L29/0653 , H01L29/42368 , H01L29/4238 , H01L29/7811
摘要： The present invention provides an insulated gate semiconductor device which has floating regions around the bottoms of trenches and which is capable of reliably achieving a high withstand voltage. An insulated gate semiconductor device 100 includes a cell area through which current flows and an terminal area which surrounds the cell area. The semiconductor device 100 also has a plurality of gate trenches 21 in the cell area and a plurality of terminal trenches 62 in the terminal area. The gate trenches 21 are formed in a striped shape, and the terminal trenches 62 are formed concentrically. In the semiconductor device 100, the gate trenches 21 and the terminal trenches 62 are positioned in a manner that spacings between the ends of the gate trenches 21 and the side of the terminal trench 62 are uniform. That is, the length of the gate trenches 21 is adjusted according to the curvature of the corners of the terminal trench 62.

94. 发明公开

EP1671374A2 INSULATED GATE TYPE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 失效转让
标题翻译：与绝缘栅型半导体组件类型及其制造方法
公开(公告)号：EP1671374A2
公开(公告)日：2006-06-21
申请号：EP04792407.1
申请日：2004-10-06
申请人： Toyota Jidosha Kabushiki Kaisha , DENSO CORPORATION
发明人： TAKAYA, Hidefumi, Toyota Jidosha Kabushiki Kaisha , HAMADA, Kimimori, Toyota Jidosha Kabushiki Kaisha , KUROYANAGI, Akira, Denso Corporation , OKURA, Yasushi, Denso Corporation , TOKURA, Norihito, Denso Corporation
IPC分类号： H01L29/78 , H01L29/06 , H01L21/336 , H01L29/423
CPC分类号： H01L29/7813 , H01L29/0623 , H01L29/0634 , H01L29/0653 , H01L29/42368 , H01L29/7397 , H01L29/7811
摘要： The invention is intended to present an insulated gate type semiconductor device that can be manufactured easily and its manufacturing method while realizing both higher withstand voltage design and lower on-resistance design. The semiconductor device comprises N+ source region 31, N+ drain region 11, P- body region 41, and N- drift region 12. By excavating part of the upper side of the semiconductor device, a gate trench 21 is formed. The gate trench 21 incorporates the gate electrode 22. A P floating region 51 is provided beneath the gate trench 21. A further trench 35 differing in depth from the gate trench 21 may be formed, a P floating region 54 being provided beneath the trench 25.

95. 发明授权

EP0795911B1 Insulated gate semiconductor device and manufacturing method thereof 失效
标题翻译：一种半导体器件，包括其制备绝缘栅和过程
公开(公告)号：EP0795911B1
公开(公告)日：2005-04-13
申请号：EP96119114.5
申请日：1996-11-28
申请人： MITSUBISHI DENKI KABUSHIKI KAISHA
发明人： Takahashi, Hideki
IPC分类号： H01L29/739 , H01L21/331 , H01L29/06 , H01L29/10
CPC分类号： H01L29/0696 , H01L29/0623 , H01L29/0847 , H01L29/66348 , H01L29/7397
摘要： An insulated gate semiconductor device includes an N layer (43) having an impurity concentration higher than that of an N layer (42) formed between the N layer (42) and a P base layer (44). In the exposed surface of the P base layer (44) connected to an emitter electrode (51), a P layer (91) having an impurity concentration higher than that of the P base layer (44) is formed. The formation of the N layer (43) allows the carrier distribution in the N layer (42) to be close to the carrier distribution of a diode, so that the on-state voltage is decreased while maintaining high the current value capable of turn-off. Furthermore, the P layer (91) allows holes to easily go through from the P base layer (44) to the emitter electrode (51), which increases the current value capable of turn-off.

96. 发明公开

EP1507294A2 Semiconductor device with surrounding gate 审中-公开
标题翻译： Halbleiterbauelement mit umschliessendem门
公开(公告)号：EP1507294A2
公开(公告)日：2005-02-16
申请号：EP04254361.1
申请日：2004-07-21
申请人： Masuoka, Fujio , Sharp Kabushiki Kaisha
发明人： Masuoka, Fujio , Horii, Shinji , Tanigami, Takuji , Yokoyama, Takashi , Takeuchi, Noboru
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L21/26586 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11556 , H01L29/0623 , H01L29/0646 , H01L29/0649 , H01L29/0657 , H01L29/42384 , H01L29/42392 , H01L29/66484 , H01L29/66666 , H01L29/66742 , H01L29/66825 , H01L29/66833 , H01L29/7828 , H01L29/78642 , H01L29/78648 , H01L29/78696
摘要： A semiconductor device comprising a memory cell which includes: a pillar-shaped semiconductor layer of a first conductive type formed on a semiconductor substrate; source and drain diffusion layers of a second conductive type formed in upper and lower portions of the pillar-shaped semiconductor layer; a semiconductor layer of the second conductive type or a cavity formed inside the pillar-shaped semiconductor layer; and a gate electrode formed on a side face of the pillar-shaped semiconductor layer via a gate insulating film, or a control gate electrode formed on the side face of the pillar-shaped semiconductor layer via a charge accumulation layer.
摘要翻译：一种包括存储单元的半导体器件，包括：药丸

97. 发明公开

EP1408554A2 Durch Feldeffekt steuerbares Halbleiterbauelement 失效
标题翻译：场效应可控半导体元件
公开(公告)号：EP1408554A2
公开(公告)日：2004-04-14
申请号：EP03026265.3
申请日：1997-01-30
申请人： Infineon Technologies AG
发明人： Tihanyi, Jenö , Strack, Helmut , Geiger, Heinrich
IPC分类号： H01L29/78 , H01L29/739 , H01L29/06
CPC分类号： H01L29/7811 , H01L21/2257 , H01L29/0623 , H01L29/0634 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/66333 , H01L29/66712 , H01L29/7395 , H01L29/7396 , H01L29/7802 , H01L29/7835
摘要： Die Erfindung betrifft ein durch Feldeffekt steuerbares Halbleiterbauelement in vertikaler oder lateraler Bauweise, d.h. MOSFETs und IGBTs. In die Source-Drain-Laststrecke werden dabei in den Halbleiterkörper, d.h. bei vertikalen Bauelementen in die Innenzone und bei lateralen Bauelementen in die Driftzone Ausräumzonen und Komplementärausräumzonen entgegengesetzter Leitungstypen eingebracht, wobei die Konzentration der vom ersten Leitungstyp dotierten Bereiche in etwa der Konzentration der vom zweiten Leitungstyp dotierten Bereiche entspricht.
摘要翻译：本发明涉及一种可控制的由场效应半导体器件在垂直结构中，即 MOSFET和IGBT。有，在半导体主体在作为源极 - 漏极负载路径引入内区（92），耗尽区（95,95 *）和互补（96,96 *）相反的导电类型，其中掺杂的第一导电类型区的掺杂剂大约为总量的总量对应于所述掺杂的第二导电类型区域的掺杂，本发明的半导体装置的特征在于耗尽区被布置成在其边缘区域和耗尽区和互补的。

98. 发明授权

EP1039548B1 Durch Feldeffekt steuerbares Halbleiterbauelement 失效
标题翻译：场效应可控半导体元件
公开(公告)号：EP1039548B1
公开(公告)日：2004-03-31
申请号：EP00112818.0
申请日：1997-01-30
申请人： Infineon Technologies AG
发明人： Tihanyi, Jenö , Strack, Helmut , Geiger, Heinrich
IPC分类号： H01L29/78 , H01L29/739 , H01L21/336 , H01L21/331 , H01L29/06
CPC分类号： H01L29/7811 , H01L21/2257 , H01L29/0623 , H01L29/0634 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/66333 , H01L29/66712 , H01L29/7395 , H01L29/7396 , H01L29/7802 , H01L29/7835

99. 发明公开

EP1396890A1 LATERAL JUNCTION TYPE FIELD EFFECT TRANSISTOR 有权
标题翻译： FELDEFFEKTTRANSISTOR DES LATERAL-SPERRSCHICHTTYPS
公开(公告)号：EP1396890A1
公开(公告)日：2004-03-10
申请号：EP02736054.4
申请日：2002-06-11
申请人： Sumitomo Electric Industries, Ltd.
发明人： HARADA, Shin, c/o Osaka Works of SUMITOMO ELECTRIC , HIROTSU, Kenichi, c/o Osaka Works of SUMITOMO , MATSUNAMI, Hiroyuki , KIMOTO, Tsunenobu
IPC分类号： H01L29/808
CPC分类号： H01L29/808 , H01L29/0623 , H01L29/1066 , H01L29/1608
摘要： A lateral JFET has a basic structure including an n-type semiconductor layer (3) formed of an n-type impurity region and a p-type semiconductor layer formed of a p-type impurity region on the n-type semiconductor layer (3). Moreover, in the p-type semiconductor layer, there are provided a p + -type gate region layer (7) extending into the n-type semiconductor layer (3) and containing p-type impurities of an impurity concentration higher than that of the n-type semiconductor layer (3) and an n + -type drain region layer (9) spaced from the p + -type gate region layer (7) by a predetermined distance and containing n-type impurities of an impurity concentration higher than that of the n-type semiconductor layer (3). With this structure, the lateral JFET can be provided that has an ON resistance further decreased while maintaining a high breakdown voltage performance.
摘要翻译：横向JFET具有包括由n型杂质区形成的n型半导体层（3）和在n型半导体层（3）上由p型杂质区形成的p型半导体层的基本结构，。此外，在p型半导体层中，设置有延伸到n型半导体层（3）中的p +型栅极区域（7），并且含有杂质浓度高于 n型半导体层（3）和与p +型栅极区域层（7）隔开预定距离的n +型漏区（9），并含有n型杂质杂质浓度高于n型半导体层（3）的浓度。利用这种结构，可以提供横向JFET，其具有进一步降低的导通电阻，同时保持高的击穿电压性能。

100. 发明公开

EP1213768A2 Mittels Feldeffekt steuerbares Halbleiterbauelement 审中-公开
标题翻译：使用场效应可控半导体元件
公开(公告)号：EP1213768A2
公开(公告)日：2002-06-12
申请号：EP01127734.0
申请日：2001-11-21
申请人： Infineon Technologies AG
发明人： Ahlers, Dirk , Stengl, Jens-Peer , Tihanyi, Jenö , Weber, Hans , Deboy, Gerald , Strack, Helmut , Willmeroth, Armin
IPC分类号： H01L29/78 , H01L29/06
CPC分类号： H01L29/7802 , H01L29/0619 , H01L29/0623 , H01L29/0634 , H01L29/1095 , H01L29/41766 , H01L29/7816
摘要： Die vorliegende Erfindung betrifft ein Halbleiterbauelement mit in einem Halbleiterkörper (10) ausgebildeten ersten und zweiten Anschlußzonen (12, 20A, 20B), einer die zweite Anschlußzone (20A, 20B) in dem Halbleiterkörper (10) umgebende Kanalzone (30A, 30B), einer zwischen der Kanalzone (30A, 30B) und der ersten Anschlußzone (12) ausgebildeten Driftstrecke (14), in der eine Kompensationszone angeordnet ist. Die Kompensationszone (60A, 60B) ist vom komplementären Leitungstyp wie die Drift-Zone (14) und weist wenigstens zwei Segmente (62A, 64A, 62B, 64B) auf, wobei der Abstand zwischen den zwei benachbarten Segmenten derart gewählt ist, daß die Punch-Through-Spannung zwischen diesen Segmenten in einem Spannungsbereich liegt, der dem Spannungsbereich entspricht, den der Spannungsabfall über der Driftstrecke bei Strömen annimmt, die zwischen einfachem und doppeltem Nennstrom liegen.
摘要翻译：本发明涉及一种具有形成在第一和第二连接区域的半导体主体（10）的半导体装置（12，20A，20B），在所述半导体主体中的第二连接区域（20A，20B）（10）包围所述沟道区（30A，30B），一个沟道区（30A，30B）和所述第一终端区之间（12），在补偿区形成漂移区（14）所在的位置。所述补偿区域（60A，60B）是互补导电类型的漂移区（14），并具有其中所述两个相邻段之间的距离被选择为使得在冲头的至少两个节段（62A，64A，62B，64B），这些段之间 - 通过电压是在对应于其中在电流跨越漂移路径的电压降呈现单，双额定电流之间的谎言的电压范围的电压范围。

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