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91. 发明授权

EP0964338B1 Method and apparatus for operating on a memory unit via a JTAG port 有权
标题翻译：用于经由JTAG端口的存储单元上执行处理的方法和装置
公开(公告)号：EP0964338B1
公开(公告)日：2007-01-24
申请号：EP99110882.0
申请日：1999-06-07
申请人： STMicroelectronics, Inc.
发明人： Slezak, Yaron , Cedar, Yoram , Wienner, Ilan
IPC分类号： G06F13/42 , G06F13/16 , G01R31/3185 , G11C29/00
CPC分类号： G06F9/24

92. 发明授权

EP0714060B1 One chip microcomputer with built-in non-volatile memory 失效
标题翻译：单片机具有内置非易失性存储器
公开(公告)号：EP0714060B1
公开(公告)日：2005-08-24
申请号：EP95308209.6
申请日：1995-11-16
申请人： SANYO ELECTRIC CO. LTD
发明人： Koyama, Hiroshi , Osawa, Hiroshi
IPC分类号： G06F9/24 , G06F12/06 , G06F15/78 , G06F9/445
CPC分类号： G06F9/24 , G06F12/0638

93. 发明公开

EP1096370A3 Microcontroller architecture supporting microcode-implemented peripheral devices 有权
标题翻译：微控制器架构，微外设
公开(公告)号：EP1096370A3
公开(公告)日：2004-05-06
申请号：EP00122984.8
申请日：2000-10-23
申请人： Imsys AB
发明人： Blixt, Sven Stefan
IPC分类号： G06F9/24
CPC分类号： G06F9/3885 , G06F9/24 , G06F9/3897 , G06F9/4403 , G06F9/4411
摘要： Methods and apparatus for creating microcode-implemented peripheral devices for a microcontroller core formed in a monolithic integrated circuit. The microcontroller core has a control store for storing microcode instructions; execution circuitry operable to execute microcode instructions from the control store; and means for loading a suite of one or more microcode-device modules defining an optional peripheral device, the optional peripheral device being implemented by microcode instructions executed by the execution circuitry in accordance with the definition provided by the microcode-device modules.

94. 发明授权

EP0947049B1 UMKONFIGURIERUNGS-VERFAHREN FÜR PROGRAMMIERBARE BAUSTEINE ZUR LAUFZEIT 失效
标题翻译：重构方法可编程块到期
公开(公告)号：EP0947049B1
公开(公告)日：2002-02-20
申请号：EP97954333.7
申请日：1997-12-22
申请人： Pact Informationstechnologie GmbH
发明人： VORBACH, Martin , MÜNCH, Robert
IPC分类号： H03K19/177 , G06F17/50
CPC分类号： G06F15/7867 , G06F9/24
摘要： The invention relates to a method for reconfiguration during the running time of FPGA, in which there is a loading logic or several loading logics which react to signals of any kind and recognize and can process special loading logic commands within a configuration programme consisting of data and commands, and, on the basis of the source of an event, can compute an entry in a branch table. For this, there are one or more branch tables for locating the address of the configuration data to be loaded after computing. One or more configuration memory areas exist, in which one or more configuration programmes are loaded; and there are one or more FIFO memory areas into which configuration data is copied which could not be sent to the element or elements to be configured. When an event occurs, an address is computed in a branch table, based on the source of the event. FIFO memory area is provided and run through before each reloading, and, if the cell can not be reloaded, the configuration data is copied into it nearer the beginning; if the cell can be reloaded, the configuration data is transferred to the cell. The computed branch table entry is read-out, and the configuration data which is stored at the read-out address is loaded into the cell, or, if the cell cannot be reprogrammed, it is copied into the FIFO memory area.

95. 发明公开

EP1146432A2 Umkonfigurierungs-Verfahren für programmierbare Bausteine während der Laufzeit 失效
标题翻译：用于在运行时间期间可编程器件重配置的方法
公开(公告)号：EP1146432A2
公开(公告)日：2001-10-17
申请号：EP01113330.3
申请日：1997-12-22
申请人： Pact Informationstechnologie GmbH
发明人： Vorbach, Martin , Münch, Robert
IPC分类号： G06F15/78
CPC分类号： G06F15/7867 , G06F9/24
摘要： Verfahren zum Umkonfigurieren von programmierbaren Bausteinen, bestehend aus einer zwei oder mehrdimensionalen Zellanordnung. Das Verfahren ermöglicht die Umkonfigurierung des Bausteins oder der Bausteine, ohne die Arbeitsfähigkeit der nicht an der Umkonfigurierung beteiligten Zellen, einzuschränken. Das Verfahren ermöglicht das Laden von kompletten Konfigurationen oder von Teilkonfigurationen in den oder die programmierbaren Bausteine.
摘要翻译：一种用于重新配置可编程装置，由两个或多维细胞排列的方法。该方法使得重新配置一个或多个设备，而不会不参与重新配置限制单元的工作能力。该方法允许完全配置或在局部配置或可编程器件的负载。

96. 发明公开

EP1107114A1 PROGRAM DOWNLOADING DEVICE AND PROGRAM DOWNLOADING METHOD 审中-公开
标题翻译：程序下载设备和程序下载方法
公开(公告)号：EP1107114A1
公开(公告)日：2001-06-13
申请号：EP00917329.5
申请日：2000-04-18
申请人： Matsushita Electric Industrial Co., Ltd.
发明人： NAGATA, Hideki , NOGUCHI, Hiroshi , TANIGUCHI, Shinichi
IPC分类号： G06F9/445
CPC分类号： G06F9/24 , G06F9/445
摘要： When a program of a DSP 104 and address initial values "AH0" and "AL0" are stored to a ROM 101 and control to transfer the program to a command RAM 108 of the DSP 104 in a state that the stored address initial values are set at the top are executed by a CPU 102 comprising a control signal generating section 103, a ternary counter 105, which repeats a number count operation corresponding to a data length (for example, 3 bytes) of the command RAM 108, performs a count in accordance with a clock signal generated from a control signal generating section 103, while an address counter 106 loads the address initial values of the ROM 101, and then increments the address value for each count-up of the ternary counter 105 and outputs the resultant to the command RAM 108.
摘要翻译：当DSP104的程序和地址初始值“AH0”和“AL0”被存储到ROM101并且控制在设置存储的地址初始值的状态下将程序传送到DSP104的命令RAM108 在上部由CPU102执行，该CPU102包括控制信号产生部分103，重复与命令RAM108的数据长度（例如，3字节）对应的数量计数操作的三进制计数器105，执行计数按照从控制信号发生部分103产生的时钟信号，当地址计数器106加载ROM101的地址初始值，然后增加三进制计数器105的每次递增的地址值并将结果输出到命令RAM 108。

97. 发明公开

EP1101303A2 METHOD AND APPARATUS FOR DATA SAMPLE CLOCK RECOVERY 审中-公开
标题翻译：方法和设备恢复数据采样
公开(公告)号：EP1101303A2
公开(公告)日：2001-05-23
申请号：EP99920426.6
申请日：1999-05-11
申请人： Digital Harmony Technologies, L.L.C.
发明人： MOSES, Robert, W. , BARTLETT, Gregory, J. , GOLDSTEIN, Allen, R. , KARR, Brian, D.
IPC分类号： H04J3/06 , H04N7/62
CPC分类号： H04L12/40058 , G06F9/24 , G06F9/30189 , H04J3/0632 , H04L12/40117 , H04N21/43632
摘要： A method and apparatus is described for recovering data sample clock rates from received isochronous streams of data packets including associated time stamp values, such as in an IEEE 1394 bus-interconnected system. The difference between consecutive time stamp values is determined by successively latching the time stamp values and applying them to a subtracter circuit to produce a difference value. This difference value is then successively decremented by a down counter, with the down counter then producing a signal pulse and loading a next difference value upon completion of the count. The pulsed signal is applied to a phase-locked loop to provide a frequency multiple, and a clock signal is correspondingly produced that has a frequency proportional to the difference between the consecutive time stamp values. Data input buffer levels may be monitored and the clock signal frequency adjusted accordingly.

98. 发明公开

EP0898225A4 APPARATUS AND METHOD FOR PROCESSING INFORMATION 失效
标题翻译：装置和方法进行信息处理
公开(公告)号：EP0898225A4
公开(公告)日：2000-07-05
申请号：EP98901493
申请日：1998-01-29
申请人： SONY CORP
发明人： MATSUURA YOKO
IPC分类号： G06F9/24 , G06F9/445 , G06F11/14 , G06F9/06 , G06F12/16
CPC分类号： G06F9/4403 , G06F8/60 , G06F8/65 , G06F9/24 , G06F11/1417
摘要： An apparatus for processing information which is provided with a nonvolatile memory in which two physical sectors are provided as basic program storing areas, a device which acquires a new basic program from the outside, and a processor which executes an application program stored in the memory in accordance with a basic program stored in the memory. The processor stores the acquired new basic program in one of the two physical sectors which is not used for writing the basic program. Therefore, the new basic program is stored in the physical sector which is not used for storing the previous basic program. The physical sector for writing the basic program is switched depending upon whether or not a program normally starts.

99. 发明公开

EP0898225A1 APPARATUS AND METHOD FOR PROCESSING INFORMATION 失效
标题翻译：设备和方法，用于在嵌入式设备更新引导和应用程序
公开(公告)号：EP0898225A1
公开(公告)日：1999-02-24
申请号：EP98901493.1
申请日：1998-01-29
申请人： SONY CORPORATION
发明人： MATSUURA, Yoko
IPC分类号： G06F9/06 , G06F9/445 , G06F12/16
CPC分类号： G06F9/4403 , G06F8/60 , G06F8/65 , G06F9/24 , G06F11/1417
摘要： There are provided a non-volatile memory in which two physical sectors have been set as areas to store a basic program, an apparatus for obtaining a new basic program from the outside, and a processor for executing an application program stored in the memory in accordance with the basic program stored in the memory. The processor allows the obtained new basic program to be stored into the physical sector which is not used to write the basic program between the two physical sectors in the memory. A new basic program is stored into the other physical sector which is not the physical sector in which the basic program has been stored at the preceding time. Upon activation, the physical sector to write the basic program is switched in accordance with whether the program is normally activated or not.
摘要翻译：本发明提供在其中的非易失性存储器中的两个物理扇区已经被设置为区域存储基本程序，对装置用于从外部获得一个新的基本程序，和一个处理器，用于对存储在存储器中雅舞蹈应用程序执行与存储在内存中的基本程序。该处理器允许获得新的基本程序被存储到物理扇区的所有未使用的写入在存储器中的两个物理扇区之间的基本程序。新的基本程序存储到另一个物理扇区所有这一切是不是在哪一个基本的程序已经存储在preceding-时间的物理扇区。激活后，写的基本程序的物理扇区被雅舞蹈与程序是否被正常激活或不切换。

100. 发明授权

EP0364743B1 Development method of data processing system 失效
标题翻译：一个数据处理系统的设计过程
公开(公告)号：EP0364743B1
公开(公告)日：1997-05-28
申请号：EP89117257.9
申请日：1989-09-18
申请人： HITACHI, LTD.
发明人： Akao, Yasushi , Baba, Shiro , Sawase, Terumi , Hagiwara, Yoshimune
IPC分类号： G06F15/78 , G06F9/24
CPC分类号： G06F9/24 , G06F15/7814

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