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91. 发明授权

EP2936321B1 SYSTEM AND METHOD FOR AN EFFICIENT CACHE WARM-UP 有权
公开(公告)号：EP2936321B1
公开(公告)日：2018-07-04
申请号：EP13865475.1
申请日：2013-12-18
申请人： NetApp, Inc.
发明人： BAIRAVASUNDARAM, Lakshmi Narayanan , SOUNDARARAJAN, Gokul , STORER, Mark Walter , ZHANG, Yiying
IPC分类号： G06F12/0862
CPC分类号： G06F12/0848 , G06F12/0804 , G06F12/0862 , G06F12/0868 , G06F12/0888
摘要： Described herein is a system and method for an efficient cache warm-up. The system and method may copy data blocks from a primary storage device to a cache memory device. The system and method may identify a subset of data blocks stored on the primary storage device as candidate data blocks for copying to the cache memory device during a cache warm-up period. A cost effectiveness for copying the candidate data blocks to the cache memory device may be determined. In some embodiments, the cost effectiveness may be calculated based on one or more latency values associated with the primary storage device and the cache memory device. The candidate data blocks may be copied to the cache memory device based on the cost effectiveness.

92. 发明公开

EP3327570A1 DUAL MODE LOCAL DATA STORE 审中-公开
公开(公告)号：EP3327570A1
公开(公告)日：2018-05-30
申请号：EP16203672.7
申请日：2016-12-13
申请人： Advanced Micro Devices, Inc.
发明人： CLIFTON, Daniel , MANTOR, Michael , BURTON, Hans
IPC分类号： G06F9/50 , G06F9/52
CPC分类号： G06F12/0848 , G06F9/3887 , G06F9/5077 , G06F9/526 , G06F2212/282
摘要： A system and method for efficiently processing access requests for a shared resource are described. Each of many requestors are assigned to a partition of a shared resource. When a controller determines no requestor generates an access request for an unassigned partition, the controller permits simultaneous access to the assigned partitions for active requestors. When the controller determines at least one active requestor generates an access request for an unassigned partition, the controller allows a single active requestor to gain exclusive access to the entire shared resource while stalling access for the other active requestors. The controller alternatives exclusive access among the active requestors. In various embodiments, the shared resource is a local data store in a graphics processing unit and each of the multiple requestors is a single instruction multiple data (SIMD) compute unit.

93. 发明公开

EP3285172A1 DATA CACHE REGION PREFETCHER 审中-公开
公开(公告)号：EP3285172A1
公开(公告)日：2018-02-21
申请号：EP16200806.4
申请日：2016-11-25
申请人： Advanced Micro Devices, Inc.
发明人： McCAULEY, Donald , JONES, William
IPC分类号： G06F12/0862 , G06F12/0886 , G06F12/0846
CPC分类号： G06F12/12 , G06F12/0848 , G06F12/0862 , G06F12/0886 , G06F12/0891 , G06F2212/1021 , G06F2212/6024 , G06F2212/6026
摘要： A data cache region prefetcher creates a region when a data cache miss occurs. Each region includes a predetermined range of data lines proximate to each data cache miss and is tagged with an associated instruction pointer register (RIP). The data cache region prefetcher compares subsequent memory requests against the predetermined range of data lines for each of the existing regions. For each match, the data cache region prefetcher sets an access bit and attempts to identify a pseudo-random access pattern based on the set access bits. The data cache region prefetcher increments or decrements appropriate counters to track how often the pseudo-random access pattern occurs. If the pseudo-random access pattern occurs frequently, then the next time a memory request is processed with the same RIP and pattern, the data cache region prefetcher prefetches the data lines in accordance with the pseudo-random access pattern for that RIP.
摘要翻译：数据缓存区域预取程序在发生数据缓存未命中时创建一个区域。每个区域包括靠近每个数据高速缓存未命中的预定范围的数据线，并且用相关联的指令指针寄存器（RIP）标记。数据高速缓存区预取器将后续存储器请求与每个现有区域的预定数据行范围进行比较。对于每个匹配，数据高速缓存区预取器设置一个访问位，并尝试基于设置的访问位来识别伪随机访问模式。数据高速缓存区域预取器递增或递减适当的计数器以跟踪伪随机访问模式发生的频率。如果伪随机访问模式频繁发生，则下一次以相同的RIP和模式处理存储器请求时，数据缓存区域预取器根据该RIP的伪随机访问模式来预取数据行。

94. 发明公开

EP3129887A4 MULTIPLE DATA PREFETCHERS THAT DEFER TO ONE ANOTHER BASED ON PREFETCH EFFECTIVENESS BY MEMORY ACCESS TYPE 有权
标题翻译： MEHRERE ZEITVERSETZTE DATENVORLADER JE NACH VORAUSLADEWIRKSAMKEIT DURCH SPEICHERZUGANGSTYP
公开(公告)号：EP3129887A4
公开(公告)日：2017-07-26
申请号：EP14891605
申请日：2014-12-14
申请人： VIA ALLIANCE SEMICONDUCTOR CO LTD
发明人： HOOKER RODNEY E , EDDY COLIN , REED DOUGLAS R , GREER JOHN MICHAEL
IPC分类号： G06F12/08 , G06F9/30 , G06F9/345 , G06F9/38 , G06F9/45 , G06F12/0811 , G06F12/0846 , G06F12/0862 , G06F12/127
CPC分类号： G06F12/0862 , G06F8/4442 , G06F9/3455 , G06F9/3802 , G06F9/383 , G06F12/0811 , G06F12/0848 , G06F12/127 , G06F2212/1016 , G06F2212/1044 , G06F2212/502 , G06F2212/6026
摘要： A processor includes a first prefetcher that prefetches data in response to memory accesses and a second prefetcher that prefetches data in response to memory accesses. Each of the memory accesses has an associated memory access type (MAT) of a plurality of predetermined MATs. The processor also includes a table that holds first scores that indicate effectiveness of the first prefetcher to prefetch data with respect to the plurality of predetermined MATs and second scores that indicate effectiveness of the second prefetcher to prefetch data with respect to the plurality of predetermined MATs. The first and second prefetchers selectively defer to one another with respect to data prefetches based on their relative scores in the table and the associated MATs of the memory accesses.
摘要翻译：处理器包括响应于存储器访问而预取数据的第一预取器以及响应于存储器访问而预取数据的第二预取器。每个存储器访问具有多个预定MAT的相关存储器访问类型（MAT）。处理器还包括保存指示第一预取器相对于多个预定MAT预取数据的有效性的第一分数以及指示第二预取器相对于多个预定MAT预取数据的有效性的第二分数的表。第一和第二预取器基于它们在表中的相对分数和存储器访问的相关MAT，选择性地相对于数据预取彼此推迟。

95. 发明公开

EP3161643A1 DISUNITED SHARED-INFORMATION AND PRIVATE-INFORMATION CACHES 审中-公开
标题翻译：在私人信息下获取信息CACHESPEICHERFÜRGEMEINSAM GENUTZTE
公开(公告)号：EP3161643A1
公开(公告)日：2017-05-03
申请号：EP15729061.0
申请日：2015-06-08
申请人： Qualcomm Incorporated
发明人： PATSILARAS, George , RYCHLIK, Bohuslav , ROHILLAH, Anwar
IPC分类号： G06F12/08 , G06F1/32
CPC分类号： G06F12/0811 , G06F1/3275 , G06F1/3287 , G06F12/0815 , G06F12/0837 , G06F12/084 , G06F12/0848 , G06F2212/1024 , G06F2212/1028 , G06F2212/1056 , G06F2212/283 , G06F2212/314 , G06F2212/601 , Y02D10/13 , Y02D10/14 , Y02D10/171
摘要： Systems and methods pertain to a multiprocessor system comprising disunited cache structures. A first private-information cache is coupled to a first processor of the multiprocessor system. The first private-information cache is configured to store information that is private to the first processor. A first shared-information cache which is disunited from the first private-information cache is also coupled to the first processor. The first shared-information cache is configured to store information that is shared/shareable between the first processor and one or more other processors of the multiprocessor system.
摘要翻译：系统和方法涉及包含不均匀缓存结构的多处理器系统。第一私人信息缓存耦合到多处理器系统的第一处理器。第一私人信息缓存被配置为存储对第一处理器是私有的信息。与第一专用信息高速缓存分离的第一共享信息高速缓存也耦合到第一处理器。第一共享信息缓存被配置为存储在第一处理器与多处理器系统的一个或多个其他处理器之间共享/共享的信息。

96. 发明公开

EP2724268A4 SYSTEM AND METHOD FOR IMPLEMENTING A SCALABLE DATA STORAGE SERVICE 有权
标题翻译：系统和方法实现一个可扩展的数据存储服务
公开(公告)号：EP2724268A4
公开(公告)日：2015-10-28
申请号：EP12803794
申请日：2012-06-27
申请人： AMAZON TECH INC
发明人： SIVASUBRAMANIAN SWAMINATHAN , STEFANI STEFANO , BURAGOHAIN CHIRANJEEB , BLACKMAN RANDE A , RATH TIMOTHY ANDREW , BRADFORD RAYMOND S , MCALISTER GRANT A M , KULESZA JAKUB , HAMILTON JAMES , CABRERA LUIS FELIPE
IPC分类号： G06F7/00 , G06F17/30
CPC分类号： G06F17/30584 , G06F9/5061 , G06F12/0848 , G06F17/30286 , G06F17/30289 , G06F17/30303 , G06F17/30306 , G06F17/30321 , G06F17/30339 , G06F17/3056 , H04L67/02 , H04L67/1097 , H04L67/2804 , Y10S707/968 , Y10S707/972
摘要： A system that implements a scalable data storage service may maintain tables in a non-relational data store on behalf of clients. The system may provide a Web services interface through which service requests are received, and an API usable to request that a table be created, deleted, or described; that an item be stored, retrieved, deleted, or its attributes modified; or that a table be queried (or scanned) with filtered items and/or their attributes returned. An asynchronous workflow may be invoked to create or delete a table. Items stored in tables may be partitioned and indexed using a simple or composite primary key. The system may not impose pre-defined limits on table size, and may employ a flexible schema. The service may provide a best-effort or committed throughput model. The system may automatically scale and/or re-partition tables in response to detecting workload changes, node failures, or other conditions or anomalies.

97. 发明公开

EP2847684A1 PER THREAD CACHELINE ALLOCATION MECHANISM IN SHARED PARTITIONED CACHES IN MULTI-THREADED PROCESSORS 审中-公开
标题翻译： GEMEINSAMEN PARTITIONIERTEN CACHESPEICHERN BEI MULTITHREAD-PROZESSOREN中的机械式FÜRPRO-THREAD-CACHEZEENZUWEISUNG
公开(公告)号：EP2847684A1
公开(公告)日：2015-03-18
申请号：EP13723374.8
申请日：2013-05-08
申请人： Qualcomm Incorporated
发明人： KOOB, Christopher Edward , INGLE, Ajay Anant , CODRESCU, Lucian , VENKUMAHANTI, Suresh K.
IPC分类号： G06F12/08
CPC分类号： G06F12/0842 , G06F12/0848 , G06F12/0864
摘要： Systems and methods for allocation of cache lines in a shared partitioned cache of a multi-threaded processor. A memory management unit is configured to determine attributes associated with an address for a cache entry associated with a processing thread to be allocated in the cache. A configuration register is configured to store cache allocation information based on the determined attributes. A partitioning register is configured to store partitioning information for partitioning the cache into two or more portions. The cache entry is allocated into one of the portions of the cache based on the configuration register and the partitioning register.
摘要翻译：用于在多线程处理器的共享分区高速缓存中分配高速缓存行的系统和方法。存储器管理单元被配置为确定与要在高速缓存中分配的处理线程相关联的高速缓存条目的地址相关联的属性。配置寄存器被配置为基于所确定的属性来存储高速缓存分配信息。分配寄存器被配置为存储用于将高速缓存分割成两个或更多个部分的分区信息。缓存条目基于配置寄存器和分区寄存器分配到高速缓存的一部分中。

98. 发明授权

EP2515238B1 Cache memory with dynamic lockstep support 有权转让
标题翻译：高速缓冲存储器与动态支持阻断步骤
公开(公告)号：EP2515238B1
公开(公告)日：2014-08-13
申请号：EP12164037.9
申请日：2012-04-13
申请人： Freescale Semiconductor, Inc.
发明人： Moyer, William C.
IPC分类号： G06F12/08 , G06F11/16 , G06F12/12
CPC分类号： G06F12/0848 , G06F11/1629 , G06F11/1658 , G06F12/0815 , G06F12/126 , G06F2201/845 , G06F2212/1016

99. 发明授权

EP1502193B1 METHODS AND APPARATUS FOR CONTROLLING HIERARCHICAL CACHE MEMORY 有权转让
标题翻译： VERFAHREN UND VORRICHRUNG ZUR STEUERUNG EINES HIERARCHISCHEN CACHE-SPEICHERS
公开(公告)号：EP1502193B1
公开(公告)日：2013-11-13
申请号：EP03717727.6
申请日：2003-04-25
申请人： Sony Computer Entertainment Inc.
发明人： Magoshi, Hidetaka
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0848 , G06F12/0864 , G06F12/0895 , G06F12/0897

100. 发明授权

EP1974256B1 EFFICIENT MEMORY HIERARCHY MANAGEMENT 有权
标题翻译：高效的内存层次管理
公开(公告)号：EP1974256B1
公开(公告)日：2010-05-05
申请号：EP07710245.7
申请日：2007-01-22
申请人： QUALCOMM Incorporated
发明人： MORROW, Michael William , SARTORIUS, Thomas Andrew
IPC分类号： G06F9/38
CPC分类号： G06F9/3802 , G06F12/0848

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