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91. 发明公开

EP1134660A3 Test mode entering in an integrated circuit for use in floppy disk drive apparatus 审中-公开
标题翻译： Prüfmoduseintritt中使用的集成电路在软盘驱动器
公开(公告)号：EP1134660A3
公开(公告)日：2004-01-14
申请号：EP01300105.2
申请日：2001-01-08
申请人： ALPS ELECTRIC CO., LTD.
发明人： Haitani, Munehisa
IPC分类号： G06F11/26 , G01R31/317
CPC分类号： G01R31/31701
摘要： In a method and a device for entering a test mode in an integrated circuit for use in a floppy disk drive apparatus, the integrated circuit enters the test mode on condition that an enter-test-mode command is input within a predetermined period after the floppy disk drive apparatus is powered on, thereby being prevented from accidentally entering the test mode while operating in a normal mode.

92. 发明授权

EP0610886B1 Microcomputer for IC card 失效
标题翻译：微机IC卡
公开(公告)号：EP0610886B1
公开(公告)日：2001-10-17
申请号：EP94101896.2
申请日：1994-02-08
申请人： MITSUBISHI DENKI KABUSHIKI KAISHA
发明人： Asami, Kazuo, c/o Mitsubishi Elec. Semiconductor
IPC分类号： G06F1/00 , G01R31/317 , G06F11/00 , G06F12/14 , G06K19/073
CPC分类号： G07F7/1008 , G01R31/31701 , G06F11/006 , G06F11/22 , G06F11/24 , G06F12/1433 , G06Q20/3558
摘要： It is an object to obtain a microcomputer for an IC card arranged in such a manner that only a user mode can be performed after the microcomputer has been shipped to a user. A region on which shipment data representing a fact that the microcomputer has been shipped is written at the time of the shipment is formed in a test EEPROM region. A shipment confirmation routine for confirming whether or not the shipment data has been written is disposed to be performed before execution of a branch routine for branching to each program in accordance with an execution command supplied from outside. If the fact that the shipment data has been written on the test EEPROM region has been confirmed in a shipment confirmation routine, branching is limited to only the user mode.

93. 发明授权

EP0788116B1 Overvoltage detection circuit for mode selection 失效
标题翻译：过电压检测电路，以选择操作模式
公开(公告)号：EP0788116B1
公开(公告)日：2001-07-11
申请号：EP97101232.3
申请日：1997-01-27
申请人： Oki Electric Industry Co., Ltd.
发明人： Honda, Takashi , Takahashi, Shinya
IPC分类号： G11C29/00 , G06F11/267 , G01R19/165
CPC分类号： G11C29/46 , G01R31/31701
摘要： The present invention relates to a signal generator for generating test mode signals when any voltage higher than a recommended input high voltage is applied to a predetermined input pin, and for switching from a normal mode to a test mode in response to the test mode signals. A signal generator of the present invention is comprised of an input pin, a high impedance circuit being coupled between the input pin and a first node, the high impedance circuit comprising a plurality of transistors, the plurality of transistors respectively being connected in series and respectively having a gate coupled with a source or a drain, a signal amplifier being coupled with the high impedance circuit through the first node, a resistor being coupled between the first node and a reference voltage, and a transistor being coupled between the first node and a second node between predetermined transistors among the plurality of transistors, the transistor bypassing a current path from the second node to the first node and maintaining a potential level of the first node, in response to an output condition of the signal amplifier.

94. 发明公开

EP1030313A3 Semiconductor device having test mode entry circuit 有权
标题翻译：半导体器件测试电路
公开(公告)号：EP1030313A3
公开(公告)日：2001-03-07
申请号：EP00301174.9
申请日：2000-02-15
申请人： FUJITSU LIMITED
发明人： Kato, Yoshiharu , Iwase, Akihiro
IPC分类号： G11C29/00 , G01R31/317
CPC分类号： G11C29/40 , G01R31/31701 , G11C11/40 , G11C29/1201 , G11C29/46 , G11C2029/0407
摘要： A semiconductor device has a normal operation mode and a test mode. A decision circuit (31) determines whether the device has entered the test mode. A control circuit (32) changes information related to a normal operation mode when the test mode has been entered. If the test mode is accidentally entered, then because the information related to normal operation has been changed, a user can readily determine that the device has entered the test mode.

95. 发明公开

EP1030313A2 Semiconductor device having test mode entry circuit 有权
标题翻译： Halbleitereinrichtung mitPrüfschaltung
公开(公告)号：EP1030313A2
公开(公告)日：2000-08-23
申请号：EP00301174.9
申请日：2000-02-15
申请人： FUJITSU LIMITED
发明人： Kato, Yoshiharu , Iwase, Akihiro
IPC分类号： G11C29/00 , G01R31/317
CPC分类号： G11C29/40 , G01R31/31701 , G11C11/40 , G11C29/1201 , G11C29/46 , G11C2029/0407
摘要： A semiconductor device has a normal operation mode and a test mode. A decision circuit (31) determines whether the device has entered the test mode. A control circuit (32) changes information related to a normal operation mode when the test mode has been entered. If the test mode is accidentally entered, then because the information related to normal operation has been changed, a user can readily determine that the device has entered the test mode.
摘要翻译：半导体器件具有正常工作模式和测试模式。判定电路（31）判断设备是否已进入测试模式。当输入测试模式时，控制电路（32）改变与正常操作模式有关的信息。如果测试模式被意外输入，则由于与正常操作相关的信息已经改变，用户可以容易地确定设备已进入测试模式。

96. 发明公开

EP0953987A2 Synchronous semiconductor storage device 有权
标题翻译：同步半导体存储装置
公开(公告)号：EP0953987A2
公开(公告)日：1999-11-03
申请号：EP99107422.0
申请日：1999-04-26
申请人： NEC CORPORATION
发明人： Taniguchi, Junya , Koshikawa, Yasuji , Mine, Kouji
IPC分类号： G11C29/00
CPC分类号： G01R31/31701
摘要： According to one disclosed embodiment, a synchronous semiconductor storage device ( 100 ) includes a circuit for accomplishing mode setting operations after a test mode is entered, where the test mode includes a higher frequency internal clock. A synchronous semiconductor storage device ( 100 ) generates a first internal synchronous clock signal ICLK which can be used to enter mode setting values to a mode register setting circuit ( 122 ). At the same time, an external synchronous signal CSB can be applied to generate a second internal synchronous clock signal CSCLK. The ICLK and CSCLK values can be used to generate a higher frequency clock ICLK' in a test mode. The ICLK' signal can be applied to internal circuits ( 124 ) allowing such circuits to operate at a higher speed. The ICLK' signal is not applied to the mode register setting circuit ( 122 ), thereby avoiding the possible latching of incorrect mode setting values by the mode register setting circuit ( 122 ).

97. 发明授权

EP0471540B1 A semiconductor memory with a flag for indicating test mode 失效
标题翻译：有用于Prüfmodusanzeigen标志的半导体存储器
公开(公告)号：EP0471540B1
公开(公告)日：1997-11-19
申请号：EP91307422.5
申请日：1991-08-12
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Steele, Randy Charles
IPC分类号： G06F11/26 , G11C29/00
CPC分类号： G11C29/46 , G01R31/31701
摘要： An integrated circuit having a normal operating mode and a special operating mode, such as a special test mode, is disclosed. The special test mode is enabled by a series of signals, such as overvoltage excursions at a terminal, rather than by a single such excursion, so that it is less likely that the special test mode is entered inadvertently, such as due to noise or power-down and power-up of the device. The circuit for enabling the test mode includes a series of D-type flip-flops, each of which are clocked upon detection of the overvoltage condition together with a particular logic level applied at another terminal; multiple series of flip-flops may be provided for multiple special test modes. Additional features include the provision of a power-on reset circuit which locks out the entry into the test mode during power-up of the device. Acknowledgment of the entry into test mode is provided by the presentation of a low impedance at output terminals while the device is not enabled; chip enable of the device causes the device to exit the test mode. Once in test mode, the output enable terminal of the device can provide a chip enable function.

98. 发明公开

EP0565866A3 Large-scale integrated circuit device 失效
标题翻译：大规模集成电路设备
公开(公告)号：EP0565866A3
公开(公告)日：1997-11-05
申请号：EP93103944.0
申请日：1993-03-11
申请人： NEC CORPORATION
发明人： Shoda, Masahiko, c/o NEC Corporation
IPC分类号： G01R31/318
CPC分类号： G01R31/318555 , G01R31/31701 , G01R31/318572 , G06F11/2273
摘要： A large-scale integrated circuit, according to the present invention, comprises an integrated circuit function block having an original circuit function as the integrated circuit, a serial bus function block for setting and changing of an internal function of the integrated circuit function block, the serial bus function block including a clock terminal for receiving a clock signal, a bus busy terminal receiving a serial bus busy signal as an operation designating signal, and a serial data terminal receiving a serial data, a boundary scanning function block for checking wiring of the integrated circuit function block after installation on a circuit board, the boundary scanning function block including a clock terminal receiving a clock signal, a test mode select terminal for receiving a rest mode select signal as an operation designation signal and a test data terminal for receiving a test data, and the serial bus function block and the boundary scanning function block being so coupled to so that at least one of pairs of terminals consisted of both of the clock terminals, the bus busy terminal and the test mode select terminal, and the serial data terminal and the test data terminal being formed with a common terminal.

99. 发明公开

EP0614144A3 Semiconductor integrated circuit device equipped with answer system for teaching optional functions to diagnostic system 失效
标题翻译：使用响应系统配备半导体集成电路教在诊断系统的功能的功能。
公开(公告)号：EP0614144A3
公开(公告)日：1997-10-01
申请号：EP94102997.7
申请日：1994-02-28
申请人： NEC CORPORATION
发明人： Edo, Yasuhiro
IPC分类号： G06F11/22 , G11C29/00
CPC分类号： G11C29/10 , G01R31/31701 , G01R31/31908 , G06F11/006
摘要： An answer system (21) incorporated in a dynamic random access memory device informs user's options to a diagnostic system in a diagnostic mode, and allows the diagnostic system to automatically proceed to appropriate test programs stored therein, thereby causing the test programs to be shared between different models of the dynamic random access memory device.

100. 发明授权

EP0471544B1 Semiconductor memory with a sequence of clocked access codes for test mode entry 失效
标题翻译：用的时钟控制的接入码的序列的半导体存储器进入测试模式
公开(公告)号：EP0471544B1
公开(公告)日：1997-05-14
申请号：EP91307426.6
申请日：1991-08-12
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Slemmer, William Carl , Coker, Thomas Allyn , McClure, David Charles
IPC分类号： G06F11/26 , G11C7/00 , G11C29/00
CPC分类号： G11C29/46 , G01R31/31701 , G01R31/31719 , G11C7/1045
摘要： An integrated circuit having a normal operating mode and a special operating mode, such as a special test mode, is disclosed. The special test mode is enabled by a series of signals, such as overvoltage excursions at a terminal, rather than by a single such excursion, so that it is less likely that the special test mode is entered inadvertently, such as due to noise or power-down and power-up of the device. The circuit for enabling the test mode includes a series of D-type flip-flops, each of which are clocked upon detection of the overvoltage condition together with a particular logic level applied at another terminal; multiple series of flip-flops may be provided for multiple special test modes. In addition, sequential codes may be used for further security. Logic for evaluating both a sequence of codes received in parallel from a number of address terminals, and also a sequence of serial codes received at single address terminal, are disclosed. Additional features include the provision of a power-on reset circuit which locks out the entry into the test mode during power-up of the device. Acknowledgment of the entry into test mode is provided by the presentation of a low impedance at output terminals while the device is not enabled; chip enable of the device causes the device to exit the test mode. Once in test mode, the output enable terminal of the device can provide a chip enable function.

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