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1. 发明公开

EP4390926A1 MATRIX-VECTOR MULTIPLICATIONS BASED ON CHARGE-SUMMING MEMORY CELL STRINGS 审中-公开
公开(公告)号：EP4390926A1
公开(公告)日：2024-06-26
申请号：EP22215794.3
申请日：2022-12-22
申请人： Imec VZW
发明人： DOEVENSPECK, Jonas , ROSMEULEN, Maarten , COSEMANS, Stefan
IPC分类号： G11C7/10 , G06F7/527 , G06N3/063 , G11C11/54 , G11C16/26
CPC分类号： G11C7/1006 , G11C11/54 , G06N3/063 , G11C16/26 , G06F7/5443 , G06N3/065
摘要： An in-memory compute device for multiply-and-accumulate operations and methods of operating the same. The device comprises a string of series-connected memory cells (11a-11e) formed over a semiconductor channel structure (12). Each memory cell comprises a programmable threshold transistor to store a weight input. A readout circuit (15) includes a sense node (14) for buffering charge packets transferred from the string of memory cells. Control circuitry is configured for applying pass mode signals, data input signals and stop signals to the control gates of the respective memory cells. Pass mode signals cause memory cells of the string to be switched on, thereby inducing charge packets in the channel structure underneath each memory cell. Data input signals representing binary zeroes and stop signals cause memory cells of the string to be switched off. Data input signals and stop signals are applied sequentially according to each memory cell's position along the string.

2. 发明公开

EP3835941A1 FPGA SPECIALIST PROCESSING BLOCK FOR MACHINE LEARNING 审中-公开
公开(公告)号：EP3835941A1
公开(公告)日：2021-06-16
申请号：EP20196629.8
申请日：2020-09-17
申请人： INTEL Corporation
发明人： Langhammer, Martin , Dongdong, Chen
IPC分类号： G06F7/527 , G06F7/57
摘要： The present disclosure describes a digital signal processing (DSP) block that includes a plurality of columns of weight registers and a plurality of inputs configured to receive a first plurality of values and a second plurality of values. The first plurality of values is stored in the plurality of columns of weight registers after being received. Additionally, the DSP block includes a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.

3. 发明公开

EP3835940A1 IMPLEMENTING LARGE MULTIPLIERS IN TENSOR ARRAYS 审中-公开
公开(公告)号：EP3835940A1
公开(公告)日：2021-06-16
申请号：EP20196562.1
申请日：2020-09-17
申请人： INTEL Corporation
发明人： Langhammer, Martin , Finn, Simon Peter
IPC分类号： G06F7/527 , G06F7/57
摘要： The present disclosure describes an integrated circuit device that includes a digital signal processing (DSP) block. The DSP block that includes a plurality of columns of weight registers and a plurality of inputs configured to receive a first plurality of values and a second plurality of values. The first plurality of values is stored in the plurality of columns of weight registers after being received. Also, the first plurality of inputs, the second plurality of inputs, or both are derived from higher precision values. Additionally, the DSP block includes a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.

4. 发明授权

EP2189897B1 Multiplikation einer ganzen Zahl mit einer Gleitkommazahl 有权
标题翻译：的整数的乘法与浮点数
公开(公告)号：EP2189897B1
公开(公告)日：2013-04-24
申请号：EP08020118.9
申请日：2008-11-19
申请人： VEGA Grieshaber KG
发明人： Kopp, Manfred
IPC分类号： G06F7/487 , G06F7/527 , G06F7/499 , H03M7/24
CPC分类号： G06F7/4876 , G06F7/49963 , G06F7/5272 , G06F2207/3852 , H03M7/24

5. 发明公开

EP0020470A4 MODULAR PROCESSOR SYSTEM. 失效
标题翻译：模块RECHNERSYSTEM。
公开(公告)号：EP0020470A4
公开(公告)日：1981-06-17
申请号：EP79901287
申请日：1980-04-22
申请人： HUGHES AIRCRAFT CO
发明人： PROPSTER JOHN A , ROWAN JOHN H
IPC分类号： G06F7/38 , G06F7/527 , G06F11/20 , G06F15/00 , G06F15/80
CPC分类号： G06F11/2051 , G06F15/8015
摘要： A signal processing system that has an improved modular architecture so that a selected number of arithmetic element (AE) units may be utilized with a single arithmetic element controller (AEC) unit to provide a system that can be readily expanded or decreased on computational ability. All of the AE units perform similar calculations under control of the AEC unit in response to common address control and coefficient signals. Each AE units has its own extended work store (EWS) unit with all of the EWS units responding to the same address and control signals, from either the AEC unit or an external interface unit to conform to the modular architecture. Each EWS unit is synchronized with the AE unit, thus allowing continuous and high speed computations to be performed. Also, each of the EWS units is coupled to the external interface unit for receiving and transferring data when not being accessed by the AEC unit. The AE units, each of which are similar, may have a single multiplier and storage unit matched to a plurality of register and arithmetic logic (RALU) units so that parallel calculations may be performed utilizing the multiplier ouput data, thus increasing the overall speed of calculation a plurality of times of the system clock speed. Another feature of the invention is that the AEC unit has an architecture that allows simplified programming. The processor system also includes a control arrangement that allows, upon failure of an AE unit or EWS unit, a redundant AE unit and EWS unit to be utilized.
摘要翻译：一种信号处理系统，具有改进的模块化结构，使得选定数量的算术元件（AE）单元可与单个算术元件控制器（AEC）单元一起使用，以提供可随计算能力容易扩展或减小的系统。所有AE单元在AEC单元的控制下执行类似的计算以响应共同的地址控制和系数信号。每个AE单元都有自己的扩展工作存储（EWS）单元，所有EWS单元都响应来自AEC单元或外部接口单元的相同地址和控制信号，以符合模块化架构。每个EWS单元都与AE单元同步，因此可以进行连续和高速计算。而且，每个EWS单元都连接到外部接口单元，用于在不被AEC单元访问时接收和传送数据。每个类似的AE单元可以具有与多个寄存器和算术逻辑（RALU）单元匹配的单个乘法器和存储单元，从而可以利用乘法器输出数据执行并行计算，从而增加总体速度计算系统时钟速度的多倍。本发明的另一个特征是AEC单元具有允许简化编程的结构。处理器系统还包括控制装置，其允许在AE装置或EWS装置发生故障时使用冗余AE装置和EWS装置。

6. 发明授权

EP3835942B1 SYSTEMS AND METHODS FOR LOADING WEIGHTS INTO A TENSOR PROCESSING BLOCK 有权
公开(公告)号：EP3835942B1
公开(公告)日：2023-10-18
申请号：EP20196801.3
申请日：2020-09-18
发明人： Langhammer, Martin
IPC分类号： G06F7/527 , G06F7/57 , G06N3/063

7. 发明授权

EP3786786B1 PROCESSING DEVICE, PROCESSING METHOD, CHIP, AND ELECTRONIC APPARATUS 有权
公开(公告)号：EP3786786B1
公开(公告)日：2023-06-07
申请号：EP19214371.7
申请日：2018-04-17
发明人： CHEN, Tianshi , GUO, Qi , ZHOU, Shengyuan , DU, Zidong
IPC分类号： G06F9/302 , G06F7/527 , G06F7/533 , G06F9/30 , G06N3/063 , G06F7/544

8. 发明公开

EP3835942A1 SYSTEMS AND METHODS FOR LOADING WEIGHTS INTO A TENSOR PROCESSING BLOCK 有权
公开(公告)号：EP3835942A1
公开(公告)日：2021-06-16
申请号：EP20196801.3
申请日：2020-09-18
申请人： INTEL Corporation
发明人： Langhammer, Martin
IPC分类号： G06F7/527 , G06F7/57
摘要： The present disclosure describes a digital signal processing (DSP) block that includes a plurality of columns of weight registers and a plurality of inputs configured to receive a first plurality of values and a second plurality of values. The first plurality of values is stored in the plurality of columns of weight registers after being received. In a first mode of operation, the first and second pluralities of values are received via a first portion of the plurality of inputs. In a second mode of operation, the first plurality of values is received via a second portion of the plurality of inputs, and the second plurality of values is received via the first portion of the plurality of inputs. Additionally, the DSP block includes a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.

9. 发明授权

EP2899636B1 A method for testing an Arithmetic logic unit 有权转让
公开(公告)号：EP2899636B1
公开(公告)日：2019-09-11
申请号：EP15159168.2
申请日：2010-07-20
申请人： Honeywell International Inc.
发明人： Bickler, Jason , Brack, Karen
IPC分类号： G06F11/22 , G06F7/499 , G06F7/527 , G06F7/57

10. 发明公开

EP2282261A3 Arithmetic logic unit for use within a flight control system 有权转让
标题翻译：一种用于在飞行控制系统中使用的算术逻辑单元
公开(公告)号：EP2282261A3
公开(公告)日：2011-06-22
申请号：EP10170206.6
申请日：2010-07-20
申请人： Honeywell International Inc.
发明人： Bickler, Jason , Brack, Karen
IPC分类号： G06F7/57 , G06F7/499 , G06F7/527
CPC分类号： G06F17/11 , G06F7/49921 , G06F7/527 , G06F7/57 , G06F11/2226
摘要： An arithmetic logic unit (ALU) (100) for use within a flight control system is provided. The ALU (100) comprises a first register (110) configured to receive a first operand, a second register (111) configured to receive a second operand, and an adder (130) coupled to the first register (110) and the second register (111). The adder (130) is configured to generate a sum of the first operand and the second operand and to generate intermediate sums that are used to determine a product of the first operand and the second operand.

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