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1. 发明授权

EP0437876B1 Multiplieur série programmable 失效
标题翻译：可编程串行乘法器
公开(公告)号：EP0437876B1
公开(公告)日：1996-03-13
申请号：EP90203242.4
申请日：1990-12-10
申请人： LABORATOIRES D'ELECTRONIQUE PHILIPS S.A.S. , Philips Electronics N.V.
发明人： Gobert, Jean
IPC分类号： G06F7/52
CPC分类号： G06F7/527 , G06F7/523

2. 发明授权

EP1038216B1 IMPLEMENTATION OF MULTIPLIERS IN PROGRAMMABLE ARRAYS 无效
标题翻译：乘法器现场可编程阵列
公开(公告)号：EP1038216B1
公开(公告)日：2006-06-14
申请号：EP98960041.6
申请日：1998-12-16
申请人： Elixent Limited
发明人： MARSHALL, Alan David , STANSFIELD, Anthony , VUILLEMIN, Jean
IPC分类号： G06F7/52
CPC分类号： G06F7/527 , G06F7/53 , G06F7/5338 , G06F9/3017 , G06F9/30181 , G06F15/7867
摘要： Implementation of multipliers in an FPGA or similar device containing an array or other aggregation of small processor devices is a significant difficulty, leading to increased cost as a result of the silicon area consumed thereby. There is thus provided a method of multiplying a first number by a second number by use of an array of processing devices, each of said processing devices having a plurality of data inputs, a plurality of data outputs, and an instruction input for control of the function of the processing device, wherein said processing devices and an input for the first number and an input for the second number are interconnected by a freely configurable interconnect, and wherein each processing device calculates a partial product for multiplication of one or more bits of the first number with one or more bits of the second number, and for each processing device: the value received at the instruction input is determined by one or more bits of the first number; data inputs are provided by m bits of the second number, and, if appropriate, a carry input to add a carry from a less significant partial product and/or a summation input to sum all the partial products of the same significance; data outputs are provided as a summation output containing the least significant m bits of the partial product and a carry output containing any more significant bits of the partial product.

3. 发明公开

EP2282261A2 Arithmetic logic unit for use within a flight control system 有权转让
标题翻译：用于飞行控制系统内的算术逻辑单元
公开(公告)号：EP2282261A2
公开(公告)日：2011-02-09
申请号：EP10170206.6
申请日：2010-07-20
申请人： Honeywell International Inc.
发明人： Bickler, Jason , Brack, Karen
IPC分类号： G06F7/57 , G06F7/499
CPC分类号： G06F17/11 , G06F7/49921 , G06F7/527 , G06F7/57 , G06F11/2226
摘要： An arithmetic logic unit (ALU) (100) for use within a flight control system is provided. The ALU (100) comprises a first register (110) configured to receive a first operand, a second register (111) configured to receive a second operand, and an adder (130) coupled to the first register (110) and the second register (111). The adder (130) is configured to generate a sum of the first operand and the second operand and to generate intermediate sums that are used to determine a product of the first operand and the second operand.
摘要翻译：提供了用于飞行控制系统内的算术逻辑单元（ALU）（100）。该ALU（100）包括被配置为接收第一操作数的第一寄存器（110），被配置为接收第二操作数的第二寄存器（111）以及耦合到第一寄存器（110）和第二寄存器（111）。加法器（130）被配置为生成第一操作数和第二操作数的和并且生成用于确定第一操作数和第二操作数的乘积的中间和。

4. 发明授权

EP1078461B1 SCHALTUNGSANORDNUNG MIT EINZELELEKTRON-BAUELEMENTEN UND VERFAHREN ZU DEREN BETRIEB 有权
标题翻译：个别电子组件的电路和方法操作
公开(公告)号：EP1078461B1
公开(公告)日：2002-09-18
申请号：EP99919077.0
申请日：1999-03-15
申请人： Infineon Technologies AG
发明人： RÖSNER, Wolfgang , RAMCKE, Ties , RISCH, Lothar
IPC分类号： H03K19/08
CPC分类号： G06F7/527 , B82Y10/00 , G06F7/502 , G06F7/505 , G06F2207/4828 , H03K19/08 , Y10S977/936 , Y10S977/937 , Y10S977/94
摘要： A circuit with at least five individual electron transistors, whereby three of said transistors (ET1, ET2, ET3) are mounted between a first main node (H1) and an output (A) via a second main node (H2) and a third main node (H3). The fourth individual electron transistor (ET4) is mounted between the second main node and a first supply voltage (V1), whereby the gate electrode pertaining thereto (G4) is connected to the first main node (H1). The fifth individual electron transistor (ET5) is mounted between the third main node (H3) and the first supply voltage (VI), whereby the gate electrode (G5) pertaining thereto is connected to the second main node (H2). The circuit is suitable for use as a full loader and a multiplier.

5. 发明授权

EP0845740B1 A multiplier unit 失效
标题翻译： Multipliziereinheit
公开(公告)号：EP0845740B1
公开(公告)日：2002-09-18
申请号：EP97120773.3
申请日：1997-11-26
申请人： Texas Instruments Incorporated
发明人： Gatherer, Alan , Lemonds, Carl E.
IPC分类号： G06F7/52
CPC分类号： G06F7/527 , G06F7/5324 , G06F2207/388

6. 发明公开

EP0845740A1 A multiplier unit 失效
标题翻译： Multipliziereinheit
公开(公告)号：EP0845740A1
公开(公告)日：1998-06-03
申请号：EP97120773.3
申请日：1997-11-26
申请人： Texas Instruments Incorporated
发明人： Gatherer, Alan , Lemonds, Carl E.
IPC分类号： G06F7/52
CPC分类号： G06F7/527 , G06F7/5324 , G06F2207/388
摘要： In a multiplier unit having a preprocessor stage (11), a multiplier stage (12), and a summation stage (14), the multiplier stage (12) includes a shift register (10), a gate component (21) for controllably transmitting the multiplicand A in a manner determined by a bit signal of multiplier B applied to the gate component (10) control terminal. Partial products are grouped by multiplicand digits and each digit is applied, through delay components (23) determined by the order of the digit, to first terminals of an associated adder components (22). Output signals from each adder component (22) is transmitted through a plurality of delay components (24) and applied to second input terminals of the same adder component (22). In this manner, partial products A p *B q are assembled and the partial products (A 0 +...A M )*B q =A*B q can be applied to the summation unit in a single period.
摘要翻译：在具有预处理器级（11），乘法器级（12）和求和级（14）的乘法器单元中，乘法器级（12）包括移位寄存器（10），用于可控地发送的门组件被乘数A以由施加到门组件（10）控制终端的乘法器B的位信号确定的方式。部分产品通过被乘数数字分组，并且通过由数字的顺序确定的延迟分量（23）将相应的加法器部件（22）的第一端子应用每个数字。来自每个加法器部件（22）的输出信号通过多个延迟部件（24）发送并施加到同一加法器部件（22）的第二输入端子。以这种方式，部分乘积Ap * Bq被组装，并且部分乘积（A0 + ... AM）* Bq = A * Bq可以在单个周期中应用于求和单元。

7. 发明公开

EP2282261A3 Arithmetic logic unit for use within a flight control system 有权转让
标题翻译：一种用于在飞行控制系统中使用的算术逻辑单元
公开(公告)号：EP2282261A3
公开(公告)日：2011-06-22
申请号：EP10170206.6
申请日：2010-07-20
申请人： Honeywell International Inc.
发明人： Bickler, Jason , Brack, Karen
IPC分类号： G06F7/57 , G06F7/499 , G06F7/527
CPC分类号： G06F17/11 , G06F7/49921 , G06F7/527 , G06F7/57 , G06F11/2226
摘要： An arithmetic logic unit (ALU) (100) for use within a flight control system is provided. The ALU (100) comprises a first register (110) configured to receive a first operand, a second register (111) configured to receive a second operand, and an adder (130) coupled to the first register (110) and the second register (111). The adder (130) is configured to generate a sum of the first operand and the second operand and to generate intermediate sums that are used to determine a product of the first operand and the second operand.

8. 发明公开

EP1817661A2 MULTIPLY INSTRUCTIONS FOR MODULAR EXPONENTIATION 审中-公开
标题翻译：模块化幂乘法指令
公开(公告)号：EP1817661A2
公开(公告)日：2007-08-15
申请号：EP05818045.6
申请日：2005-09-01
申请人： Cavium Networks, Inc.
发明人： CARLSON, David, A.
IPC分类号： G06F7/52
CPC分类号： G06F7/527 , G06F7/723 , G06F9/3001 , G06F9/30065 , G06F9/30112 , G06F9/383
摘要： A method and apparatus for increasing performance of a multiplication operation in a processor. The processor's instruction set includes multiply instructions that can be used to accelerate modular exponentiation. Prior to issuing a sequence of multiply instructions for the multiplication operation, a multiplier register in a multiply unit in the processor is loaded with the value of the multiplier. The multiply unit stores intermediate results of the multiplication operation in redundant format. The intermediate results are shifted and stored in the product register in the multiply unit so that carries between intermediate results are handled within the multiply unit.

9. 发明公开

EP1449065A2 CIRCUIT FOR PERFORMING A DIGITAL LOGIC OPERATION 审中-公开
标题翻译：电路是否实现数字逻辑运算
公开(公告)号：EP1449065A2
公开(公告)日：2004-08-25
申请号：EP02708584.4
申请日：2002-03-26
申请人： Koninklijke Philips Electronics N.V.
发明人： BOUDEWIJNS, Arnoldus, J., J.
IPC分类号： G06F7/48
CPC分类号： H03K19/0016 , G06F7/00 , G06F7/48 , G06F7/527 , H03K19/01728
摘要： A circuit for performing a digital logic operation comprising a start/stop oscillator (1) is proposed. The start/stop oscillator (1) starts in response to a system clock signal and is stopped a predetermined period of time after the digital logic operation has been completed. The period during which pulses are supplied by the start/stop oscillator (1) is shorter than the period of the system clock.

10. 发明公开

EP0437876A1 Multiplieur série programmable 失效
标题翻译： Multiplikator程序员。
公开(公告)号：EP0437876A1
公开(公告)日：1991-07-24
申请号：EP90203242.4
申请日：1990-12-10
申请人： LABORATOIRES D'ELECTRONIQUE PHILIPS S.A.S. , Philips Electronics N.V.
发明人： Gobert, Jean
IPC分类号： G06F7/52
CPC分类号： G06F7/527 , G06F7/523
摘要： Multiplieur série programmable opérant la multiplication d'un multiplicande par une constante fixe codée sur r bits. Il comprend une batterie de (r/2)-1 cellules d'addition (11₀ - 11 (r/2)-2 ) connectées entre elles en série par une première entrée, un registre à décalage formé de (r/2)+1 bascules initialisables (10₀ - 10 r/2 ), et des moyens de connexions (17) qui permettent de programmer le multiplieur série pour opérer la multiplication par la constante fixe C, soit à l'aide de la valeur +C lorsque la constante C renferme en notation binaire un nombre de 1 inférieur ou égal au nombre de 0, soit à l'aide de la valeur -C dans le cas inverse. Il peut opérer avec une constante fixe C signée.
L'invention concerne également un processeur de calcul qui effectue une transformée linéaire de données numériques mettant en oeuvre un tel multiplieur. Pour chaque multiplication de la transformée linéaire, le processeur peut opérer soit avec la constante proprement dite soit avec l'opposé de la constante. Pour chaque étape du calcul, le résultat correct est ensuite déterminé en inversant le type d'opérateur prévu pour l'opération de sommation considérée.
Application : multiplieur série, traitement du signal.
摘要翻译：可编程串行乘法器执行被乘数乘以一个固定常数，并将其编码在r位上。它包括通过第一输入串联在一起的（r / 2）-1个加法单元（110-11（r / 2）-2）的范围，由（r / 2）+ 1可初始化翻转（100-10r / 2）和连接装置（17），其允许对串行乘法器进行编程，以便在常数C以二进制符号表示的数字中使用值+ C来执行乘以固定常数C 小于或等于0的数字，或者在相反的情况下使用值-C。它可以用固定的有符号常数C来执行。本发明还涉及一种使用这种乘法器执行数字数据的线性变换的计算处理器。对于线性变换的每个乘法，处理器可以以常数适当或与常数相反的方式运行。对于每个计算步骤，接下来通过反转为所讨论的求和操作提供的操作者的类型来确定正确的结果。 ...应用：串行乘法器，信号处理。 ... ...... ...

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