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1. 发明授权

EP0242506B1 Sidewall spacers for cmos circuits stress relief/isolation and method for making 失效
标题翻译：用于CMOS电路的紧固件间隔件应力消除/隔离和制造方法
公开(公告)号：EP0242506B1
公开(公告)日：1993-03-24
申请号：EP87100962.7
申请日：1987-01-23
申请人： International Business Machines Corporation
发明人： Dally, Anthony John , Ogura, Seiki , Riseman, Jacob , Rovedo, Nivo
IPC分类号： H01L29/78 , H01L21/225 , H01L21/76
CPC分类号： H01L21/76224

2. 发明公开

EP0242506A2 Sidewall spacers for cmos circuits stress relief/isolation and method for making 失效
标题翻译：侧壁间隔物用于接收电压和CMOS电路的隔离，以及制造过程。
公开(公告)号：EP0242506A2
公开(公告)日：1987-10-28
申请号：EP87100962.7
申请日：1987-01-23
申请人： International Business Machines Corporation
发明人： Dally, Anthony John , Ogura, Seiki , Riseman, Jacob , Rovedo, Nivo
IPC分类号： H01L29/78 , H01L21/225 , H01L21/76
CPC分类号： H01L21/76224
摘要： A method for forming fully recessed (planar) isolation regions (22,24) on a semiconductor for the manufacture of CMOS integrated circuits, and the resulting semiconductor structure, comprising in a P doped silicon substrate (10) with mesas (22,24) formed therein, forming low viscosity sidewall spacers (30) of borosilicate glass in contact with the sidewalls of those mesas designated to have N-channel devices formed therein; then filling the trenches (11,12) in the substrate adjacent to the mesas with TEOS 32); and heating the structure until the boron in the sidewall spacers diffuses into the sidewalls of the designated mesas to form channel stops (40,42). These sidewall spacers reduce the occurrence of cracks in the TEOS by relieving internal mechanical stress therein and permit the formation of channel stops via diffusion, thereby permitting mesa walls to be substantially vertical.
摘要翻译：一种用于形成在半导体完全凹入（平面）的隔离区（22,24），用于CMOS的制造方法的集成电路，产生的半导体结构，在P掺杂硅衬底与台面，其包含（10）（22,24）形成于其中，形成与指定为具有N沟道器件形成于其中台面的那些侧壁接触的硼硅酸盐玻璃的低粘度侧壁间隔物（30）; 然后填充在邻近与TEOS 32）的台面的衬底沟槽（11,12）; 并加热该结构，直到在侧壁间隔件中的硼扩散进入指定台面以形成通道的侧壁停止（40,42）。这些侧壁间隔物通过在其中缓和内部机械应力减小TEOS裂纹的产生，并允许信道的形成通过扩散停止，由此允许台面的壁是基本垂直的。

3. 发明公开

EP0495329A2 High performance/high density bicmos process 失效
标题翻译： Verfahren zum Herstellen eines BiCMOS hoher Leistung und hoher Dichte。
公开(公告)号：EP0495329A2
公开(公告)日：1992-07-22
申请号：EP91480186.5
申请日：1991-12-17
申请人： International Business Machines Corporation
发明人： Monkowski, Michael , Ogura, Seiki , Rovedo, Nivo , Shepard, Joseph Francis
IPC分类号： H01L21/82
CPC分类号： H01L21/2257 , H01L21/763 , H01L21/8249
摘要： An integrated circuit using high-performance bipolar and CMOS transistor elements on a single chip is fabricated by a simplified process requiring minimal, if any, changes in the process used for forming either type of device in accordance with a variety of possible device designs. The method according to the invention makes maximal use of self-aligned and self-masking processes to reduce the number of processing steps. The number of processing steps is further reduced by performing some steps concurrently on different device types. Further, the masking steps which are employed are reasonably misregistration tolerant, resulting in high manufacturing yield for the process. Consequently, the process according to the invention substantially eliminates the existence of trade-offs between element performance, integration density and process complexity and cost when plural technologies are integrated on the same chip.
摘要翻译：在单个芯片上使用高性能双极和CMOS晶体管元件的集成电路是通过简化的工艺制造的，其需要根据各种可能的器件设计来形成任何一种器件的工艺的最小化（如果有的话）变化。根据本发明的方法最大限度地利用自对准和自掩蔽过程来减少处理步骤的数量。通过在不同的设备类型上同时执行一些步骤来进一步减少处理步骤的数量。此外，所使用的掩蔽步骤是合理的对准容限，导致该方法的高制造产量。因此，当多个技术集成在同一芯片上时，根据本发明的方法基本上消除了元件性能，集成密度和工艺复杂性以及成本之间的权衡的存在。

4. 发明授权

EP0224646B1 Method for removing protuberances at the surface of a semiconductor wafer using a chem-mech polishing technique 失效
标题翻译：使用CHEM-MECH抛光技术在半导体波长表面移除原子的方法
公开(公告)号：EP0224646B1
公开(公告)日：1991-09-25
申请号：EP86110462.8
申请日：1986-07-29
申请人： International Business Machines Corporation
发明人： Beyer, Klaus Dietrich , Makris, James Steve , Mendel, Eric , Nummy, Karen Ann , Ogura, Seiki , Riseman, Jacob , Rovedo, Nivo
IPC分类号： H01L21/306 , H01L21/76
CPC分类号： H01L21/763 , H01L21/31053 , H01L21/743 , H01L21/76202

5. 发明公开

EP0242506A3 Sidewall spacers for cmos circuits stress relief/isolation and method for making 失效
标题翻译：用于CMOS电路的紧固件间隔件应力消除/隔离和制造方法
公开(公告)号：EP0242506A3
公开(公告)日：1990-03-14
申请号：EP87100962.7
申请日：1987-01-23
申请人： International Business Machines Corporation
发明人： Dally, Anthony John , Ogura, Seiki , Riseman, Jacob , Rovedo, Nivo
IPC分类号： H01L29/78 , H01L21/225 , H01L21/76
CPC分类号： H01L21/76224
摘要： A method for forming fully recessed (planar) isolation regions (22,24) on a semiconductor for the manufacture of CMOS integrated circuits, and the resulting semiconductor structure, comprising in a P doped silicon substrate (10) with mesas (22,24) formed therein, forming low viscosity sidewall spacers (30) of borosilicate glass in contact with the sidewalls of those mesas designated to have N-channel devices formed therein; then filling the trenches (11,12) in the substrate adjacent to the mesas with TEOS 32); and heating the structure until the boron in the sidewall spacers diffuses into the sidewalls of the designated mesas to form channel stops (40,42). These sidewall spacers reduce the occurrence of cracks in the TEOS by relieving internal mechanical stress therein and permit the formation of channel stops via diffusion, thereby permitting mesa walls to be substantially vertical.

6. 发明授权

EP0354153B1 Vertical bipolar transistor 失效
标题翻译：垂直双极晶体管
公开(公告)号：EP0354153B1
公开(公告)日：1993-04-21
申请号：EP89480105.9
申请日：1989-06-29
申请人： International Business Machines Corporation
发明人： Akbar, Shah , Kroesen, Patricia Lavelle , Ogura, Seiki , Rovedo, Nivo
IPC分类号： H01L29/72 , H01L29/52 , H01L29/60
CPC分类号： H01L29/66272 , H01L29/0821 , H01L29/1004 , H01L29/732 , Y10S148/009 , Y10S148/011

7. 发明授权

EP0144762B1 Methods for forming closely spaced openings and for making contacts to semiconductor device surfaces 失效
标题翻译：用于形成闭合间隔开口并用于制造与半导体器件表面的接触的方法
公开(公告)号：EP0144762B1
公开(公告)日：1988-10-19
申请号：EP84113321.8
申请日：1984-11-06
申请人： International Business Machines Corporation
发明人： Ogura, Seiki , Riseman, Jacob , Rovedo, Nivo , Shepard, Joseph Francis
IPC分类号： H01L21/28 , H01L21/60
CPC分类号： H01L29/6625 , H01L29/66272 , H01L29/66606

8. 发明公开

EP0144762A1 Methods for forming closely spaced openings and for making contacts to semiconductor device surfaces 失效
标题翻译：制造紧密间隔的孔中的与用于半导体器件的表面相接触的方法。
公开(公告)号：EP0144762A1
公开(公告)日：1985-06-19
申请号：EP84113321.8
申请日：1984-11-06
申请人： International Business Machines Corporation
发明人： Ogura, Seiki , Riseman, Jacob , Rovedo, Nivo , Shepard, Joseph Francis
IPC分类号： H01L21/28 , H01L21/60
CPC分类号： H01L29/6625 , H01L29/66272 , H01L29/66606
摘要： Methods for producing integrated circuit structures are described with reference to a small area lateral bipolar transistor comprising a semiconductor body (10) having surface regions thereof isolated from other such regions by a pattern of dielectric isolation.
At least two narrow width PN junction regions are located within at least one of the surface regions. Substantially vertical conformal conductive layers (62, 64) electrically contact each of the PN junction regions which serve as the emitter (56) and collector (58) regions for the bipolar transistor, A junction base region (74) of an opposite conductivity is located between and contiguous to the emitter and the collector junctions. Substantially horizontal conductive layers (22) are in electrical contact with an edge of each of the vertical conductive layers (62, 64) and separated from the surface regions by a first electrically insulating layer (20). A second insulating layer (70) covers the conformal conductive layers. The horizontal conductive layer is patterned so as to form conductive lines electrically separated from one another. A third insulating layer (24) is located over the patterned horizontal conductive layers. An ohmic contact (80, 84) is made to each of the horizontal conductive layers (22) through an opening in the third insulating layer (24) which effectively makes electrical contacts to the emitter (56) and collector (58) regions via the patterned horizontal conductive layers (22) and the vertical conductive layers (62, 64). Another contact (82) is made to the base region (74) which contact is separated from the vertical conductive layers (62, 64) by the second insulating layer (70).
摘要翻译：的制造集成电路结构的方法是参照小区域横向双极性晶体管，其包含具有由介电隔离的图案检查其他区域相隔离的表面区域的半导体主体（10）。 ... 至少两个窄的宽度PN结区位于所述表面区域中的至少一个内。基本上垂直的保形导电层（62，64）电接触的每一个作为所述发射器（56）和集电极（58），用于双极性晶体管的区域的PN结区域。相反的导电性的结基极区域（74）位于与邻接发射极和集电极结之间。大致水平导电层（22）是在每个垂直导电层（62，64）的边缘的电接触，并通过第一电绝缘层（20）从所述表面区域分离。第二绝缘层（70）覆盖所述保形导电层。该水平导电层被图案化，从而形成导电线彼此电分离。第三绝缘层（24）位于所述图案化的水平的导电层。欧姆接触（80，84）通过对各水平导电层（22）制成的第三绝缘层在开口（24）通过（58）的区域，有效地使电接触到发射极（56）和收集器图案化的水平导电层（22）和所述垂直导电层（62，64）。另一个触头（82）到哪个触点从垂直导电层（62，64）由所述第二绝缘层（70）分离的基极区域（74）制成。

9. 发明授权

EP0375585B1 Method for manufacturing a BI-CMOS device 失效
标题翻译：一种制造的BiCMOS布置的方法
公开(公告)号：EP0375585B1
公开(公告)日：1996-04-10
申请号：EP89480174.5
申请日：1989-11-07
申请人： International Business Machines Corporation
发明人： Ogura, Seiki , Rovedo, Nivo
IPC分类号： H01L21/82
CPC分类号： H01L21/8249 , H01L27/0623 , H01L27/0711

10. 发明公开

EP0568475A1 Method of forming thin silicon mesas having uniform thickness 失效
标题翻译： Verfahren zur Herstellung vondünnenSiliziummesas mit gleicher Dicke。
公开(公告)号：EP0568475A1
公开(公告)日：1993-11-03
申请号：EP93480024.4
申请日：1993-03-23
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Doerre, George William , Ogura, Seiki , Rovedo, Nivo
IPC分类号： H01L21/84 , H01L21/302 , H01L21/76
CPC分类号： H01L21/76251 , H01L21/31053 , H01L21/32105 , Y10S148/05 , Y10S438/97
摘要： An SOI wafer (10/20) has an epitaxial device layer (30) of initial thickness that is formed into a set of mesas (40) in the interval between which a temporary layer (42) of polysilicon is blanket deposited to a precisely controlled thickness. This polysilicon is entirely converted in a self-limiting process to an oxide etch stop pads (45) (having a thickness greater than the initial thickness) except on the mesa side walls. The mesas are thinned by a chemical mechanical polishing technique until the mesa is the same level as the top surface of the new oxide. The etch stop layer of oxide forming pads (45) is not removed but serves both as an isolating layer to provide dielectric isolation between final mesas (40') in the final circuit and also as a visual gauge to determine the time when the polishing process should stop.
摘要翻译： SOI晶片（10/20）具有初始厚度的外延器件层（30），该外延器件层（30）形成为一组台阶（40），其中多晶硅的暂时层（42）被毯式沉积到精确控制厚度。除了台面侧壁之外，该多晶硅在自限制过程中完全转换为氧化物蚀刻停止焊盘（45）（具有大于初始厚度的厚度）。台面通过化学机械抛光技术变薄，直到台面与新氧化物的顶表面相同。氧化物形成焊盘（45）的蚀刻停止层不被去除，而是用作隔离层，以在最终电路中的最终台面（40'）之间提供绝缘隔离，并且还可以作为视觉仪器来确定抛光过程应该停止

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