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1. 发明授权

US06710814B1 Digital broadcast receiving system for detecting short-breaks and holding information based on same 有权
标题翻译：数字广播接收系统，用于检测短信和保存信息
公开(公告)号：US06710814B1
公开(公告)日：2004-03-23
申请号：US09555479
申请日：2000-07-26
申请人： Kohei Ueno , Akinori Hashimoto , Hisakazu Katoh , Hajime Matsumura , Tomohiro Saito
发明人： Kohei Ueno , Akinori Hashimoto , Hisakazu Katoh , Hajime Matsumura , Tomohiro Saito
IPC分类号： H04N504
CPC分类号： H04N21/4382 , H04N5/04 , H04N5/4401 , H04N21/4305 , H04N21/44209
摘要： A receiver is constructed so that it detects a short-break of a digital broadcasting wave by the absence of a synchronizing code or by a transmission control signal multiplexed with the broadcasting wave and, according to the short-break detection signal, holds data and state information (program arrangement, and reference time information) obtained by an antenna and converter (1), tuner and digital decoding portion (2), an error correction code decoding portion (3), a stream multiplexed signal separating portion (4), an audio/video decoding portion (5) and the other components and performs a process for optimally changing characteristics of closed loops for establishing synchronization.
摘要翻译：接收机被构造为通过不存在同步码或通过与广播波复用的传输控制信号来检测数字广播波的短暂断裂，并且根据短路检测信号保存数据和状态通过天线和转换器（1），调谐器和数字解码部分（2），纠错码解码部分（3），流多路复用信号分离部分（4）获得的信息（节目安排和参考时间信息）音频/视频解码部分（5）和其他组件，并且执行用于最佳地改变用于建立同步的闭环的特性的处理。

2. 发明授权

US06356316B1 Microkeyer: microcomputer broadcast video overlay device and method 失效
标题翻译：微键盘：微电脑广播视频覆盖设备及方法
公开(公告)号：US06356316B1
公开(公告)日：2002-03-12
申请号：US06692053
申请日：1985-01-15
申请人： Henry B. Mistrot
发明人： Henry B. Mistrot
IPC分类号： H04N504
CPC分类号： H04N9/75 , G09G5/12 , G09G2340/125 , H04N5/445 , H04N9/641 , H04N21/478
摘要： Broadcast standard format video signals such as that adopted by the National Television Standards Committee (NTSC) or the European standard format of Phase Alternating Line (PAL) and some broadcast “compatible” video signals are used as inputs to a microkeyer to synchronize a microcomputer's display in a manner that allows full and complete merging of the two signals in the broadcast video domain by, for example, additive (mixing) or non-additive (keying) processes. The required synchronization in turn makes possible incorporation in any video space a variety of computer generated visuals such as illustrative graphics, titling and any other data displayed in the video. The merged video signal from this device may then be displayed on a television monitor, or transmitted, or received, or recorded by a video recorder or processed by a standard broadcast means for example. When applied to any common microcomputer display in its most fundamental form, no additional software is required.
摘要翻译：广播标准格式的视频信号，例如由国家电视标准委员会（NTSC）采用的标准格式视频信号或者相位交替线（PAL）的欧洲标准格式和一些广播的“兼容”视频信号被用作微键盘的输入以使微型计算机的显示器以允许通过例如添加（混合）或非添加（键控）处理在广播视频域中完全和完全地合并两个信号的方式。所需的同步又使得可以在任何视频空间中并入各种计算机生成的视觉效果，例如说明图形，标题和视频中显示的任何其他数据。然后，来自该设备的合并的视频信号可以显示在电视监视器上，或者由视频记录器发送或接收或记录，或者例如由标准广播装置处理。当以最基本的形式应用于任何普通微机显示器时，不需要额外的软件。

3. 发明授权

US06297849B1 Output timebase corrector 失效
标题翻译：输出时基校正器
公开(公告)号：US06297849B1
公开(公告)日：2001-10-02
申请号：US09213532
申请日：1998-12-17
申请人： Jeroen H. C. J. Stessen , Antonius H. H. J. Nillesen
发明人： Jeroen H. C. J. Stessen , Antonius H. H. J. Nillesen
IPC分类号： H04N504
CPC分类号： H03L7/0994 , H04N5/126
摘要： An output timebase corrector converts orthogonal sampled video (VS) into asynchronous sampled video (VOS) with asynchronous sample values occurring at clock instants (TC) of a clock signal (CLK). The asynchronous sampled video (VOS) is displayed on a display screen of a display device (DD). A discrete time oscillator (DTO) of a time-discrete phase-locked loop (PLL) supplies a time base signal (OS). The time-discrete phase-locked loop (PLL) determines a phase difference (PE) between the time base signal (OS) and reference instants (FB) indicating a timing of a line deflection of the display device (DD) to obtain the time base signal (OS) being locked to the reference instants (FB). The time base signal (OS) controls a sample rate converter (SRC) such that the asynchronous video values (VOS) which occur at the clock instants (TC) are interpolated from the orthogonal sampled video (VS) by the sample rate converter (SRC) such that the video signal is displayed on the correct position on the display screen. In the output timebase corrector according to the invention all circuits are clocked by clock signals (CLK) originating from one and the same clock generator (OSC).
摘要翻译：输出时基校正器将正交采样视频（VS）转换成异步采样视频（VOS），其中异步采样值出现在时钟信号（CLK）的时钟时刻（TC）。异步采样视频（VOS）显示在显示设备（DD）的显示屏幕上。时分离锁相环（PLL）的离散时间振荡器（DTO）提供时基信号（OS）。时间离散锁相环（PLL）确定时基信号（OS）和指示显示设备（DD）的线路偏转的定时的参考时刻（FB）之间的相位差（PE），以获得时间基本信号（OS）被锁定到参考时刻（FB）。时基信号（OS）控制采样率转换器（SRC），使得在时钟时刻（TC）发生的异步视频值（VOS）由采样率转换器（SRC）从正交采样视频（VS）内插），使得视频信号显示在显示屏上的正确位置。在根据本发明的输出时基校正器中，所有电路由源自同一个时钟发生器（OSC）的时钟信号（CLK）计时。

4. 发明授权

US06760076B2 System and method of synchronization recovery in the presence of pilot carrier phase rotation for an ATSC-HDTV receiver 失效
标题翻译：在存在ATSC-HDTV接收机的导频载波相位旋转的同时恢复的系统和方法
公开(公告)号：US06760076B2
公开(公告)日：2004-07-06
申请号：US09732583
申请日：2000-12-08
申请人： Karl R. Wittig
发明人： Karl R. Wittig
IPC分类号： H04N504
CPC分类号： H04N21/4383 , H04L1/004 , H04L2027/0057 , H04N5/08 , H04N5/4401 , H04N7/56 , H04N11/002 , H04N21/42607 , H04N21/4382
摘要： There is disclosed a system and method for recovering a recurring data segment synchronization pattern in the presence of an arbitrary phase rotation of a pilot carrier by detecting and compensating for the amount of the phase rotation. The system comprises a first synchronization pattern detector capable of receiving a real component of a complex signal and detecting a data segment synchronization pattern on the real component, and a second synchronization pattern detector capable of receiving an imaginary component of a complex signal and detecting a data segment synchronization pattern on the imaginary component. There is also disclosed a method for compensating a pilot carrier phase rotation comprising the steps of determining the angle of pilot carrier phase rotation present in a complex signal and rotating the pilot carrier signal through the same angle in the opposite direction. Methods are also disclosed for compensating signal gain in a complex signal in which pilot carrier phase rotation has occurred.
摘要翻译：公开了一种系统和方法，用于通过检测和补偿相位旋转的量来在导频载波的任意相位旋转的存在下恢复重复的数据段同步模式。该系统包括第一同步模式检测器，能够接收复数信号的实分量并检测实部分上的数据段同步模式;以及第二同步模式检测器，能够接收复信号的虚分量并检测数据虚分量上的段同步模式。还公开了一种用于补偿导频载波相位旋转的方法，包括以下步骤：确定复信号中存在的导频载波相位旋转的角度，并使导频载波信号沿相反方向旋转相同的角度。还公开了在发生导频载波相位旋转的复信号中补偿信号增益的方法。

5. 发明授权

US06275265B1 Video signal synchronizing apparatus 失效
标题翻译：视频信号同步装置
公开(公告)号：US06275265B1
公开(公告)日：2001-08-14
申请号：US09100461
申请日：1998-06-19
申请人： Hiromitsu Kimura , Shinichi Takahashi
发明人： Hiromitsu Kimura , Shinichi Takahashi
IPC分类号： H04N504
CPC分类号： H04N5/126
摘要： An apparatus for performing a generator locking for a video signal including a first video processing circuit for processing an input video signal, an expansion module having a second video processing circuit and a delay circuit having a delay time introduced by said second video processing circuit, a synchronizing signal separating circuit for separating a synchronizing signal from an external reference signal, and a phase-lock loop circuit for generating a reference control signal for said first video processing circuit as well as a phase comparison signal. Said phase comparison signal is fed-back to the phase-lock loop circuit by means of said delay circuit. Although the expansion module is connected to the expansion slot, a phase of a finally obtained video signal is remained in a same fixed relationship as a phase relationship when a connection board is connected to the expansion slot.
摘要翻译：一种用于执行视频信号的发生器锁定的装置，包括用于处理输入视频信号的第一视频处理电路，具有第二视频处理电路的扩展模块和具有由所述第二视频处理电路引入的延迟时间的延迟电路，用于从外部参考信号分离同步信号的同步信号分离电路，以及用于产生所述第一视频处理电路的参考控制信号的相位锁定环路电路以及相位比较信号。所述相位比较信号通过所述延迟电路反馈到锁相环电路。虽然扩展模块连接到扩展槽，但是当连接板连接到扩展槽时，最终获得的视频信号的相位与相位关系保持相同的固定关系。

6. 发明授权

US06177959B1 Circuit and method for generating a clock signal synchronized with time reference signals associated with television signals 失效
标题翻译：用于产生与电视信号相关联的时间参考信号同步的时钟信号的电路和方法
公开(公告)号：US06177959B1
公开(公告)日：2001-01-23
申请号：US09001413
申请日：1997-12-31
申请人： Vlad Bril
发明人： Vlad Bril
IPC分类号： H04N504
CPC分类号： H03L7/0805 , G09G5/18 , G09G2340/125 , H03L7/06 , H04N5/04 , H04N5/44504 , H04N21/4305
摘要： A clock generation circuit for use in a television system displaying images encoded in television signals and images represented by network application data. The clock generation circuit generates a clock signal synchronized with HSYNC signals of the television signals. The clock generation circuit includes a phase-lock-loop (PLL) circuit and a tracking block. PLL circuit includes an oscillator (e.g., VCO) driven by an error signal to generate an internal periodic signal having frequency substantially equal to the frequency of the desired clock signal. The tracking block includes a resettable VCO (RVCO) driven by the error signal. A restart signal is asserted prior to the expected arrival time of the HSYNC edge to cause the RVCO to stop generating the desired clock signal. The restart signal is deasserted on receiving the HSYNC edge to cause the RVCO to start generating the clock signal. Accordingly, the clock signal is synchronized with the HSYNC signal.
摘要翻译：一种在电视系统中使用的时钟生成电路，其显示以电视信号编码的图像和由网络应用数据表示的图像。时钟发生电路产生与电视信号的HSYNC信号同步的时钟信号。时钟发生电路包括锁相环（PLL）电路和跟踪块。 PLL电路包括由误差信号驱动的振荡器（例如VCO），以产生具有基本上等于期望时钟信号频率的频率的内部周期信号。跟踪块包括由误差信号驱动的可复位VCO（RVCO）。在HSYNC边缘的预期到达时间之前断言重启信号，以使RVCO停止产生期望的时钟信号。接收到HSYNC边沿后，重新启动信号被置为无效，使RVCO开始产生时钟信号。因此，时钟信号与HSYNC信号同步。

7. 发明授权

US06816202B1 Picture frame generating circuit and digital television system using the same 失效
标题翻译：相框生成电路和数字电视系统使用相同
公开(公告)号：US06816202B1
公开(公告)日：2004-11-09
申请号：US09671151
申请日：2000-09-28
申请人： Isao Sezaki
发明人： Isao Sezaki
IPC分类号： H04N504
CPC分类号： H04N5/44504 , H04N5/45 , H04N21/4316
摘要： A picture frame generating circuit has: a coordinate value calculation processor that calculates frame start position (X, Y), picture end position (X, Y), frame end position (X, Y) using calculation start signal as activation signal, based on picture position (X, Y) registers, picture size (X, Y) registers and frame size register which are written through a data bus, the processor allowing frame color data to be written into frame color register to designate the color of frame through the data bus: and a selection circuit of frame and picture to which the frame start position (X, Y), picture end position (X, Y), frame end position (X, Y), picture position (X, Y) registers, frame color data, picture data, horizontal display position and vertical display position are input, the circuit selecting the picture data or frame color data and outputs the selected one as display data.

8. 发明授权

US06803965B1 Method of and apparatus for measuring horizontal frequency 失效
标题翻译：测量水平频率的方法和装置
公开(公告)号：US06803965B1
公开(公告)日：2004-10-12
申请号：US09477459
申请日：2000-01-04
申请人： Hirotaka Takegoshi , Nobuo Yamazaki
发明人： Hirotaka Takegoshi , Nobuo Yamazaki
IPC分类号： H04N504
CPC分类号： H04N17/00
摘要： A method of measuring horizontal frequency, which comprises the steps of resetting an 8-bit counter, which counts horizontal synchronous pulses separated from a video signal, at a time point corresponding to an edge of a vertical synchronous signal separated from the video signal, causing a data latch portion, which is operative to latch count data obtained from a 16-bit counter operative to count clock pulses having a predetermined frequency, to latch the count data obtained from the 16-bit counter at a time point corresponding to an edge of a bit output signal obtained from the seventh bit position of the 8-bit counter, detecting a period which corresponds to 128 times a horizontal period of the video signal based on a difference between counted values represented respectively by a couple of count data latched successively by the data latch portion, and measuring horizontal frequency of the video signal by calculating the horizontal frequency on the strength of the period corresponding to 128 times the horizontal period.
摘要翻译：一种测量水平频率的方法，包括以下步骤：在对应于与视频信号分离的垂直同步信号的边缘的时间点上复位计数从视频信号分离的水平同步脉冲的8位计数器，引起数据锁存部分，用于锁存从16位计数器获得的计数数据，该计数数据可操作用于计数具有预定频率的时钟脉冲，以在与16位计数器的边缘对应的时间点锁存从16位计数器获得的计数数据从8位计数器的第7位位置获得的位输出信号，根据由相继锁存的数个计数数据表示的计数值之间的差值，检测对应于视频信号的水平周期的128倍的周期数据锁存部分，并且通过根据周期的强度计算水平频率来测量视频信号的水平频率 ng到水平周期的128倍。

9. 发明授权

US06583822B1 Timing recovery device of digital TV 有权
标题翻译：数字电视定时恢复装置
公开(公告)号：US06583822B1
公开(公告)日：2003-06-24
申请号：US09467374
申请日：1999-12-21
申请人： Jung Sig Jun
发明人： Jung Sig Jun
IPC分类号： H04N504
CPC分类号： H04N5/08 , H04N5/04 , H04N5/4401
摘要： A timing recovery device in a digital television receiver using a VSB system is disclosed. In the present invention, the timing recovery device independently determines whether the detected hsync signal is reliable and operates if the detected hsync signal is reliable.
摘要翻译：公开了一种使用VSB系统的数字电视接收机中的定时恢复装置。在本发明中，定时恢复装置独立地确定检测到的同步信号是否可靠，并且如果检测到的同步信号是可靠的，则其操作。

10. 发明授权

US06525776B1 Information compressing apparatus and method 有权
标题翻译：信息压缩装置及方法
公开(公告)号：US06525776B1
公开(公告)日：2003-02-25
申请号：US09363093
申请日：1999-07-30
申请人： Seiji Higurashi
发明人： Seiji Higurashi
IPC分类号： H04N504
CPC分类号： H04N19/85
摘要： An information processing apparatus includes an address generation circuit for generating an address signal. A memory operates for storing an information signal containing a video signal in response to the address signal. The address signal is periodically updated. A compression processing circuit operates for reading out the information signal from the memory, and subjecting the readout information signal to a compressively encoding process. A head of every frame represented by the information signal is detected. A state of the address signal is stored which corresponds to the detected frame head. Detection is made as to whether or not the information signal becomes discontinuous. The updating of the address signal and also the operation of the compression processing circuit are suspended when it is detected that the information signal becomes discontinuous. Detection is made as to whether or not the information signal returns to a normally continuous state after the information signal becomes discontinuous. The updating of the address is started from the stored state when it is detected that the information signal returns to its normally continuous state after the information signal becomes discontinuous.
摘要翻译：信息处理装置包括用于产生地址信号的地址产生电路。存储器用于响应于地址信号存储包含视频信号的信息信号。定期更新地址信号。压缩处理电路用于从存储器读出信息信号，并对读出的信息信号进行压缩编码处理。检测由信息信号表示的每帧的头部。存储对应于检测到的帧头的地址信号的状态。检测信息信号是否不连续。当检测到信息信号变得不连续时，地址信号的更新以及压缩处理电路的操作被暂停。在信息信号变得不连续之后，检测信息信号是否恢复正常连续状态。当信息信号变得不连续时，当检测到信息信号恢复到其正常连续状态时，地址的更新从存储状态开始。

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