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1. 发明授权

US06710814B1 Digital broadcast receiving system for detecting short-breaks and holding information based on same 有权
标题翻译：数字广播接收系统，用于检测短信和保存信息
公开(公告)号：US06710814B1
公开(公告)日：2004-03-23
申请号：US09555479
申请日：2000-07-26
申请人： Kohei Ueno , Akinori Hashimoto , Hisakazu Katoh , Hajime Matsumura , Tomohiro Saito
发明人： Kohei Ueno , Akinori Hashimoto , Hisakazu Katoh , Hajime Matsumura , Tomohiro Saito
IPC分类号： H04N504
CPC分类号： H04N21/4382 , H04N5/04 , H04N5/4401 , H04N21/4305 , H04N21/44209
摘要： A receiver is constructed so that it detects a short-break of a digital broadcasting wave by the absence of a synchronizing code or by a transmission control signal multiplexed with the broadcasting wave and, according to the short-break detection signal, holds data and state information (program arrangement, and reference time information) obtained by an antenna and converter (1), tuner and digital decoding portion (2), an error correction code decoding portion (3), a stream multiplexed signal separating portion (4), an audio/video decoding portion (5) and the other components and performs a process for optimally changing characteristics of closed loops for establishing synchronization.
摘要翻译：接收机被构造为通过不存在同步码或通过与广播波复用的传输控制信号来检测数字广播波的短暂断裂，并且根据短路检测信号保存数据和状态通过天线和转换器（1），调谐器和数字解码部分（2），纠错码解码部分（3），流多路复用信号分离部分（4）获得的信息（节目安排和参考时间信息）音频/视频解码部分（5）和其他组件，并且执行用于最佳地改变用于建立同步的闭环的特性的处理。

2. 发明授权

US06490010B1 AFC circuit, carrier recovery circuit and receiver device capable of regenerating a carrier reliably even at the time of low C/N ratio 有权
标题翻译： AFC电路，载波恢复电路和接收机装置，即使在低C / N比下也能够可靠地再生载波
公开(公告)号：US06490010B1
公开(公告)日：2002-12-03
申请号：US09308263
申请日：1999-05-14
申请人： Kazuhiko Shibuya , Junji Kumada , Yuichi Iwadate , Hiroyuki Hamazumi , Toshihiro Nomoto , Kouichi Takano , Tomohiro Saito , Shoji Tanaka , Fumiaki Minematsu , Akinori Hashimoto , Shigeyuki Itoh , Hajime Matsumura , Hisakazu Katoh , Masaru Takechi
发明人： Kazuhiko Shibuya , Junji Kumada , Yuichi Iwadate , Hiroyuki Hamazumi , Toshihiro Nomoto , Kouichi Takano , Tomohiro Saito , Shoji Tanaka , Fumiaki Minematsu , Akinori Hashimoto , Shigeyuki Itoh , Hajime Matsumura , Hisakazu Katoh , Masaru Takechi
IPC分类号： H04N550
CPC分类号： H03J7/02 , H04L27/22 , H04L2027/0057 , H04N5/4401 , H04N5/455 , H04N5/50
摘要： Stabilized carrier recovery is achieved even at the time of a low C/N ratio by measuring the phase of a signal and controlling VCO or NCO (Numerical Controlled Oscillator) using only a period having few constellation points. At this time, false lock phenomenon is avoided as follows. That is, relatively short SYNC modulated by an already-known pattern is entered into a modulation wave, VCO or NCO oscillation frequency is swept in a wide range and sweep is stopped at a frequency in which the SYNC can be received, thereby carrying out coarse control AFC. Further, a period having long to some extent, having few constellation points is provided in the modulation wave and then, a difference between the frequency of a received modulated signal and a local oscillation signal of VCO or NCO is obtained in this period. This frequency difference is analyzed according to the phase differential function method, self-correlation function method or count method, and the VCO or NCO is controlled based on this result of analysis.
摘要翻译：即使在C / N比较低的时候，通过测量信号的相位并且仅使用具有少量星座点的时段来控制VCO或NCO（数控振荡器），也能实现稳定的载波恢复。此时，如下避免假锁现象。也就是说，通过已知的模式调制的相对较短的SYNC被输入到调制波中，VCO或NCO振荡频率在宽范围内被扫描，并且在可以接收SYNC的频率上停止扫描，从而执行粗略控制AFC。此外，在调制波中提供具有很少的星座点的长时间段，然后在该周期中获得接收到的调制信号的频率与VCO或NCO的本地振荡信号之间的差。根据相位差函数法，自相关函数法或计数法对该频差进行分析，并根据分析结果对VCO或NCO进行控制。

3. 发明授权

US06512759B1 Transmitter and receiver 有权
标题翻译：发射机和接收机
公开(公告)号：US06512759B1
公开(公告)日：2003-01-28
申请号：US09367190
申请日：1999-08-04
申请人： Akinori Hashimoto , Hajime Matsumura , Junji Kumada , Hisakazu Katoh
发明人： Akinori Hashimoto , Hajime Matsumura , Junji Kumada , Hisakazu Katoh
IPC分类号： H04Q732
CPC分类号： H04L1/0071 , H03M13/15 , H03M13/271 , H04L1/0041 , H04L1/007 , H04L1/0075
摘要： An interleave frame is formed by combining slots corresponding to the same slot number in each frame when interleave process is performed in a super frame, and the data are read out along row or column direction (i.e. readout direction) and the data are written along the direction opposite to the readout direction in the same memory.
摘要翻译：当在超帧中进行交织处理时，通过组合对应于每帧中相同时隙号的时隙来形成交织帧，并且沿着行或列方向（即，读出方向）读出数据，并且沿着方向与相同存储器中的读出方向相反。

4. 发明授权

US06813321B1 Digital demodulator 有权
标题翻译：数字解调器
公开(公告)号：US06813321B1
公开(公告)日：2004-11-02
申请号：US09582229
申请日：2000-07-21
申请人： Hisakazu Katoh , Akinori Hashimoto , Yuichi Iwadate , Kazuhiko Shibuya , Fumiaki Minematsu , Shigeyuki Itoh , Tomohiro Saito , Kenichi Shiraishi , Akihiro Horii , Shoji Matsuda , Soichi Shinjo
发明人： Hisakazu Katoh , Akinori Hashimoto , Yuichi Iwadate , Kazuhiko Shibuya , Fumiaki Minematsu , Shigeyuki Itoh , Tomohiro Saito , Kenichi Shiraishi , Akihiro Horii , Shoji Matsuda , Soichi Shinjo
IPC分类号： H03D322
CPC分类号： H04L27/2273 , H04L7/042 , H04L27/0014 , H04L2027/0057 , H04L2027/0067 , H04L2027/0077 , H04L2027/0095
摘要： A digital demodulator which will need no absolute phasing circuit is provided. A known-pattern BPSK signal generating circuit 6 generates the same known-pattern BPSK signal as a known-pattern BPSK signal in a received digital modulated wave in synchronism with the known-pattern BPSK signal in the received digital modulated wave, a carrier-reproducing phase error detecting circuit 7 has a phase error table where one of reference phases in a signal point position of a demodulation baseband signal is made a convergence point, a phase error voltage corresponding to a phase error between a phase determined from the signal point position of the demodulation baseband signals and a phase convergence point is sent out, by enable-controlling a carrier-reproducing loop filter 8 according to the known-pattern BPSK signal outputted from the known-pattern BPSK signal generating circuit 6, the phase error voltage is smoothed, and carrier reproduction is performed while controlling the frequency of a reproduced carrier according to the smoothed output so that the phase in the signal point position coincides with the phase convergence point.
摘要翻译：提供了不需要绝对定相电路的数字解调器。已知模式BPSK信号发生电路6与接收的数字调制波中的已知模式BPSK信号同步地产生与接收的数字调制波中已知模式BPSK信号相同的已知模式BPSK信号，载波再现相位误差检测电路7具有相位误差表，其中解调基带信号的信号点位置中的参考相位之一成为会聚点，相位误差电压对应于从信号点位置确定的相位之间的相位误差通过根据从已知模式BPSK信号发生电路6输出的已知模式BPSK信号启用控制载波再现环路滤波器8，发送解调基带信号和相位收敛点，平滑相位误差电压并且在根据平滑输出控制再现载波的频率的同时执行载波再现，使得si中的相位点位置与相位收敛点一致。

5. 发明授权

US06788654B1 Digital data receiver 有权
标题翻译：数字数据接收机
公开(公告)号：US06788654B1
公开(公告)日：2004-09-07
申请号：US09402700
申请日：1999-12-15
申请人： Akinori Hashimoto , Hisakazu Katoh , Hiroyuki Hamada , Kyoichi Saito , Tomohiro Saito , Fumiaki Minematsu
发明人： Akinori Hashimoto , Hisakazu Katoh , Hiroyuki Hamada , Kyoichi Saito , Tomohiro Saito , Fumiaki Minematsu
IPC分类号： H04B7212
CPC分类号： H04H60/12 , H04L1/0045 , H04L1/0059 , H04L1/007 , H04L1/203 , H04L1/206 , H04N19/89 , H04N21/4382
摘要： After receiving a time division multiplex signal including a plurality of digital data signals transmitted in accordance with different transmission schemes, the received time division multiplex signal is demodulated by a demodulation circuit, and it is judged by a detection circuit whether each of the demodulated digital data signals is received correctly or not. When it is detected that a digital data signal transmitted by any one of the plurality of different transmission schemes is not received correctly, the relevant digital data signal is replaced by a suitable signal such as a null packet signal which does not affect a correct reception of the remaining digital data signals transmitted by the remaining transmission schemes to form a corrected time division multiplexed signal even if a digital data signal is not received correctly.
摘要翻译：在接收到包括根据不同传输方案发送的多个数字数据信号的时分复用信号之后，接收的时分多路复用信号由解调电路解调，并且由检测电路判断每个解调数字数据正确接收信号。当检测到由多个不同传输方案中的任何一个发送的数字数据信号没有被正确地接收时，相关的数字数据信号被诸如空分组信号之类的合适的信号替代，该信号不影响正确接收剩余的数字数据信号由剩余的传输方案发送，以便即使数字数据信号没有被正确地接收，也形成校正的时分复用信号。

6. 发明授权

US06700940B1 Carrier reproduction circuit 有权
标题翻译：载波再现电路
公开(公告)号：US06700940B1
公开(公告)日：2004-03-02
申请号：US09581212
申请日：2000-08-15
申请人： Hisakazu Katoh , Akinori Hashimoto , Tomohiro Saito , Fumiaki Minematsu , Kenichi Shiraishi , Akihiro Horii , Shoji Matsuda , Soichi Shinjo
发明人： Hisakazu Katoh , Akinori Hashimoto , Tomohiro Saito , Fumiaki Minematsu , Kenichi Shiraishi , Akihiro Horii , Shoji Matsuda , Soichi Shinjo
IPC分类号： H04B1700
CPC分类号： H04L27/2273
摘要： A carrier reproduction circuit which can perform stable carrier reproduction even when reception takes place with low C/N values is provided. The reception phase of the demodulated known-pattern reception signal is detected with a frame synchronizing timing circuit (4), and based on the detected reception phase, either the phase difference table of absolute phase having one convergence point or the phase difference table of the phase rotated from the absolute phase by 180°, which are included in a carrier reproduction phase difference detecting circuit (8), is selected, and from the selected phase difference table the output based on the phase difference between the phase obtained from the signal point position of the reception signal and the phase convergence point is obtained, and thus carrier reproduction is implemented by undergoing the reproduced carrier frequency control via an AFC circuit (10) so that the phase obtained from the signal point position coincides with the phase convergence point.
摘要翻译：提供即使在以低C / N值进行接收的情况下也能够执行稳定的载波再现的载波再现电路。利用帧同步定时电路（4）检测解调的已知模式接收信号的接收相位，并且基于检测到的接收相位，具有一个收敛点的绝对相位的相位差表或者具有一个收敛点的相位差表选择包含在载波再现相位差检测电路（8）中的从绝对相位旋转180°的相位，并且从所选择的相位差表中选择基于从信号点获得的相位之间的相位差的输出获得接收信号和相位收敛点的位置，从而通过经由AFC电路（10）经历再现的载波频率控制来实现载波再现，使得从信号点位置获得的相位与相位收敛点一致。

7. 发明授权

US06639951B1 Digital demodulator 有权
标题翻译：数字解调器
公开(公告)号：US06639951B1
公开(公告)日：2003-10-28
申请号：US09554689
申请日：2000-05-18
申请人： Hisakazu Katoh , Akinori Hashimoto , Tomohiro Saito , Fumiaki Minematsu , Kenichi Shiraishi , Akihiro Horii , Shoji Matsuda , Soichi Shinjo
发明人： Hisakazu Katoh , Akinori Hashimoto , Tomohiro Saito , Fumiaki Minematsu , Kenichi Shiraishi , Akihiro Horii , Shoji Matsuda , Soichi Shinjo
IPC分类号： H04L2714
CPC分类号： H04L27/2332 , H04L7/04 , H04L2027/003 , H04L2027/0057 , H04L2027/0095
摘要： A digital demodulator that eliminates the need for an absolute phase circuit is provided. In a digital demodulator for a digital broadcasting receiver that receives digital time-division multiplexed signals of different types of modulation, the demodulated baseband signal is selectively inverted by an inverter (7) according to an inversion command signal “0” or “1” that is output from an inversion decision circuit (6) depending on a BPSK signal of a known pattern. A phase error detector (8) for carrier reproduction determines the phase error voltage based on the phase difference between the absolute phase and the phase of the signal point of the demodulated baseband signal output from the inverter (7). The phase error voltage is passed through a carrier filter (9), including a low-pass filter, to control the carrier frequency so that carrier reproduction can be carried out with the phase at the signal point being coincident with the point of phase convergence.
摘要翻译：提供了一种无需绝对相位电路的数字解调器。在用于数字广播接收机的数字解调器中，接收不同类型调制的数字时分多路复用信号，根据反相器（7）根据反相指令信号“0”或“1”选择性地将解调的基带信号反相，根据已知图案的BPSK信号从反转判定电路（6）输出。用于载波再现的相位误差检测器（8）基于从逆变器（7）输出的解调的基带信号的信号点的绝对相位和相位之间的相位差来确定相位误差电压。相位误差电压通过包括低通滤波器的载波滤波器（9），以控制载波频率，使得载波再现可以在信号点处的相位与相位收敛点一致。

8. 发明授权

US06526107B1 Synchronization acquiring circuit 失效
标题翻译：同步采集电路
公开(公告)号：US06526107B1
公开(公告)日：2003-02-25
申请号：US09530962
申请日：2000-07-12
申请人： Hisakazu Katoh , Akinori Hashimoto , Kenichi Shiraishi , Akihiro Horii
发明人： Hisakazu Katoh , Akinori Hashimoto , Kenichi Shiraishi , Akihiro Horii
IPC分类号： H04L700
CPC分类号： H04J3/0605 , H04J3/0608 , H04L7/0083 , H04L27/22
摘要： There is provided a synchronization acquiring circuit for stably acquiring frame synchronization without pseudo-synchronization lock when the frame synchronization is acquired in reception at the time of a low C/N. The synchronization pattern of a received frame is detected by a frame synchronization detecting circuit 2. The bits of the synchronization pattern of the received frame are compared with those of a frame synchronization pattern on the transmitting side by a frame synchronizing circuit 5 to obtain the number of coincided bits. The frame synchronization is regarded as detected when the obtained number of bits of each frame is equal to or larger than the correlation detection value.
摘要翻译：提供了一种在低C / N时接收帧同步时稳定地获取帧同步而不进行伪同步锁定的同步获取电路。接收帧的同步模式由帧同步检测电路2检测。通过帧同步电路5将接收帧的同步模式的比特与发送侧的帧同步模式的位进行比较，以获得数字一致的位。当获得的每帧的比特数等于或大于相关检测值时，认为帧同步被检测。

9. 发明授权

US06748037B1 Digital broadcasting receiver 有权
标题翻译：数字广播接收机
公开(公告)号：US06748037B1
公开(公告)日：2004-06-08
申请号：US09554690
申请日：2000-05-18
申请人： Hisakazu Katoh , Akinori Hashimoto , Kenichi Shiraishi , Akihiro Horii , Shoji Matuda
发明人： Hisakazu Katoh , Akinori Hashimoto , Kenichi Shiraishi , Akihiro Horii , Shoji Matuda
IPC分类号： H04L2706
CPC分类号： H04L27/2273 , H04L2027/0057 , H04L2027/0067 , H04L2027/0077 , H04L2027/0095
摘要： A digital broadcasting receiver is provided which can reproduce a carrier quickly and capture a desired signal at high speed. A carrier reproduction phase error detection circuit (6) detects a phase error voltage in accordance with a demodulation output obtained by demodulating a demodulated wave of a modulated wave during a predetermined section in a header section. A peak number calculation circuit (92) calculates an error frequency between a desired reception frequency and a reproduction carrier frequency in accordance with the phase error voltage. A differential coefficient calculation circuit (94) calculates the polarity of the error frequency. A step frequency control circuit (96) converts the calculated error frequency having the calculated polarity into a step frequency width for automatic frequency control. The reproduction carrier frequency is scanned at the converted step frequency width until a frame sync is established after the frame sync is detected. It is therefore possible to reproduce the carrier quickly and capture the desired signal at high speed.
摘要翻译：提供一种数字广播接收机，其可以快速地再现载波并以高速捕获期望的信号。载波再现相位误差检测电路（6）根据在标题部分中的预定部分期间解调调制波的解调波得到的解调输出来检测相位误差电压。峰值计算电路（92）根据相位误差电压计算期望的接收频率和再现载波频率之间的误差频率。差分系数计算电路（94）计算误差频率的极性。步进频率控制电路（96）将计算出的极性的计算误差频率转换为用于自动频率控制的步进频率宽度。以转换的步进频率宽度扫描再现载波频率，直到在检测到帧同步之后建立帧同步。因此，可以快速地再现载体并以高速捕获期望的信号。

10. 发明授权

US06678336B1 Hierarchical transmission digital demodulator 有权
标题翻译：分层传输数字解调器
公开(公告)号：US06678336B1
公开(公告)日：2004-01-13
申请号：US09554669
申请日：2000-08-09
申请人： Hisakazu Katoh , Akinori Hashimoto , Kenichi Shiraishi , Akihiro Horii , Shoji Matsuda
发明人： Hisakazu Katoh , Akinori Hashimoto , Kenichi Shiraishi , Akihiro Horii , Shoji Matsuda
IPC分类号： H04L2706
CPC分类号： H04L27/2332 , H04L2027/003 , H04L2027/0057 , H04L2027/0081 , H04L2027/0095
摘要： A hierarchical transmission digital demodulator capable of stable sync capture and stable demodulation through setting of a demodulation operation in accordance with a reception C/N value. A CNR measuring circuit receives a demodulation output from an arithmetic circuit and measures a reception C/N value. During a period until sync is captured, a carrier is reproduced in accordance with the demodulation output that a modulated wave in a header section and a modulated wave of burst symbol signal. After sync is captured, at an intermediate C/N value the carrier is reproduced in accordance with the demodulation output of the header section, burst symbol signal and QPSK signal and in accordance with output from a logical gate circuit, and at high and low C/N values the carrier is reproduced by setting high a carrier reproduction loop gain of a gain control circuit in accordance with a signal from the logical gate circuit.
摘要翻译：一种能够通过根据接收C / N值设置解调操作来稳定同步捕获和稳定解调的分级发送数字解调器。 CNR测量电路从运算电路接收解调输出并测量接收C / N值。在捕获同步之前的一段时间内，根据解调输出再现载波，以便在报头部分中的调制波和突发符号信号的调制波。在捕获同步之后，以中间C / N值，根据标题部分的解调输出，突发符号信号和QPSK信号，并根据逻辑门电路的输出，以及在高和低C / N值通过根据来自逻辑门电路的信号设置增益控制电路的载波再生环路增益来重放载波。

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