专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06501132B1 Transistor with variable channel width 有权
标题翻译：具有可变通道宽度的晶体管
公开(公告)号：US06501132B1
公开(公告)日：2002-12-31
申请号：US09468859
申请日：1999-12-21
申请人： Hisashi Ohtani
发明人： Hisashi Ohtani
IPC分类号： H01L2901
CPC分类号： H01L29/66757 , H01L29/42384 , H01L29/78675
摘要： A gate insulating film 103 is oxidized by a thermal oxidation method using a gate electrode 104 as a mask. At this time, the thickness of the gate insulating film 103 becomes thicker so that the portions indicated by 106 and 107 are obtained. The thickness of an active layer becomes thin at an end 112 of a channel, so that the distance from the gate electrode becomes long by the thickness. Then the strength of an electric field between a source and drain is relaxed by this portion. In this way, a thin film transistor having improved withstand voltage characteristics and leak current characteristics is obtained.
摘要翻译：栅极绝缘膜103通过使用栅电极104作为掩模的热氧化法氧化。此时，栅极绝缘膜103的厚度变厚，得到106,107所示的部分。有源层的厚度在沟道的端部112处变薄，使得与栅电极的距离变长为厚度。那么这个部分放宽源极和漏极之间的电场的强度。以这种方式，获得具有改善的耐压特性和漏电流特性的薄膜晶体管。

2. 发明授权

US06326642B1 Electric device, matrix device, electro-optical display device, and semiconductor memory having thin-film transistors 失效
标题翻译：电气装置，矩阵装置，电光显示装置和具有薄膜晶体管的半导体存储器
公开(公告)号：US06326642B1
公开(公告)日：2001-12-04
申请号：US09375352
申请日：1999-08-17
申请人： Shunpei Yamazaki , Yasuhiko Takemura
发明人： Shunpei Yamazaki , Yasuhiko Takemura
IPC分类号： H01L2901
CPC分类号： H01L27/1214 , G02F1/13454 , G02F2001/136245 , H01L27/10873 , H01L29/78603 , H01L29/78609 , H01L29/78666 , H01L29/78675 , H01L29/78696
摘要： A circuit adapted to dynamically activate an electro-optical display device is constructed from a thin-film gate-insulated semiconductor device. This device comprises PMOS TFTs producing only a small amount of leakage current. Besides the dynamic circuit, a CMOS circuit comprising both NMOS and PMOS thin-film transistors is constructed to drive the dynamic circuit.
摘要翻译：适于动态激活电光显示装置的电路由薄膜栅极绝缘半导体器件构成。该器件包括仅产生少量漏电流的PMOS TFT。除了动态电路之外，构造包括NMOS和PMOS薄膜晶体管的CMOS电路以驱动动态电路。

3. 发明授权

US06765265B2 System and method for manufacturing a thin film transistor 失效
标题翻译：用于制造薄膜晶体管的系统和方法
公开(公告)号：US06765265B2
公开(公告)日：2004-07-20
申请号：US09936040
申请日：2001-12-11
申请人： Ichio Yudasaka , Mitsutoshi Miyasaka , Piero Migliorato
发明人： Ichio Yudasaka , Mitsutoshi Miyasaka , Piero Migliorato
IPC分类号： H01L2901
CPC分类号： H01L29/78696 , H01L29/42384 , H01L29/78612
摘要： The present invention provides a thin film transistor (TET) and its production method which enable the stabilizing of saturation current and improving reliability by improving the film quality of the channel region. The TFT includes a channel region towering over a gate electrode through a gate insulation film, a source region connecting to the channel region and a drain region connecting to the channel region on an opposite side of the source region are formed on the polycrystal semiconductor film on which island-like patterning is performed. An indented section is formed on a surface of the channel region, and the section corresponding to the indented section becomes a recombination center which captures the small-number carrier (holes) because the degree of the crystallization is low in the section corresponding to the indented section due to shift from the optimum conditions at the time of laser annealing of the semiconductor.
摘要翻译：本发明提供一种薄膜晶体管（TET）及其制造方法，其能够通过提高沟道区域的膜质量来稳定饱和电流并提高可靠性。 TFT包括通过栅极绝缘膜在栅电极上耸立的沟道区，在多晶半导体膜上形成连接到沟道区的源极区和连接到源极区相对侧的沟道区的漏极区，进行岛状图案化。在通道区域的表面上形成凹陷部分，并且与缩进部分对应的部分成为俘获小数载体（空穴）的复合中心，因为在对应于缩进的部分中结晶度低由于半导体的激光退火时的最佳条件的变化。

4. 发明授权

US06492684B2 Silicon-on-insulator chip having an isolation barrier for reliability 有权
公开(公告)号：US06492684B2
公开(公告)日：2002-12-10
申请号：US09878681
申请日：2001-06-11
申请人： Ronald J. Bolam , Subhash B. Kulkarni , Dominic J. Schepis
发明人： Ronald J. Bolam , Subhash B. Kulkarni , Dominic J. Schepis
IPC分类号： H01L2901
CPC分类号： H01L29/66772 , H01L21/743 , H01L21/76264 , H01L21/76283 , H01L27/1203 , H01L29/78636 , H01L29/78648
摘要： An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact—which define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.

5. 发明授权

US06278157B1 Method and apparatus for elimination of parasitic bipolar action in logic circuits including complementary oxide semiconductor (CMOS) silicon on insulator (SOI) elements 失效
标题翻译：用于消除包括互补氧化物半导体（CMOS）绝缘体上硅（SOI）元件的逻辑电路中的寄生双极性作用的方法和装置
公开(公告)号：US06278157B1
公开(公告)日：2001-08-21
申请号：US09240991
申请日：1999-01-29
申请人： Jeff Van Tran , Salvatore N. Storino
发明人： Jeff Van Tran , Salvatore N. Storino
IPC分类号： H01L2901
CPC分类号： H03K19/00361 , H01L29/78612
摘要： The present invention is an apparatus and method to overcome the unwanted effects of parasitic bipolar discharge in silicon-on-insulator (SOI) field effect transistors (FET) by expanding a stack SOI MOS devices arranged to provide a predetermined logic function. The SOI MOS devices are arranged so as to eliminate electrical connections between certain intermediate nodes of the dynamic logic circuit. Accordingly, eliminating any parasitic bipolar current leakage paths associated with such electrical connections between certain intermediate nodes of said stacked SOI MOS devices of said dynamic circuit.
摘要翻译：本发明是通过扩展布置成提供预定逻辑功能的堆叠SOI MOS器件来克服绝缘体上硅（SOI）场效应晶体管（FET）中寄生双极放电的不希望的影响的装置和方法。 SOI MOS器件被布置成消除动态逻辑电路的某些中间节点之间的电连接。因此，消除与所述动态电路的所述堆叠的SOI MOS器件的某些中间节点之间的这种电连接相关联的任何寄生双极性电流泄漏路径。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式