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1. 发明授权

US06492684B2 Silicon-on-insulator chip having an isolation barrier for reliability 有权
公开(公告)号：US06492684B2
公开(公告)日：2002-12-10
申请号：US09878681
申请日：2001-06-11
申请人： Ronald J. Bolam , Subhash B. Kulkarni , Dominic J. Schepis
发明人： Ronald J. Bolam , Subhash B. Kulkarni , Dominic J. Schepis
IPC分类号： H01L2901
CPC分类号： H01L29/66772 , H01L21/743 , H01L21/76264 , H01L21/76283 , H01L27/1203 , H01L29/78636 , H01L29/78648
摘要： An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact—which define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.

2. 发明授权

US06281095B1 Process of manufacturing silicon-on-insulator chip having an isolation barrier for reliability 有权
标题翻译：制造具有隔离屏障的绝缘体上硅芯片的可靠性的工艺
公开(公告)号：US06281095B1
公开(公告)日：2001-08-28
申请号：US09148918
申请日：1998-09-04
申请人： Ronald J. Bolam , Subhash B. Kulkarni , Dominic J. Schepis
发明人： Ronald J. Bolam , Subhash B. Kulkarni , Dominic J. Schepis
IPC分类号： H01L21301
CPC分类号： H01L29/66772 , H01L21/743 , H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/78636 , H01L29/78648
摘要： An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact—which define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.
摘要翻译：具有隔离屏障的SOI芯片。 SOI芯片包括衬底，沉积在衬底上的氧化物层和沉积在氧化物层上的硅层。栅极沉积在硅层上方。第一金属触点沉积在栅极上方以形成与栅极的电接触。沉积第二和第三金属触点以形成与硅层的电接触。隔离屏障延伸穿过硅层和氧化物层，并部分地延伸到衬底中，以阻挡隔离屏障之外的氧化物层中的杂质扩散到隔离屏障内部的氧化物层中。隔离屏障围绕栅极，第一金属触点，第二金属触点和第三金属触点，其限定隔离屏障内部的有源芯片区域。还公开了制造SOI芯片的方法。

3. 发明授权

US06563173B2 Silicon-on-insulator chip having an isolation barrier for reliability 有权
公开(公告)号：US06563173B2
公开(公告)日：2003-05-13
申请号：US09859146
申请日：2001-05-16
申请人： Ronald J. Bolam , Subhash B. Kulkarni , Dominic J. Schepis
发明人： Ronald J. Bolam , Subhash B. Kulkarni , Dominic J. Schepis
IPC分类号： H01L2900
CPC分类号： H01L29/66772 , H01L21/743 , H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/78636 , H01L29/78648
摘要： An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact—which define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.

4. 发明授权

US6133610A Silicon-on-insulator chip having an isolation barrier for reliability and process of manufacture 失效
标题翻译：绝缘体上硅芯片具有可靠性和制造工艺的隔离屏障
公开(公告)号：US6133610A
公开(公告)日：2000-10-17
申请号：US9445
申请日：1998-01-20
申请人： Ronald J. Bolam , Subhash B. Kulkarni , Dominic J. Schepis
发明人： Ronald J. Bolam , Subhash B. Kulkarni , Dominic J. Schepis
IPC分类号： H01L21/336 , H01L21/74 , H01L21/762 , H01L21/84 , H01L27/12 , H01L29/786 , H01L29/00
CPC分类号： H01L29/66772 , H01L21/743 , H01L21/76264 , H01L21/84 , H01L27/1203 , H01L29/78636 , H01L29/78648 , H01L21/76283
摘要： An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact--which define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.
摘要翻译：具有隔离屏障的SOI芯片。 SOI芯片包括衬底，沉积在衬底上的氧化物层和沉积在氧化物层上的硅层。栅极沉积在硅层上方。第一金属触点沉积在栅极上方以形成与栅极的电接触。沉积第二和第三金属触点以形成与硅层的电接触。隔离屏障延伸穿过硅层和氧化物层，并部分地延伸到衬底中，以阻挡隔离屏障之外的氧化物层中的杂质扩散到隔离屏障内部的氧化物层中。隔离屏障围绕栅极，第一金属触点，第二金属触点和第三金属触点，其限定隔离屏障内部的有源芯片区域。还公开了制造SOI芯片的方法。

5. 再颁专利

USRE40339E1 Silicon-on-insulator chip having an isolation barrier for reliability 有权
标题翻译：绝缘体上硅芯片具有可靠性的隔离屏障
公开(公告)号：USRE40339E1
公开(公告)日：2008-05-27
申请号：US11004791
申请日：2004-12-03
申请人： Ronald J. Bolam , Subhash B. Kulkami , Dominic J. Schepis
发明人： Ronald J. Bolam , Subhash B. Kulkami , Dominic J. Schepis
IPC分类号： H01L29/01
摘要： An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact—which define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.
摘要翻译：具有隔离屏障的SOI芯片。 SOI芯片包括衬底，沉积在衬底上的氧化物层和沉积在氧化物层上的硅层。栅极沉积在硅层上方。第一金属触点沉积在栅极上方以形成与栅极的电接触。沉积第二和第三金属触点以形成与硅层的电接触。隔离屏障延伸穿过硅层和氧化物层，并部分地延伸到衬底中，以阻挡隔离屏障之外的氧化物层中的杂质扩散到隔离屏障内部的氧化物层中。隔离屏障围绕栅极，第一金属触点，第二金属触点和第三金属触点，其限定隔离屏障内部的有源芯片区域。还公开了制造SOI芯片的方法。

6. 发明授权

US08685845B2 Epitaxial growth of silicon doped with carbon and phosphorus using hydrogen carrier gas 有权
标题翻译：使用氢气载气使碳和磷掺杂的硅的外延生长
公开(公告)号：US08685845B2
公开(公告)日：2014-04-01
申请号：US12860236
申请日：2010-08-20
申请人： Abhishek Dube , Ashima B. Chakravarti , Jinghong H. Li , Rainer Loesing , Dominic J. Schepis
发明人： Abhishek Dube , Ashima B. Chakravarti , Jinghong H. Li , Rainer Loesing , Dominic J. Schepis
IPC分类号： H01L21/20
CPC分类号： H01L21/0262 , H01L21/0237 , H01L21/02529 , H01L21/02576 , H01L21/02587 , H01L21/02636 , H01L29/045 , H01L29/6656 , H01L29/78 , H01L29/7848
摘要： A method for depositing epitaxial films of silicon carbon (Si:C). In one embodiment, the method includes depositing an n-type doped silicon carbon (Si:C) semiconductor material on a semiconductor deposition surface using a deposition gas precursor composed of a silane containing gas precursor, a carbon containing gas precursor, and an n-type gas dopant source. The deposition gas precursor is introduced to the semiconductor deposition surface with a hydrogen (H2) carrier gas. The method for depositing epitaxial films may include an etch reaction provided by hydrogen chloride (HCl) gas etchant and a hydrogen (H2) carrier gas.
摘要翻译：一种用于沉积硅碳外延膜（Si：C）的方法。在一个实施例中，该方法包括：使用由含硅烷的气体前体，含碳气体前体和正极材料构成的沉积气体前体，在半导体沉积表面上沉积n型掺杂硅碳（Si：C）型气体掺杂剂源。沉积气体前体用氢（H 2）载气引入半导体沉积表面。沉积外延膜的方法可以包括由氯化氢（HCl）气体蚀刻剂和氢（H 2）载气提供的蚀刻反应。

7. 发明授权

US08652925B2 Method of fabricating isolated capacitors and structure thereof 有权
标题翻译：隔离电容器的制造方法及其结构
公开(公告)号：US08652925B2
公开(公告)日：2014-02-18
申请号：US12838515
申请日：2010-07-19
申请人： Oh-Jung Kwon , Junedong Lee , Paul C. Parries , Dominic J. Schepis
发明人： Oh-Jung Kwon , Junedong Lee , Paul C. Parries , Dominic J. Schepis
IPC分类号： H01L21/20
CPC分类号： H01L21/2007 , G06F17/5068 , H01L21/76224 , H01L21/7624 , H01L21/76251 , H01L21/76283 , H01L21/84 , H01L27/0207 , H01L27/10829 , H01L27/10861 , H01L27/1087 , H01L27/1203 , H01L28/40 , H01L28/90 , H01L29/66181
摘要： A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.
摘要翻译：提供了用于制造隔离电容器的结构和方法。该方法包括同时形成多个深沟槽和围绕多个深沟槽的一组或多个阵列的一个或多个隔离沟槽，其通过SOI和掺杂多晶硅层形成到下面的绝缘体层。该方法还包括用绝缘体材料衬套多个深沟槽和一个或多个隔离沟槽。该方法还包括在绝缘体材料上用导电材料填充多个深沟槽和一个或多个隔离沟槽。深沟槽形成深沟槽电容器，并且一个或多个隔离沟槽形成一个或多个隔离板，其将深沟槽电容器的至少一组或阵列与另一组或深沟槽电容器阵列隔离开来。

8. 发明申请

US20120205749A1 SILICON GERMANIUM FILM FORMATION METHOD AND STRUCTURE 有权
标题翻译：硅锗膜形成方法和结构
公开(公告)号：US20120205749A1
公开(公告)日：2012-08-16
申请号：US13025474
申请日：2011-02-11
申请人： Ashima B. Chakravarti , Abhishek Dube , Dominic J. Schepis
发明人： Ashima B. Chakravarti , Abhishek Dube , Dominic J. Schepis
IPC分类号： H01L27/092 , H01L21/762 , H01L21/8238
CPC分类号： H01L21/823814 , H01L21/76224 , H01L21/823807
摘要： Epitaxial deposition of silicon germanium in a semiconductor device is achieved without using masks. Nucleation delays induced by interactions with dopants present before deposition of the silicon germanium are used to determine a period over which an exposed substrate surface may be subjected to epitaxial deposition to form a layer of SiGe on desired parts with substantially no deposition on other parts. Dopant concentration may be changed to achieve desired thicknesses within preferred deposition times. Resulting deposited SiGe is substantially devoid of growth edge effects.
摘要翻译：在不使用掩模的情况下实现硅锗在半导体器件中的外延沉积。使用在沉积硅锗之前与存在的掺杂剂的相互作用引起的成核延迟来确定暴露的衬底表面可以经历外延沉积以在所需部分上形成SiGe层的周期，而在其它部分上基本上没有沉积。可以改变掺杂剂浓度以在优选的沉积时间内实现期望的厚度。导致沉积的SiGe基本上没有生长边缘效应。

9. 发明授权

US08232186B2 Methods of integrating reverse eSiGe on NFET and SiGe channel on PFET, and related structure 失效
标题翻译：在PFET上对NFET和SiGe沟道反向eSiGe进行积分的方法及相关结构
公开(公告)号：US08232186B2
公开(公告)日：2012-07-31
申请号：US12128955
申请日：2008-05-29
申请人： Eric C. T. Harley , Judson R. Holt , Dominic J. Schepis , Michael D. Steigerwalt , Linda Black , Rick Carter
发明人： Eric C. T. Harley , Judson R. Holt , Dominic J. Schepis , Michael D. Steigerwalt , Linda Black , Rick Carter
IPC分类号： H01L21/20
CPC分类号： H01L21/823814 , H01L21/823807 , H01L29/1054 , H01L29/161 , H01L29/66636 , H01L29/7848
摘要： Methods of integrating reverse embedded silicon germanium (SiGe) on an NFET and SiGe channel on a PFET, and a related structure are disclosed. One method may include providing a substrate including an NFET area and a PFET area; performing a single epitaxial growth of a silicon germanium (SiGe) layer over the substrate; forming an NFET in the NFET area, the NFET including a SiGe plug in a channel thereof formed from the SiGe layer; and forming a PFET in the PFET area, the PFET including a SiGe channel formed from the SiGe layer. As an option, the SiGe layer over the PFET area may be thinned.
摘要翻译：公开了在NFET和PFET上的SiGe沟道上集成反向嵌入硅锗（SiGe）的方法和相关结构。一种方法可以包括提供包括NFET区域和PFET区域的衬底; 在衬底上执行硅锗（SiGe）层的单个外延生长; 在NFET区域中形成NFET，NFET在由SiGe层形成的沟道中包括SiGe插塞; 以及在PFET区中形成PFET，PFET包括由SiGe层形成的SiGe沟道。作为选择，PFET区域上的SiGe层可能变薄。

10. 发明申请

US20120181631A1 METHOD AND STRUCTURE FOR PMOS DEVICES WITH HIGH K METAL GATE INTEGRATION AND SiGe CHANNEL ENGINEERING 有权
标题翻译：具有高K金属栅组合和SiGe通道工程的PMOS器件的方法和结构
公开(公告)号：US20120181631A1
公开(公告)日：2012-07-19
申请号：US13431328
申请日：2012-03-27
申请人： Stephen W. Bedell , Ashima B. Chakravarti , Michael P. Chudzik , Judson R. Holt , Dominic J. Schepis
发明人： Stephen W. Bedell , Ashima B. Chakravarti , Michael P. Chudzik , Judson R. Holt , Dominic J. Schepis
IPC分类号： H01L29/78
CPC分类号： H01L29/1054 , H01L21/0237 , H01L21/02532 , H01L21/02612 , H01L29/6659 , H01L29/66651 , H01L29/7833
摘要： Various techniques for changing the workfunction of the substrate by using a SiGe channel which, in turn, changes the bandgap favorably for a p-type metal oxide semiconductor field effect transistors (pMOSFETs) are disclosed. In the various techniques, a SiGe film that includes a low doped SiGe region above a more highly doped SiGe region to allow the appropriate threshold voltage (Vt) for pMOSFET devices while preventing pitting, roughness and thinning of the SiGe film during subsequent cleans and processing is provided.
摘要翻译：公开了通过使用SiGe通道来改变衬底的功函数的各种技术，其又有利于改变p型金属氧化物半导体场效应晶体管（pMOSFET）的带隙。在各种技术中，SiGe膜包括在更高掺杂的SiGe区域上方的低掺杂SiGe区域，以允许pMOSFET器件的适当阈值电压（Vt），同时防止随后的清洁和处理期间SiGe膜的点蚀，粗糙度和变薄被提供。

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