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1. 发明专利

DE3884712T2 未知
公开(公告)号：DE3884712T2
公开(公告)日：1994-05-05
申请号：DE3884712
申请日：1988-07-27
申请人： SHARP KK
发明人： ASHIDA TSUTOMU , OKADA MIKIRO
IPC分类号： H01L21/8246 , H01L21/8247 , H01L27/112 , H01L29/78 , H01L27/10 , H01L21/82 , H01L29/62 , G11C17/00
摘要： A matrix type semiconductor memory device with higher complexity comprising: (a) a p-type (or n-type) semiconductor substrate, (b) a group of n-type (or p-type) semiconductor regions formed in the surface layer of the substrate in the from of strips arranged in parallel at a predetermined spacing, the semiconductor regions providing alternating source regions and drain regions and defining gate regions between the alternating regions, (c) a group of strips of first gate insulating film formed on the surface of the substrate at a predetermined spacing and intersecting the group of semiconductor regions, (d) a first gate electrode formed on each of the strips of first gate insulating film, (e) a group of portions of second gate insulating film formed on the exposed surface of the substrate between the strips of first gate insulating film, and (f) a second gate electrode formed on each of the portions of second gate insulating film and held out of contact with the first gate electrode, whereby a matrix of MIS semiconductor cells is formed, each of the cells being provided by the intersection of each gate region with one of the first and second electrodes, the gate regions of some of the cells being selectively doped with a p-type (or n-type) impurity substance at a higher concentration than the substrate.

2. 发明专利

DE3884712D1 未知
公开(公告)号：DE3884712D1
公开(公告)日：1993-11-11
申请号：DE3884712
申请日：1988-07-27
申请人： SHARP KK
发明人： ASHIDA TSUTOMU , OKADA MIKIRO
IPC分类号： H01L21/8246 , H01L21/8247 , H01L27/112 , H01L29/78 , H01L27/10 , H01L21/82 , H01L29/62 , G11C17/00
摘要： A matrix type semiconductor memory device with higher complexity comprising: (a) a p-type (or n-type) semiconductor substrate, (b) a group of n-type (or p-type) semiconductor regions formed in the surface layer of the substrate in the from of strips arranged in parallel at a predetermined spacing, the semiconductor regions providing alternating source regions and drain regions and defining gate regions between the alternating regions, (c) a group of strips of first gate insulating film formed on the surface of the substrate at a predetermined spacing and intersecting the group of semiconductor regions, (d) a first gate electrode formed on each of the strips of first gate insulating film, (e) a group of portions of second gate insulating film formed on the exposed surface of the substrate between the strips of first gate insulating film, and (f) a second gate electrode formed on each of the portions of second gate insulating film and held out of contact with the first gate electrode, whereby a matrix of MIS semiconductor cells is formed, each of the cells being provided by the intersection of each gate region with one of the first and second electrodes, the gate regions of some of the cells being selectively doped with a p-type (or n-type) impurity substance at a higher concentration than the substrate.

3. 发明专利

DE69120020T2 未知
公开(公告)号：DE69120020T2
公开(公告)日：1996-11-28
申请号：DE69120020
申请日：1991-10-22
申请人： SHARP KK
发明人： HOTTA YASUHIRO , OKADA MIKIRO
IPC分类号： H01L27/112 , G11C17/12 , H01L21/8246 , G11C7/00
摘要： A read-only memory includes columns of memory cell arrays, a plurality of banks formed by dividing each column of the memory cell arrays along the columns, sub-bit lines disposed between adjacent banks situated along the rows and connected to a transistor of each memory cell, and main-bit lines disposed between every two other columns of the memory cell arrays and extending along the columns, wherein the sub-bit lines are divided into sets of three sub-bit lines connected to a pair of adjacent banks situated along the rows, and one end of each center sub-bit line being connected to a first main-bit line through a first selector transistor, the first main-bit line passing through one side of the set to which the center bit-line belongs, and the other end of the sub-bit line being connected to a second main-bit line through a second selector transistor, the second main-bit line passing through the other side of the set to which the center sub-bit line belongs, the two outer sub-bit lines being directly connected to the main-bit lines adjacent to the set of banks, respectively.

4. 发明专利

DE69120020D1 未知
公开(公告)号：DE69120020D1
公开(公告)日：1996-07-11
申请号：DE69120020
申请日：1991-10-22
申请人： SHARP KK
发明人： HOTTA YASUHIRO , OKADA MIKIRO
IPC分类号： H01L27/112 , G11C17/12 , H01L21/8246 , G11C7/00
摘要： A read-only memory includes columns of memory cell arrays, a plurality of banks formed by dividing each column of the memory cell arrays along the columns, sub-bit lines disposed between adjacent banks situated along the rows and connected to a transistor of each memory cell, and main-bit lines disposed between every two other columns of the memory cell arrays and extending along the columns, wherein the sub-bit lines are divided into sets of three sub-bit lines connected to a pair of adjacent banks situated along the rows, and one end of each center sub-bit line being connected to a first main-bit line through a first selector transistor, the first main-bit line passing through one side of the set to which the center bit-line belongs, and the other end of the sub-bit line being connected to a second main-bit line through a second selector transistor, the second main-bit line passing through the other side of the set to which the center sub-bit line belongs, the two outer sub-bit lines being directly connected to the main-bit lines adjacent to the set of banks, respectively.

5. 发明专利

JPH0778466A SEMICONDUCTOR STORAGE 失效
公开(公告)号：JPH0778466A
公开(公告)日：1995-03-20
申请号：JP22473993
申请日：1993-09-09
申请人： SHARP KK
发明人： IMURA KOJI , OKADA MIKIRO , SHIMADA YUKIMINE
IPC分类号： G06F12/06 , G11C8/00 , G11C11/401
摘要： PURPOSE:To facilitate the optimization and the expansion of storage capacity by suppressing the output of the data when a signal showing a free address is received though the data stored in a specific memory are outputted according to an enable signal by a control circuit. CONSTITUTION:One among 2 +m pieces of memory cells provided in a memory cell array 3 is specified according to an address signal of n+1 bits by an address decoder 2, and the storage data are outputted by an output buffer circuit 4. By a free address detection circuit 5, a detection signal showing whether or not two bits among the received address signal of n+1 bits show the free address is outputted. Further, by the control circuit 6, an internal control signal the inverse of E outputting the data stored in the specified memory cell is generated according to the enable signal the inverse of CE. However, by the circuit 6, when the detection signal from the circuit 5 shows the free address, the signal the inverse of E suppressing the output of the data in spite of the signal the inverse of CE is outputted. Thus, the optimization and the expansion of the storage capacity are facilitated.

6. 发明专利

JPH10228776A SEMICONDUCTOR MEMORY AND DATA ACCESS METHOD 失效
公开(公告)号：JPH10228776A
公开(公告)日：1998-08-25
申请号：JP2814897
申请日：1997-02-12
申请人： SHARP KK
发明人： OKADA MIKIRO , KOMATSU KOJI
IPC分类号： G11C11/41 , G11C11/401 , G11C11/407 , H01L27/10
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory which can access the leading address at high speed without increasing a chip area and power consumption of a semiconductor memory, in a high speed access mode such as a page mode, a serial access mode, and the like. SOLUTION: A first memory cell array 1 and a second memory cell array 2 are arranged at both sides of a first row decoder 3 and a word line driving circuit 5.5 of a semiconductor memory. In the semiconductor memory, a word line WLiA of the first memory cell array 1 is made short by allotting a few memory cell to the first memory cell array 1.

7. 发明专利

JPH03205699A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH03205699A
公开(公告)日：1991-09-09
申请号：JP75390
申请日：1990-01-05
申请人： SHARP KK
发明人： HOTTA YASUHIRO , OKADA MIKIRO
IPC分类号： G11C29/00 , G06F11/16 , G11C17/00 , G11C17/12 , G11C17/18 , G11C29/04
摘要： PURPOSE:To accurately decide a semiconductor memory as a good or defective memory in a short test time by providing a switch circuit for test and a signal input means for test for input of a test signal which sets a row address decoder and a column address decoder to the selective set operation release state. CONSTITUTION:When a potential in the high level is given to a signal input terminal 18 for test at the time of test, an X decoder 15 and a Y decoder 16 are set to the operation stop state. If a defect exists in a gate oxide film or the like and a leak current flows to the ground from the defect part, a current I flows to transistors TRs Qio to Qik for memory cells from the signal input terminal 18 for test through NMOS TRs Q0 to Q(k+1) of a switch circuit 17 for test though the leak current is minute. This current I is confirmed to decide a mask ROM (read only memory) as a good or defective memory. Thus, it is accurately decide as a good or defective memory in a short test time.

8. 发明专利

JPH0311036B2 失效
公开(公告)号：JPH0311036B2
公开(公告)日：1991-02-15
申请号：JP14425283
申请日：1983-08-05
申请人： SHARP KK
发明人： KAMURO SETSUSHI , HIRANO TAKAAKI , OKADA MIKIRO
IPC分类号： G11C19/28 , G11C7/10 , G11C19/00 , H03M9/00

9. 发明专利

JPH04246855A SEMICONDUCTOR READ-ONLY MEMORY 失效
公开(公告)号：JPH04246855A
公开(公告)日：1992-09-02
申请号：JP1201091
申请日：1991-02-01
申请人： SHARP KK
发明人： HOTTA YASUHIRO , OKADA MIKIRO
IPC分类号： G11C17/12 , H01L21/8246 , H01L27/10 , H01L27/112
摘要： PURPOSE:To obtain a bank system semiconductor read only memory which can be made to operate stably at a high speed independently of the position of a memory cell selected at readout by a method wherein the other ends of a first and a second selection transistor are connected to different primary bit lines. CONSTITUTION:Primary bit lines MB extending in a row direction, a first selection transistor QO whose one end is connected to the end of one of two auxiliary bit lines SB adjacent to each other in a column direction, and a second selection transistor QE whose one end is connected to the end of the other auxiliary bit line SB are provided. The other ends of the first and the second selection transistor, QO and QE, are connected to the primary bit lines MB different from each other respectively. Therefore, a semiconductor read only memory is equal to an auxiliary bit line in resistance independently of the position (column) of a memory cell. Therefore, a data readout operation can be executed at a high speed as a whole.

10. 发明专利

JPH03214764A MANUFACTURE OF SEMICONDUCTOR CHIP 失效
公开(公告)号：JPH03214764A
公开(公告)日：1991-09-19
申请号：JP1114290
申请日：1990-01-19
申请人： SHARP KK
发明人： OKADA MIKIRO , NAKAHARA KAZUNORI
IPC分类号： H01L25/18 , H01L21/822 , H01L25/04 , H01L27/04
摘要： PURPOSE:To improve yield of a semiconductor chip by forming a plurality of functional blocks adjacent to a same wafer, sorting out the pass blocks from fail blocks, and dicing a plurality of pass and adjacent blocks as one chip. CONSTITUTION:Upper memory chip rows 20a having a plurality of upper memory chips A on a wafer 10 and lower memory chip rows 20b having a plurality of lower memory chips B are alternately formed. Accordingly, the laterally adjacent one of an arbitrary memory chip becomes a different memory chip. In this case, bonding pads 30 of the chip A to the chip B is formed only along upper and lower sides, and bonding pads are set at the same position in the same row. Then, the chips A, B are sorted to pass and fail ones. A plurality of pass and adjacent functional blocks are diced as one semiconductor chip 100. Thus, the yield of the chip 100 can be improved.

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