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1. 发明授权

US06709991B1 Method of fabricating semiconductor device with capacitor 失效
标题翻译：制造具有电容器的半导体器件的方法
公开(公告)号：US06709991B1
公开(公告)日：2004-03-23
申请号：US09084578
申请日：1998-05-26
申请人： Jun Kawahara , Shinobu Saito , Yukihiko Maejima , Yoshihiro Hayashi
发明人： Jun Kawahara , Shinobu Saito , Yukihiko Maejima , Yoshihiro Hayashi
IPC分类号： H01L21469
CPC分类号： H01L28/57 , H01L21/02164 , H01L21/0217 , H01L21/02216 , H01L21/02219 , H01L21/02271 , H01L21/31612 , H01L21/76801 , H01L21/76802
摘要： A fabrication method of a semiconductor device with a capacitor is provided, which prevents leakage current from increasing and dielectric breakdown resistance from decreasing during a CVD or dry etching process for forming an insulating film to cover the capacitor. In this method, a lower electrode of a capacitor is formed on a first insulating film. The first insulating film is typically formed on or over a semiconductor substrate. A dielectric film of the capacitor is formed on the lower electrode to be overlapped therewith. An upper electrode of the capacitor is formed on the dielectric film to be overlapped therewith. A second insulating film is formed to cover the capacitor by a thermal CVD process in an atmosphere containing no plasma at a substrate temperature in which hydrogen is prevented from being activated due to heat. A source material of the second insulating film has a property that no hydrogen is generated in the atmosphere through decomposition of the source material during the thermal CVD process.
摘要翻译：提供了具有电容器的半导体器件的制造方法，其防止了在用于形成绝缘膜以覆盖电容器的CVD或干蚀刻工艺期间泄漏电流增加和绝缘击穿电阻降低。在该方法中，在第一绝缘膜上形成电容器的下电极。第一绝缘膜通常形成在半导体衬底上或上方。电容器的电介质膜形成在下电极上以与其重叠。电容器的上电极形成在电介质膜上以与其重叠。形成第二绝缘膜，通过热CVD法在不防止由于热而被活化的基板温度下的不含等离子体的气氛中覆盖电容器。第二绝缘膜的源材料具有通过在热CVD工艺期间源材料分解而在大气中不产生氢的性质。

2. 发明授权

US6100201A Method of forming a semiconductor memory device 失效
标题翻译：形成半导体存储器件的方法
公开(公告)号：US6100201A
公开(公告)日：2000-08-08
申请号：US33912
申请日：1998-03-03
申请人： Yukihiko Maejima , Jun Kawahara , Shinobu Saitoh , Yoshihiro Hayashi
发明人： Yukihiko Maejima , Jun Kawahara , Shinobu Saitoh , Yoshihiro Hayashi
IPC分类号： H01L21/8247 , H01L21/02 , H01L21/302 , H01L21/3065 , H01L21/3105 , H01L21/311 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L27/04 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/788 , H01L29/792 , H01L21/461
CPC分类号： H01L28/55 , H01L21/3105 , H01L21/31122
摘要： A method of forming a capacitor by forming a dielectric layer over a bottom electrode layer, forming a top electrode layer over the dielectric layer to form laminations of the bottom electrode layer, the dielectric layer and the top electrode layer, and selectively etching the laminations to form a capacitor, the dielectric layer being etched by a reactive ion etching so that the dielectric layer of the capacitor receives no substantive damage in the etching process.
摘要翻译：一种通过在底部电极层上形成电介质层形成电容器的方法，在电介质层上形成顶部电极层以形成底部电极层，电介质层和顶部电极层的叠层，并选择性地蚀刻叠片至形成电容器，通过反应离子蚀刻蚀刻电介质层，使得电容器的电介质层在蚀刻工艺中不会受到实质的损坏。

3. 发明授权

US6004839A Semiconductor device with conductive plugs 失效
标题翻译：带导电插头的半导体器件
公开(公告)号：US6004839A
公开(公告)日：1999-12-21
申请号：US804112
申请日：1997-02-20
申请人： Yoshihiro Hayashi , Nobuhiro Tanabe , Tsuneo Takeuchi , Shinobu Saito
发明人： Yoshihiro Hayashi , Nobuhiro Tanabe , Tsuneo Takeuchi , Shinobu Saito
IPC分类号： H01L21/768 , H01L21/8242 , H01L21/8246 , H01L21/8238
CPC分类号： H01L27/11502 , H01L21/768 , H01L27/10844 , H01L27/10852 , H01L27/11507
摘要： In a method of manufacturing a semiconductor device, a CMOS section composed of an N-channel MOS transistor and a P-channel MOS transistor and a memory section composed of at least a transfer gate MOS transistor is formed on a substrate. A plurality of conductive plugs is formed to penetrate a laminate insulating film to the MOS transistors. The laminate insulating film is composed of a first insulating film and a second insulating film. A capacitor section is formed on the laminate insulating film and the capacitor section is composed of an upper electrode, a dielectric film and a lower electrode. A third insulating film is formed on the laminate insulating film and the capacitor section. A wiring pattern is formed on the third insulating film to partially penetrate the second insulating film connect to the plurality of conductive plugs. A wiring pattern may be disposed in the laminate insulating film to connect at least two of the plurality of conductive plugs.
摘要翻译：在制造半导体器件的方法中，在衬底上形成由N沟道MOS晶体管和P沟道MOS晶体管组成的CMOS部分和至少由传输门MOS晶体管组成的存储部分。形成多个导电插塞以穿透层压绝缘膜到MOS晶体管。层叠绝缘膜由第一绝缘膜和第二绝缘膜构成。在层叠绝缘膜上形成电容器部，电容部由上部电极，电介质膜和下部电极构成。在层压绝缘膜和电容器部分上形成第三绝缘膜。在第三绝缘膜上形成布线图案，以部分地穿透连接到多个导电插塞的第二绝缘膜。布线图案可以布置在层压绝缘膜中以连接多个导电插塞中的至少两个。

4. 发明授权

US08648441B2 Semiconductor device and method of manufacturing semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08648441B2
公开(公告)日：2014-02-11
申请号：US13106590
申请日：2011-05-12
申请人： Kenichiro Hijioka , Ippei Kume , Naoya Inoue , Hiroki Shirai , Jun Kawahara , Yoshihiro Hayashi
发明人： Kenichiro Hijioka , Ippei Kume , Naoya Inoue , Hiroki Shirai , Jun Kawahara , Yoshihiro Hayashi
IPC分类号： H01L21/02
CPC分类号： H01L27/10894 , H01L21/76811 , H01L23/5223 , H01L27/10852 , H01L28/75 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a substrate; a multi-layered interconnect formed on the substrate, and having a plurality of interconnect layers, each of which being configured by an interconnect and an insulating layer, stacked therein; a memory circuit formed in a memory circuit region on the substrate in a plan view, and having a peripheral circuit and at least one capacitor element embedded in the multi-layered interconnect; and a logic circuit formed in a logic circuit region on the substrate, wherein the capacitor element is configured by a lower electrode, a capacitor insulating film, an upper electrode, an embedded electrode and an upper interconnect; the top surface of the upper interconnect, and the top surface of the interconnect configuring the logic circuit formed in the same interconnect layer with the upper interconnect, are aligned to the same plane.
摘要翻译：半导体器件具有基板; 形成在所述基板上的多层互连，并且具有多个互连层，每个互连层由布置在其中的互连和绝缘层构成; 在平面图形成在基板上的存储器电路区域中的存储电路，并且具有外围电路和嵌入多层互连中的至少一个电容元件; 以及形成在所述基板上的逻辑电路区域中的逻辑电路，其中所述电容器元件由下电极，电容器绝缘膜，上电极，嵌入电极和上互连构成; 上互连的顶表面和构成与上互连的同一互连层中形成的逻辑电路的互连的顶表面与同一平面对准。

5. 发明授权

US08629529B2 Semiconductor device and its manufacturing method 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US08629529B2
公开(公告)日：2014-01-14
申请号：US12519706
申请日：2007-12-25
申请人： Naoya Inoue , Ippei Kume , Jun Kawahara , Yoshihiro Hayashi
发明人： Naoya Inoue , Ippei Kume , Jun Kawahara , Yoshihiro Hayashi
IPC分类号： H01L27/06
CPC分类号： H01L23/5228 , H01L23/5223 , H01L23/53238 , H01L27/0688 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device is produced by fabricating a capacitor element including a lower electrode, a capacitor insulating film, and an upper electrode, and a thin-film resistor element, in the same step. As the lower electrode of the capacitor element is lined with a lower layer wiring layer (Cu wiring), the lower electrode has extremely low resistance substantially. As such, even if the film thickness of the lower electrode becomes thinner, parasitic resistance does not increased. The resistor element is formed to have the same film thickness as that of the lower electrode of the capacitor element. Since the film thickness of the lower electrode is thin, it works as a resistor having high resistance. In the top layer of the passive element, a passive element cap insulating film is provided, which works as an etching stop layer when etching a contact of the upper electrode of the capacitor element.
摘要翻译：通过在同一步骤中制造包括下电极，电容器绝缘膜和上电极的电容器元件和薄膜电阻器元件来制造半导体器件。由于电容器元件的下电极衬有下层布线层（Cu布线），所以下电极具有极低的电阻。因此，即使下电极的膜厚变薄，寄生电阻也不会增加。电阻元件形成为具有与电容器元件的下电极相同的膜厚度。由于下部电极的膜厚薄，所以作为具有高电阻的电阻器。在无源元件的顶层中，设置无源元件帽绝缘膜，当蚀刻电容器元件的上电极的接触时，其被用作蚀刻停止层。

6. 发明授权

US08624328B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08624328B2
公开(公告)日：2014-01-07
申请号：US12591089
申请日：2009-11-06
申请人： Jun Kawahara , Yoshihiro Hayashi , Ippei Kume
发明人： Jun Kawahara , Yoshihiro Hayashi , Ippei Kume
IPC分类号： H01L27/06
CPC分类号： H01L27/0207 , H01L23/522 , H01L23/5223 , H01L23/53238 , H01L23/53295 , H01L27/10814 , H01L27/10852 , H01L27/10894 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： Provided is a semiconductor device including: a semiconductor substrate; a multi-layered wiring structure which is formed over the semiconductor substrate and in which a plurality of wiring layers, each of which is formed by a wiring and an insulating layer, are laminated; and a capacitive element having a lower electrode, a capacitor insulating layer, and an upper electrode which is embedded in the multi-layered wiring structure, wherein at least two or more of the wiring layers are provided between a lower capacitor wiring connected to the lower electrode and an upper capacitor wiring connected to the upper electrode.
摘要翻译：提供一种半导体器件，包括：半导体衬底; 形成在半导体衬底上并且其中由布线和绝缘层形成的多个布线层被层叠的多层布线结构; 以及具有嵌入在所述多层布线结构中的下电极，电容绝缘层和上电极的电容元件，其特征在于，所述布线层中的至少两个以上设置在与所述下层电极电极和连接到上电极的上电容器布线。

7. 发明授权

US08435828B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08435828B2
公开(公告)日：2013-05-07
申请号：US13006034
申请日：2011-01-13
申请人： Hironori Yamamoto , Yoshihiro Hayashi , Jun Kawahara , Tatsuya Usami , Koichi Ohto
发明人： Hironori Yamamoto , Yoshihiro Hayashi , Jun Kawahara , Tatsuya Usami , Koichi Ohto
IPC分类号： H01L51/40
CPC分类号： H01L21/76832 , H01L21/02126 , H01L21/022 , H01L21/02203 , H01L21/02274 , H01L21/76826 , H01L21/76829 , H01L21/76883
摘要： A method of manufacturing a semiconductor device includes forming a first insulating film over an underlying film by plasma polymerization of cyclic siloxane, and forming a second insulating film on the first insulating film by plasma polymerization of the cyclic siloxane continuously, after forming the first insulating film. The deposition rate of the first insulating film is slower than the deposition rate of the second insulating film.
摘要翻译：一种制造半导体器件的方法包括：通过环状硅氧烷的等离子体聚合在下面的膜上形成第一绝缘膜，并且在形成第一绝缘膜之后，通过环状硅氧烷的等离子体聚合在第一绝缘膜上形成第二绝缘膜。第一绝缘膜的沉积速度比第二绝缘膜的沉积速度慢。

8. 发明申请

US20110284991A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20110284991A1
公开(公告)日：2011-11-24
申请号：US13106590
申请日：2011-05-12
申请人： Kenichiro HIJIOKA , Ippei Kume , Naoya Inoue , Hiroki Shirai , Jun Kawahara , Yoshihiro Hayashi
发明人： Kenichiro HIJIOKA , Ippei Kume , Naoya Inoue , Hiroki Shirai , Jun Kawahara , Yoshihiro Hayashi
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L27/10894 , H01L21/76811 , H01L23/5223 , H01L27/10852 , H01L28/75 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a substrate; a multi-layered interconnect formed on the substrate, and having a plurality of interconnect layers, each of which being configured by an interconnect and an insulating layer, stacked therein; a memory circuit formed in a memory circuit region on the substrate in a plan view, and having a peripheral circuit and at least one capacitor element embedded in the multi-layered interconnect; and a logic circuit formed in a logic circuit region on the substrate, wherein the capacitor element is configured by a lower electrode, a capacitor insulating film, an upper electrode, an embedded electrode and an upper interconnect; the top surface of the upper interconnect, and the top surface of the interconnect configuring the logic circuit formed in the same interconnect layer with the upper interconnect, are aligned to the same plane.
摘要翻译：半导体器件具有基板; 形成在所述基板上的多层互连，并且具有多个互连层，每个互连层由布置在其中的互连和绝缘层构成; 在平面图形成在基板上的存储器电路区域中的存储电路，并且具有外围电路和嵌入多层互连中的至少一个电容元件; 以及形成在所述基板上的逻辑电路区域中的逻辑电路，其中所述电容器元件由下电极，电容器绝缘膜，上电极，嵌入电极和上互连构成; 上互连的顶表面和构成与上互连的同一互连层中形成的逻辑电路的互连的顶表面与同一平面对准。

9. 发明申请

US20050059788A1 Organic polymer film and method for producing the same 审中-公开
标题翻译：有机聚合物膜及其制造方法
公开(公告)号：US20050059788A1
公开(公告)日：2005-03-17
申请号：US10901189
申请日：2004-07-29
申请人： Nobutaka Kunimi , Masashi Komatsu , Jun Kawahara , Yoshihiro Hayashi
发明人： Nobutaka Kunimi , Masashi Komatsu , Jun Kawahara , Yoshihiro Hayashi
IPC分类号： C08F2/52 , C08F38/00
CPC分类号： C08F2/52
摘要： An organic polymer film with high mechanical strength, which is produced by a method comprising the steps of supplying a raw material gas containing an organic compound having at least one carbon-carbon triple bond in a molecule into a reaction chamber under reduced pressure, exciting the raw material gas in plasma generated in the reaction chamber, depositing the excited raw material gas on a surface of a substrate placed in the reaction chamber, and growing an organic polymer film on the surface of the substrate.
摘要翻译：一种具有高机械强度的有机聚合物膜，其通过包括以下步骤的方法制备：将分子内含有至少一个碳 - 碳三键的有机化合物的原料气体在减压下供给到反应室中，在反应室中产生的等离子体中的原料气体，将被激发的原料气体沉积在放置在反应室中的基板的表面上，并在基板的表面上生长有机聚合物膜。

10. 发明授权

US06344693B1 Semiconductor device and method for manufacturing same 有权
公开(公告)号：US06344693B1
公开(公告)日：2002-02-05
申请号：US09572632
申请日：2000-05-17
申请人： Jun Kawahara , Yoshihiro Hayashi
发明人： Jun Kawahara , Yoshihiro Hayashi
IPC分类号： H01L2348
CPC分类号： H01L21/76834 , H01L21/76801 , H01L21/76807 , H01L21/7681 , H01L21/76813 , H01L21/76829 , H01L21/76832 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： In a method for manufacturing a semiconductor device having a first insulation film, a second insulation film formed over the first insulation film, an inlayed interconnection layer formed in the second insulation film, and an organic film provided on the inlayed interconnection layer and the second insulation film, the organic film having a dielectric constant lower than the second insulation film, the organic film is grown inside a vacuum chamber.

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