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1. 再颁专利

USRE40507E1 Method of forming pre-metal dielectric film on a semiconductor substrate including first layer of undoped oxide of high ozone:TEOS volume ratio and second layer of low ozone doped BPSG 有权
标题翻译：在包括高臭氧未掺杂氧化物的第一层：TEOS体积比和第二层低臭氧掺杂BPSG的半导体衬底上形成预金属介电膜的方法
公开(公告)号：USRE40507E1
公开(公告)日：2008-09-16
申请号：US10606426
申请日：2003-06-25
申请人： Amit S. Kelkar , Michael D. Whiteman
发明人： Amit S. Kelkar , Michael D. Whiteman
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/02129 , H01L21/02164 , H01L21/022 , H01L21/02271 , H01L21/31051 , H01L21/31612 , H01L21/31625
摘要： A method of forming a pre-metal dielectric film having good as deposited gapfill characteristics, as well as good mobile-ion gettering capability. The method involves first depositing a layer of high-ozone undoped silicon dioxide film having a high ozone/TEOS volume ratio. Then, a low-ozone doped BPSG film is deposited over the high-ozone undoped silicon dioxide layer. The film layers are heat treated to densify the film, and then the top layer is planarized using known planarization techniques to a thickness that allows for adequate mobile-ion gettering.
摘要翻译：形成具有良好的作为沉积间隙填充特性的预金属电介质膜的方法，以及良好的移动离子吸除能力。该方法首先沉积具有高臭氧/ TEOS体积比的高臭氧未掺杂的二氧化硅膜层。然后，在高臭氧未掺杂的二氧化硅层上沉积低臭氧掺杂的BPSG膜。对膜层进行热处理以使膜致密化，然后使用已知的平面化技术对顶层进行平面化，以达到允许足够的移动离子吸气的厚度。

2. 发明授权

US06709990B2 Method for fabrication of a high capacitance interpoly dielectric 有权
标题翻译：高电容互聚电介质的制造方法
公开(公告)号：US06709990B2
公开(公告)日：2004-03-23
申请号：US10267354
申请日：2002-10-09
申请人： Mark A. Good , Amit S. Kelkar
发明人： Mark A. Good , Amit S. Kelkar
IPC分类号： H01L21469
CPC分类号： H01L21/02326 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02271 , H01L21/3144
摘要： A method for fabricating a silicon dioxide/silicon nitride/silicon dioxide (ONO) stacked composite having a thin silicon nitride layer for providing a high capacitance interpoly dielectric structure. In the formation of the ONO composite, a bottom silicon dioxide layer is formed on a substrate such as polysilicon. A silicon nitride layer is formed on the silicon dioxide layer and is thinned by oxidation. The oxidation of the silicon nitride film consumes some of the silicon nitride by a reaction that produces a silicon dioxide layer. This silicon dioxide layer is removed with a hydrofluoric acid dilution. The silicon nitride layer is again thinned by re-oxidization as a top silicon dioxide layer is formed on the silicon nitride layer. A second layer of polysilicon is deposited over the silicon nitride, forming an interpoly dielectric.
摘要翻译：一种制造具有薄氮化硅层的二氧化硅/氮化硅/二氧化硅（ONO）层叠复合体的方法，用于提供高电容互聚电介质结构。在ONO复合材料的形成中，在诸如多晶硅的衬底上形成底部二氧化硅层。在二氧化硅层上形成氮化硅层，通过氧化而变薄。氮化硅膜的氧化通过产生二氧化硅层的反应消耗一些氮化硅。用氢氟酸稀释液除去该二氧化硅层。当在氮化硅层上形成顶部二氧化硅层时，氮化硅层又被再次氧化而变薄。在氮化硅上沉积第二层多晶硅，形成多晶硅间电介质。

3. 发明授权

US06291367B1 Method for depositing a selected thickness of an interlevel dielectric material to achieve optimum global planarity on a semiconductor wafer 有权
标题翻译：用于沉积选定厚度的层间电介质材料以在半导体晶片上实现最佳全局平面度的方法
公开(公告)号：US06291367B1
公开(公告)日：2001-09-18
申请号：US09586660
申请日：2000-06-01
申请人： Amit S. Kelkar
发明人： Amit S. Kelkar
IPC分类号： H01L2131
CPC分类号： H01L21/02274 , H01L21/02107 , H01L21/31051 , H01L21/31612 , H01L21/76819
摘要： A method of depositing an interlevel dielectric material on a semiconductor wafer at a selected thickness such that the best global planarity of the dielectric layer is achieved. A model for the deposition of a silicon dioxide layer is developed based upon the physics of deposition and sputtering and based upon the minimum geometry of features in the semiconductor device. First the geometric parameters of the metal features are determined. Then, based upon the most aggressive aspect ratio between metal lines, the deposition rate to sputter rate ratio is calculated. The film thickness for optimum global planarity is determined based on the calculated ratio. The dielectric material is then deposited on the metal features using HDP-CVD techniques in a manner using the calculated ratio to stop deposition at the determined film thickness such that the optimum thickness for global planarity is achieved.
摘要翻译：在半导体晶片上以选定的厚度沉积层间电介质材料的方法，使得实现电介质层的最佳全局平坦度。基于沉积和溅射的物理学和基于半导体器件中的特征的最小几何形状开发沉积二氧化硅层的模型。首先确定金属特征的几何参数。然后，基于金属线之间最具侵蚀性的纵横比，计算沉积速率与溅射速率比。基于计算出的比例确定最佳全局平面度的膜厚度。然后使用HDP-CVD技术以介电材料沉积金属特征，使用计算出的比例，在所确定的膜厚度上停止沉积，使得实现全局平面度的最佳厚度。

4. 发明申请

US20120193808A1 BONDED STACKED WAFERS AND METHODS OF ELECTROPLATING BONDED STACKED WAFERS 有权
标题翻译：结合堆叠的波形和电镀结合堆叠的波形的方法
公开(公告)号：US20120193808A1
公开(公告)日：2012-08-02
申请号：US13018534
申请日：2011-02-01
申请人： Quanbo Zou , Uppili Sridhar , Amit S. Kelkar , Xuejun Ying
发明人： Quanbo Zou , Uppili Sridhar , Amit S. Kelkar , Xuejun Ying
IPC分类号： H01L23/48 , H01L21/60
CPC分类号： H01L24/83 , B81C3/001 , B81C2201/0197 , B81C2203/035 , C25D7/123 , C25D17/001 , C25D17/005 , C25D17/007 , H01L23/481 , H01L24/13 , H01L24/94 , H01L25/50 , H01L2224/13144 , H01L2225/06513 , H01L2225/06541 , H01L2924/01068 , H01L2924/10253 , H01L2924/12042 , H01L2924/1461 , H01L2924/30101 , H01L2924/00014 , H01L2924/00
摘要： A wafer structure includes a first wafer stack and a first bonding layer disposed on the first wafer stack. The wafer structure further includes a second wafer stack that includes a first surface and a second surface opposing the first surface. A second bonding layer is disposed on the second surface and is in contact with the first bonding layer. The second wafer stack comprises through-silicon-vias (TSVs) that extend from the first surface to the second bonding layer. A seed layer is disposed on the first surface and is in contact with the TSVs.
摘要翻译：晶片结构包括第一晶片堆叠和设置在第一晶片堆叠上的第一结合层。晶片结构还包括第二晶片堆叠，其包括第一表面和与第一表面相对的第二表面。第二接合层设置在第二表面上并与第一接合层接触。第二晶片堆叠包括从第一表面延伸到第二结合层的穿硅通孔（TSV）。种子层设置在第一表面上并与TSV接触。

5. 发明授权

US06828212B2 Method of forming shallow trench isolation structure in a semiconductor device 有权
标题翻译：在半导体器件中形成浅沟槽隔离结构的方法
公开(公告)号：US06828212B2
公开(公告)日：2004-12-07
申请号：US10278294
申请日：2002-10-22
申请人： Timothy M. Barry , Nicolas Degors , Donald A. Erickson , Amit S. Kelkar , Bradley J. Larsen
发明人： Timothy M. Barry , Nicolas Degors , Donald A. Erickson , Amit S. Kelkar , Bradley J. Larsen
IPC分类号： H01L21762
CPC分类号： H01L27/11521 , H01L21/3081 , H01L21/76235
摘要： A method for fabricating a shallow trench isolation structure is described, in which a bottom pad oxide layer, a middle silicon nitride layer, a middle oxide layer and a top silicon nitride layer are sequentially formed on a silicon substrate. Photolithographic masking and anisotropic etching are then conducted to form a trench in the substrate. An oxide material is then deposited on top of the top silicon nitride layer, filling up the trenches at the same time. A chemical mechanical polishing step is then employed to remove the oxide material by using the top silicon nitride layer as a barrier layer. The top silicon nitride layer is then removed, followed by an isotropic etch of the oxide layer below. With the middle nitride layer acting as a natural etch stop, the oxide material is sculpted to a desirable shape. The middle nitride layer and the pad oxide layer are subsequently removed to complete the fabrication of a shallow trench isolation structure.
摘要翻译：描述了一种用于制造浅沟槽隔离结构的方法，其中在硅衬底上依次形成底部衬垫氧化物层，中间氮化硅层，中间氧化物层和顶部氮化硅层。然后进行光刻掩模和各向异性蚀刻以在衬底中形成沟槽。然后将氧化物材料沉积在顶部氮化硅层的顶部，同时填充沟槽。然后采用化学机械抛光步骤，通过使用顶部氮化硅层作为阻挡层去除氧化物材料。然后去除顶部氮化硅层，随后对下面的氧化物层进行各向同性蚀刻。当中间氮化物层用作自然蚀刻停止物时，氧化物材料被雕刻成期望的形状。随后去除中间氮化物层和焊盘氧化物层以完成浅沟槽隔离结构的制造。

6. 发明授权

US06495475B2 Method for fabrication of a high capacitance interpoly dielectric 失效
标题翻译：高电容互聚电介质的制造方法
公开(公告)号：US06495475B2
公开(公告)日：2002-12-17
申请号：US09821365
申请日：2001-03-28
申请人： Mark A. Good , Amit S. Kelkar
发明人： Mark A. Good , Amit S. Kelkar
IPC分类号： H01L21469
CPC分类号： H01L21/02326 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02271 , H01L21/3144
摘要： A method for fabricating a silicon dioxide/silicon nitride/silicon dioxide (ONO) stacked composite having a thin silicon nitride layer for providing a high capacitance interpoly dielectric structure. In the formation of the ONO composite, a bottom silicon dioxide layer is formed on a substrate such as polysilicon. A silicon nitride layer is formed on the silicon dioxide-layer and is thinned by oxidation. The oxidation of the silicon nitride film consumes some of the silicon nitride by a reaction that produces a temporary silicon dioxide layer. The temporary silicon dioxide layer is removed with a hydrofluoric acid dilution. The silicon nitride layer is again thinned by re-oxidization as a top silicon dioxide layer is formed on the silicon nitride layer. A layer of polysilicon is deposited over the silicon nitride, forming an interpoly dielectric.
摘要翻译：一种制造具有薄氮化硅层的二氧化硅/氮化硅/二氧化硅（ONO）层叠复合体的方法，用于提供高电容互聚电介质结构。在ONO复合材料的形成中，在诸如多晶硅的衬底上形成底部二氧化硅层。在二氧化硅层上形成氮化硅层，并通过氧化而变薄。通过产生临时二氧化硅层的反应，氮化硅膜的氧化消耗一些氮化硅。用氢氟酸稀释液除去临时二氧化硅层。当在氮化硅层上形成顶部二氧化硅层时，氮化硅层又被再次氧化而变薄。在氮化硅上沉积多晶硅层，形成多晶硅间电介质。

7. 发明授权

US08124916B2 Thermal processing of silicon wafers 有权
标题翻译：硅片的热处理
公开(公告)号：US08124916B2
公开(公告)日：2012-02-28
申请号：US11735639
申请日：2007-04-16
申请人： Amit S. Kelkar , Larry Puechner , David E. Billings
发明人： Amit S. Kelkar , Larry Puechner , David E. Billings
IPC分类号： F27B5/04 , F27B5/16 , H01L21/324
CPC分类号： H01L21/324 , F27B17/0025 , H01L21/67017 , H01L21/67253
摘要： Apparatus and methods that minimize surface defect development in silicon wafers during thermal processing at relatively high temperatures at which silicon wafers are annealed and at less extreme temperature, or for other purposes. The apparatus and methods have utility to horizontally-disposed furnaces for silicon wafers and to vertically-oriented furnaces in which larger wafers can be thermally processed. A selectively-sealable process tube encloses silicon wafers during heating of the silicon wafers to a predetermined temperature, and a heating atmosphere supply system induces through the process tube a positive flow of a process gas, such as hydrogen or argon, that is non-reactive with solid silicon at the predetermined temperature. A process tube outlet vents gas from the process tube, and an impurity sensor in the process tube outlet detects oxygen and moisture in the vented gas to verify the purity of the atmosphere surrounding the wafers during thermal processing.
摘要翻译：在硅晶片退火的较高温度和较不极端的温度下，或用于其他目的的热处理期间，硅晶片的表面缺陷发展最小化的装置和方法。该装置和方法适用于用于硅晶片的水平布置的炉和垂直定向的炉，其中可以对较大的晶片进行热处理。在将硅晶片加热至预定温度期间，可选择性密封的工艺管将硅晶片封装在一起，并且加热气氛供应系统通过处理管引起无反应性的工艺气体（例如氢气或氩气）的正流固体硅处于预定温度。处理管出口从处理管中排出气体，并且处理管出口中的杂质传感器检测排出气体中的氧气和水分，以验证热处理期间晶片周围的气氛的纯度。

8. 发明申请

US20080254599A1 Thermal Processing of Silicon Wafers 有权
标题翻译：硅晶片的热处理
公开(公告)号：US20080254599A1
公开(公告)日：2008-10-16
申请号：US11735639
申请日：2007-04-16
申请人： Amit S. Kelkar , Larry Puechner , David E. Billings
发明人： Amit S. Kelkar , Larry Puechner , David E. Billings
IPC分类号： H01L21/324 , F27B9/02
CPC分类号： H01L21/324 , F27B17/0025 , H01L21/67017 , H01L21/67253
摘要： Apparatus and methods that minimize surface defect development in silicon wafers during thermal processing at relatively high temperatures at which silicon wafers are annealed and at less extreme temperature, or for other purposes. The apparatus and methods have utility to horizontally-disposed furnaces for silicon wafers and to vertically-oriented furnaces in which larger wafers can be thermally processed. A selectively-sealable process tube encloses silicon wafers during heating of the silicon wafers to a predetermined temperature, and a heating atmosphere supply system induces through the process tube a positive flow of a process gas, such as hydrogen or argon, that is non-reactive with solid silicon at the predetermined temperature. A process tube outlet vents gas from the process tube, and an impurity sensor in the process tube outlet detects oxygen and moisture in the vented gas to verify the purity of the atmosphere surrounding the wafers during thermal processing.
摘要翻译：在硅晶片退火的较高温度和较不极端的温度下，或用于其他目的的热处理期间，硅晶片的表面缺陷发展最小化的装置和方法。该装置和方法适用于用于硅晶片的水平布置的炉和垂直定向的炉，其中可以对较大的晶片进行热处理。在将硅晶片加热至预定温度期间，可选择性密封的工艺管将硅晶片封装在一起，并且加热气氛供应系统通过处理管引起无反应性的工艺气体（例如氢气或氩气）的正流固体硅处于预定温度。处理管出口从处理管中排出气体，并且处理管出口中的杂质传感器检测排出气体中的氧气和水分，以验证热处理期间晶片周围的气氛的纯度。

9. 发明授权

US08970043B2 Bonded stacked wafers and methods of electroplating bonded stacked wafers 有权
标题翻译：粘合的堆叠晶片和电镀粘合堆叠晶片的方法
公开(公告)号：US08970043B2
公开(公告)日：2015-03-03
申请号：US13018534
申请日：2011-02-01
申请人： Quanbo Zou , Uppili Sridhar , Amit S. Kelkar , Xuejun Ying
发明人： Quanbo Zou , Uppili Sridhar , Amit S. Kelkar , Xuejun Ying
IPC分类号： H01L23/02 , H01L23/48 , H01L23/52 , H01L29/40 , C25D17/00 , B81C3/00 , C25D7/12 , H01L25/00 , H01L23/00
CPC分类号： H01L24/83 , B81C3/001 , B81C2201/0197 , B81C2203/035 , C25D7/123 , C25D17/001 , C25D17/005 , C25D17/007 , H01L23/481 , H01L24/13 , H01L24/94 , H01L25/50 , H01L2224/13144 , H01L2225/06513 , H01L2225/06541 , H01L2924/01068 , H01L2924/10253 , H01L2924/12042 , H01L2924/1461 , H01L2924/30101 , H01L2924/00014 , H01L2924/00
摘要： A wafer structure includes a first wafer stack and a first bonding layer disposed on the first wafer stack. The wafer structure further includes a second wafer stack that includes a first surface and a second surface opposing the first surface. A second bonding layer is disposed on the second surface and is in contact with the first bonding layer. The second wafer stack comprises through-silicon-vias (TSVs) that extend from the first surface to the second bonding layer. A seed layer is disposed on the first surface and is in contact with the TSVs.
摘要翻译：晶片结构包括第一晶片堆叠和设置在第一晶片堆叠上的第一结合层。晶片结构还包括第二晶片堆叠，其包括第一表面和与第一表面相对的第二表面。第二接合层设置在第二表面上并与第一接合层接触。第二晶片堆叠包括从第一表面延伸到第二结合层的穿硅通孔（TSV）。种子层设置在第一表面上并与TSV接触。

10. 发明申请

US20120194306A1 PREVENTING CONTACT STICTION IN MICRO RELAYS 审中-公开
标题翻译：防止微型继电器中的接触件
公开(公告)号：US20120194306A1
公开(公告)日：2012-08-02
申请号：US13018499
申请日：2011-02-01
申请人： Uppili Sridhar , Quanbo Zou , Amit S. Kelkar , Xuejun Ying
发明人： Uppili Sridhar , Quanbo Zou , Amit S. Kelkar , Xuejun Ying
IPC分类号： H01H1/0237
CPC分类号： H01H1/0237 , H01H59/0009 , H01H2001/0084
摘要： A micro relay of a micro-electro-mechanical system (MEMS), includes a cap substrate, a first electrical contact, an actuator, and a second electrical contact. The first electrical contact is formed on the cap substrate, includes a platinum group metal, and includes a first surface layer of an oxide of the platinum group metal. The second electrical contact is formed on the actuator, includes the platinum group metal, and includes a second surface layer of the oxide of the platinum group metal. At least a first portion of the first surface layer contacts at least a second portion of the second surface layer during cycling of the micro relay.
摘要翻译：微电子机械系统（MEMS）的微型继电器包括盖基板，第一电触头，致动器和第二电触点。第一电接触形成在盖基板上，包括铂族金属，并且包括铂族金属的氧化物的第一表面层。第二电触点形成在致动器上，包括铂族金属，并且包括铂族金属的氧化物的第二表面层。第一表面层的至少第一部分在微型继电器的循环期间接触第二表面层的至少第二部分。

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