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1. 发明申请

US20060248254A1 Data transfer device, semiconductor integrated circuit, and microcomputer 失效
公开(公告)号：US20060248254A1
公开(公告)日：2006-11-02
申请号：US11475937
申请日：2006-06-28
申请人： Naoki Mitsuishi
发明人： Naoki Mitsuishi
IPC分类号： G06F13/36
CPC分类号： G06F13/405 , G06F13/362
摘要： It is aimed at improving the efficiency of data transfer processing and the concurrent data processing on a central processing unit. A data transfer device can independently request a bus access right and output an address to a first bus (IBUS) and a second bus (PBUS). It is possible to solve the state of competing for the bus access right between both buses. While the bus access right of one bus is granted for reading or writing, the bus access right of the other bus can be released. When the data transfer device releases the bus access right for the first bus, a central processing unit can process data. In response to one data transfer start request, the bus access right is requested for one bus and the other bus, There is not used a sequence of requesting the bus access right in response to different data transfer requests for respective buses. It is possible to simplify a handshake sequence of a data transfer request and its acknowledgment.

2. 发明申请

US20050251615A1 Microcomputer 审中-公开
标题翻译：微电脑
公开(公告)号：US20050251615A1
公开(公告)日：2005-11-10
申请号：US11180554
申请日：2005-07-14
申请人： Naoki Mitsuishi
发明人： Naoki Mitsuishi
IPC分类号： G11C17/00 , G06F12/00 , G06F12/02 , G06F15/78 , G06F21/00 , G11C16/02
CPC分类号： G06F12/0223 , G06F15/7814 , G06F21/79
摘要： A single chip type microcomputer includes at least a central processing unit (CPU), a random-access memory (RAM), a mask read-only memory (CPU) and an electrically writable ROM such as an electrically erasable and programmable read-only memory (EEPROM). The electrically writable ROM stores both the user program and data to be preserved. The microcomputer includes further a memory for storing a write control program for controlling the write operation to the writable ROM, and the electrically writable ROM and the memory are disposed at mutually different address positions on the address space of CPU. The proportion of size of the user program region and the data region in the writable ROM can be selected in a free proportion.
摘要翻译：单片式微型计算机至少包括中央处理单元（CPU），随机存取存储器（RAM），掩模只读存储器（CPU）和电可写ROM，诸如电可擦除和可编程只读存储器（EEPROM）。电可写ROM存储要保存的用户程序和数据。微型计算机还包括用于存储用于控制对可写ROM的写入操作的写入控制程序的存储器，并且电可写ROM和存储器设置在CPU的地址空间上的相互不同的地址位置处。用户程序区域和可写入ROM中的数据区域的大小的比例可以自由选择。

3. 发明授权

US06907514B2 Microcomputer and microcomputer system 有权
标题翻译：微电脑和微机系统
公开(公告)号：US06907514B2
公开(公告)日：2005-06-14
申请号：US10887843
申请日：2004-07-12
申请人： Naoki Mitsuishi
发明人： Naoki Mitsuishi
IPC分类号： G06F3/00 , G06F11/30 , G06F13/14 , G06F13/16 , G06F13/28 , G06F15/00
CPC分类号： G06F13/16 , G06F13/28
摘要： A microcomputer is provided with a data-transfer unit such as a DMA (direct memory access) controller for controlling a transfer of data through an external bus. Used in an access to an external device controlled by the data-transfer unit, a bus-interface means of the microcomputer includes a buffer-register means which can be specified as either a source location or a destination location of a data transfer. Thus, an internal-bus master such as a CPU employed in the microcomputer is capable of reading out information such as a packet command from the buffer-register means at a high speed through an internal bus without using the external bus and, hence, capable of carrying out an operation reflecting a transfer control condition specified by the packet command.
摘要翻译：微型计算机设置有数据传送单元，例如DMA（直接存储器访问）控制器，用于通过外部总线控制数据传送。在用于访问由数据传送单元控制的外部设备的情况下，微计算机的总线接口装置包括可指定为数据传送的源位置或目的地位置的缓冲寄存器装置。因此，微型计算机中使用的诸如CPU的内部总线主机能够通过内部总线从缓冲寄存器装置高速地读出诸如分组命令的信息，而不使用外部总线，因此能够执行反映由分组命令指定的传送控制条件的操作。

4. 发明授权

US5930488A Semiconductor integrated circuit device with a central processing unit, a data transfer controller and a memory storing data transfer parameters 失效
标题翻译：具有中央处理单元的半导体集成电路器件，数据传输控制器和存储数据传输参数的存储器
公开(公告)号：US5930488A
公开(公告)日：1999-07-27
申请号：US822026
申请日：1997-03-24
申请人： Naoki Mitsuishi
发明人： Naoki Mitsuishi
IPC分类号： G06F15/78 , G06F9/312 , G06F13/36 , G06F13/00
CPC分类号： G06F9/30043
摘要： The invention provides a semiconductor integrated circuit device, which minimizes an increase in the physical and logical size, allows data transfers invoked by a large number of interrupts, and improves the processing efficiency. This semiconductor integrated circuit device is applied to a single chip microcomputer and includes function blocks such as CPU, data transfer controller DTC, ROM, RAMI, RAMP, timer, pulse output circuit, serial communication interface SCI, A/D converter, IOP0-11, interrupt controller, and bus controller BSC. The internal address bus IAB and the internal data bus IDB are connected to CPU, ROM, RAMI and BSC. The internal address bus PAB and the internal data bus PDB are connected to BSC, RAMP, timer, pulse output circuit, SCI, A/D converter, interrupt controller, and IOP0-11. Further, PDB is connected to DTC.
摘要翻译：本发明提供一种使物理和逻辑大小增加最小化的半导体集成电路器件，允许由大量中断引起的数据传输，并且提高了处理效率。该半导体集成电路器件应用于单片机，包括CPU，数据传输控制器DTC，ROM，RAMI，RAMP，定时器，脉冲输出电路，串行通信接口SCI，A / D转换器，IOP0-11等功能块，中断控制器和总线控制器BSC。内部地址总线IAB和内部数据总线IDB连接到CPU，ROM，RAMI和BSC。内部地址总线PAB和内部数据总线PDB连接到BSC，RAMP，定时器，脉冲输出电路，SCI，A / D转换器，中断控制器和IOP0-11。此外，PDB连接到DTC。

5. 发明授权

US5774702A Integrated circuit having function blocks operating in response to clock signals 失效
标题翻译：具有响应时钟信号工作的功能块的集成电路
公开(公告)号：US5774702A
公开(公告)日：1998-06-30
申请号：US561728
申请日：1995-11-22
申请人： Naoki Mitsuishi , Kenichi Ishibashi , Koichi Hashimura
发明人： Naoki Mitsuishi , Kenichi Ishibashi , Koichi Hashimura
IPC分类号： G06F15/78 , G06F1/04 , G06F1/08 , G06F1/10 , G06F1/06
CPC分类号： G06F1/08
摘要： A semiconductor integrated circuit comprising a clock pulse generator, peripheral function blocks and bus master modules. The peripheral function blocks are commonly supplied with a first system clock signal of a constant frequency generated on the basis of the output from the clock pulse generator. The bus master modules are fed with a second system clock signal generated on the basis of the pulse generator output. The frequency of the second system clock signal is variable and lower than that of the first system clock signal. The function blocks supplied with the first system clock signal are connected to a data bus separate from the one connected to the function blocks fed with the second system clock signal.
摘要翻译：一种半导体集成电路，包括时钟脉冲发生器，外围功能块和总线主模块。周边功能块通常被提供有基于来自时钟脉冲发生器的输出而产生的恒定频率的第一系统时钟信号。总线主模块馈送有基于脉冲发生器输出产生的第二系统时钟信号。第二系统时钟信号的频率可变并且低于第一系统时钟信号的频率。与第一系统时钟信号一起提供的功能块连接到与连接到与第二系统时钟信号馈送的功能块相连的数据总线上的数据总线。

6. 发明授权

US08645742B2 Semiconductor device operating according to an operation clock and having a serial communication interface performing external communications according to a unit transfer time based on the operation clock 有权
标题翻译：半导体器件根据操作时钟操作并具有串行通信接口，其基于操作时钟根据单位传送时间执行外部通信
公开(公告)号：US08645742B2
公开(公告)日：2014-02-04
申请号：US12951004
申请日：2010-11-20
申请人： Naoki Mitsuishi
发明人： Naoki Mitsuishi
IPC分类号： G06F1/00
CPC分类号： H03K23/507
摘要： Serial communication with a bit rate close to a required bit rate can be performed, regardless of the frequency of an operation clock.A semiconductor device includes a serial communication interface that operates according to a certain operation clock. The serial communication interface is provided with a baud rate generator that generates a basic clock for counting the operation clock to define the unit transfer time based on the count, and a transmission/reception controller for performing control of transmission and reception according to the generated basic clock. Further, the serial communication interface is provided with a bit rate modulator capable of realizing a desired bit rate by partially masking supply of the operation clock to the baud rate generator, and thereby serial communication with a bit rate close to a required bit rate is realized.
摘要翻译：无论操作时钟的频率如何，都可以执行接近所需比特率的比特率的串行通信。半导体器件包括根据特定操作时钟进行操作的串行通信接口。串行通信接口设置有波特率发生器，该波特率发生器基于计数产生用于对操作时钟进行计数以定义单位传送时间的基本时钟，以及发送/接收控制器，用于根据生成的基本信息执行发送和接收控制时钟。此外，串行通信接口设置有能够通过部分地掩蔽向波特率发生器提供操作时钟来实现期望比特率的比特率调制器，从而实现接近所需比特率的比特率的串行通信。

7. 发明申请

US20110129004A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110129004A1
公开(公告)日：2011-06-02
申请号：US12951004
申请日：2010-11-20
申请人： Naoki MITSUISHI
发明人： Naoki MITSUISHI
IPC分类号： H04B1/38
CPC分类号： H03K23/507
摘要： Serial communication with a bit rate close to a required bit rate can be performed, regardless of the frequency of an operation clock.A semiconductor device includes a serial communication interface that operates according to a certain operation clock. The serial communication interface is provided with a baud rate generator that generates a basic clock for counting the operation clock to define the unit transfer time based on the count, and a transmission/reception controller for performing control of transmission and reception according to the generated basic clock. Further, the serial communication interface is provided with a bit rate modulator capable of realizing a desired bit rate by partially masking supply of the operation clock to the baud rate generator, and thereby serial communication with a bit rate close to a required bit rate is realized.
摘要翻译：无论操作时钟的频率如何，都可以执行接近所需比特率的比特率的串行通信。半导体器件包括根据特定操作时钟进行操作的串行通信接口。串行通信接口设置有波特率发生器，该波特率发生器基于计数产生用于对操作时钟进行计数以定义单位传送时间的基本时钟，以及发送/接收控制器，用于根据生成的基本信息进行发送和接收控制时钟。此外，串行通信接口设置有能够通过部分地掩蔽向波特率发生器提供操作时钟来实现期望比特率的比特率调制器，从而实现接近所需比特率的比特率的串行通信。

8. 发明授权

US07260667B2 Data transfer device, semiconductor integrated circuit, and microcomputer 失效
标题翻译：数据传输设备，半导体集成电路和微机
公开(公告)号：US07260667B2
公开(公告)日：2007-08-21
申请号：US11475937
申请日：2006-06-28
申请人： Naoki Mitsuishi
发明人： Naoki Mitsuishi
IPC分类号： G06F13/00
CPC分类号： G06F13/405 , G06F13/362
摘要： It is aimed at improving the efficiency of data transfer processing and the concurrent data processing on a central processing unit. A data transfer device can independently request a bus access right and output an address to a first bus (IBUS) and a second bus (PBUS). It is possible to solve the state of competing for the bus access right between both buses. While the bus access right of one bus is granted for reading or writing, the bus access right of the other bus can be released. When the data transfer device releases the bus access right for the first bus, a central processing unit can process data. In response to one data transfer start request, the bus access right is requested for one bus and the other bus, There is not used a sequence of requesting the bus access right in response to different data transfer requests for respective buses. It is possible to simplify a handshake sequence of a data transfer request and its acknowledgment.
摘要翻译：它旨在提高数据传输处理的效率和中央处理单元的并发数据处理。数据传输设备可以独立地请求总线访问权限，并将地址输出到第一总线（IBUS）和第二总线（PBUS）。可以解决两条公交车之间的公共汽车通行权竞争的状态。当一条总线的总线访问权限被授予读取或写入时，可以释放另一条总线的总线访问权限。当数据传输设备释放第一个总线的总线访问权限时，中央处理单元可以处理数据。响应于一个数据传输启动请求，对于一个总线和另一个总线请求总线访问权限。响应于各个总线的不同数据传送请求，没有使用请求总线访问权限的顺序。可以简化数据传输请求的握手顺序及其确认。

9. 发明授权

US07216193B2 Data transfer device, semiconductor integrated circuit, and microcomputer 失效
公开(公告)号：US07216193B2
公开(公告)日：2007-05-08
申请号：US11475916
申请日：2006-06-28
申请人： Naoki Mitsuishi
发明人： Naoki Mitsuishi
IPC分类号： G06F13/00
CPC分类号： G06F13/405 , G06F13/362
摘要： It is aimed at improving the efficiency of data transfer processing and the concurrent data processing on a central processing unit. A data transfer device can independently request a bus access right and output an address to a first bus (IBUS) and a second bus (PBUS). It is possible to solve the state of competing for the bus access right between both buses. While the bus access right of one bus is granted for reading or writing, the bus access right of the other bus can be released. When the data transfer device releases the bus access right for the first bus, a central processing unit can process data. In response to one data transfer start request, the bus access right is requested for one bus and the other bus, There is not used a sequence of requesting the bus access right in response to different data transfer requests for respective buses. It is possible to simplify a handshake sequence of a data transfer request and its acknowledgment.

10. 发明授权

US07093055B2 Data transfer device, semiconductor integrated circuit, and microcomputer 失效
公开(公告)号：US07093055B2
公开(公告)日：2006-08-15
申请号：US10705902
申请日：2003-11-13
申请人： Naoki Mitsuishi
发明人： Naoki Mitsuishi
IPC分类号： G06F13/00
CPC分类号： G06F13/405 , G06F13/362
摘要： It is aimed at improving the efficiency of data transfer processing and the concurrent data processing on a central processing unit. A data transfer device can independently request a bus access right and output an address to a first bus (IBUS) and a second bus (PBUS). It is possible to solve the state of competing for the bus access right between both buses. While the bus access right of one bus is granted for reading or writing, the bus access right of the other bus can be released. When the data transfer device releases the bus access right for the first bus, a central processing unit can process data. In response to one data transfer start request, the bus access right is requested for one bus and the other bus, There is not used a sequence of requesting the bus access right in response to different data transfer requests for respective buses. It is possible to simplify a handshake sequence of a data transfer request and its acknowledgment.

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