专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090327609A1 Performance based cache management 审中-公开
标题翻译：基于性能的缓存管理
公开(公告)号：US20090327609A1
公开(公告)日：2009-12-31
申请号：US12215914
申请日：2008-06-30
申请人： Bruce Fleming , Ticky Thakkar
发明人： Bruce Fleming , Ticky Thakkar
IPC分类号： G06F12/08 , G06F1/26
CPC分类号： G06F12/0802 , G06F12/0815 , G06F12/0864 , G06F12/0897 , G06F2212/1028 , G06F2212/502 , G06F2212/601 , Y02D10/13
摘要： Methods and apparatus to manage cache memory are disclosed. In one embodiment, an electronic device comprises a first processing unit, a first cache memory, and a first cache controller, and a power management module, wherein the power management module determines at least one operating parameter for the cache memory and passes the at least one operating parameter for the cache memory to a cache controller. Further, the first cache controller manages the cache memory according to the at least one operating parameter, and the power management module evaluates, in the power management module, operating data for the cache memory from the cache controller, and generates, in the power management module, at least one modified operating parameter for the cache memory based on the operating data for the cache memory from the cache controller.
摘要翻译：公开了管理高速缓冲存储器的方法和装置。在一个实施例中，电子设备包括第一处理单元，第一高速缓存存储器和第一高速缓存控制器以及电源管理模块，其中电源管理模块确定高速缓冲存储器的至少一个操作参数，并且至少通过缓存控制器的高速缓存的一个操作参数。此外，第一高速缓存控制器根据至少一个操作参数管理高速缓冲存储器，并且电源管理模块在电源管理模块中评估来自高速缓存控制器的高速缓冲存储器的操作数据，并且在电源管理模块，基于来自高速缓存控制器的高速缓冲存储器的操作数据，用于高速缓冲存储器的至少一个修改的操作参数。

2. 发明授权

US06230253B1 Executing partial-width packed data instructions 失效
标题翻译：执行部分宽度打包的数据指令
公开(公告)号：US06230253B1
公开(公告)日：2001-05-08
申请号：US09053127
申请日：1998-03-31
申请人： Patrice Roussel , Ticky Thakkar
发明人： Patrice Roussel , Ticky Thakkar
IPC分类号： G06F922
CPC分类号： G06F9/3875 , G06F9/30014 , G06F9/30036 , G06F9/30112 , G06F9/3013 , G06F9/30134 , G06F9/30145 , G06F9/30167 , G06F9/3017 , G06F9/30181 , G06F9/30196 , G06F9/384 , G06F9/3885
摘要： A method and apparatus are provided for executing scalar packed data instructions. According to one aspect of the invention, a processor includes a plurality of registers, a register renaming unit coupled to the plurality of registers, a decoder coupled to the register renaming unit, and a partial-width execution unit coupled to the decoder. The register renaming unit provides an architectural register file to store packed data operands each of which include a plurality of data elements. The decoder is configured to decode a first and second set of instructions that each specify one or more registers in the architectural register file. Each of the instructions in the first set of instructions specify operations to be performed on all of the data elements stored in the one or more specified registers. In contrast, each of the instructions in the second set of instructions specify operations to be performed on only a subset of the data element stored in the one or more specified registers. The partial-width execution unit is configured to execute operations specified by either of the first or the second set of instructions.
摘要翻译：提供了一种用于执行标量打包数据指令的方法和装置。根据本发明的一个方面，处理器包括多个寄存器，耦合到多个寄存器的寄存器重命名单元，耦合到寄存器重命名单元的解码器以及耦合到解码器的部分宽度执行单元。寄存器重命名单元提供架构寄存器文件以存储打包数据操作数，每个数据操作数包括多个数据元素。解码器被配置为解码每个指定体系结构寄存器文件中的一个或多个寄存器的第一和第二组指令。第一组指令中的每个指令指定要对存储在一个或多个指定寄存器中的所有数据元素执行的操作。相反，第二组指令中的每个指令指定仅对存储在一个或多个指定寄存器中的数据元素的子集执行的操作。部分宽度执行单元被配置为执行由第一或第二组指令指定的操作。

3. 发明申请

US20130290756A1 Power Management For A System On A Chip (SoC) 有权
标题翻译：片上系统电源管理（SoC）
公开(公告)号：US20130290756A1
公开(公告)日：2013-10-31
申请号：US13925999
申请日：2013-06-25
申请人： Woojong Han , Madhu Athreya , Ken Shoemaker , Arvind Mandhani , Mahesh Wagh , Ticky Thakkar
发明人： Woojong Han , Madhu Athreya , Ken Shoemaker , Arvind Mandhani , Mahesh Wagh , Ticky Thakkar
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/3243 , Y02D10/152
摘要： In one embodiment, the present invention includes a method for sending a first link handshake signal between a first subsystem and a power management unit (PMU) of a system on a chip (SoC) to request entry into a power saving state for the first subsystem, sending a second link handshake signal between the first subsystem and the PMU to acknowledge the request, and placing the first subsystem into the power saving state without further signaling between the PMU and the first subsystem. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于在芯片上的系统（SoC）的第一子系统和功率管理单元（PMU）之间发送第一链路握手信号以请求进入第一子系统的省电状态的方法在所述第一子系统和所述PMU之间发送第二链路握手信号以确认所述请求，以及将所述第一子系统置于省电状态，而不在所述PMU与所述第一子系统之间进一步发信号。描述和要求保护其他实施例。

4. 发明授权

US08510580B2 Power management for a system on a chip (SoC) 有权
公开(公告)号：US08510580B2
公开(公告)日：2013-08-13
申请号：US13611930
申请日：2012-09-12
申请人： Woojong Han , Madhu Athreya , Ken Shoemaker , Arvind Mandhani , Mahesh Wagh , Ticky Thakkar
发明人： Woojong Han , Madhu Athreya , Ken Shoemaker , Arvind Mandhani , Mahesh Wagh , Ticky Thakkar
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/3243 , Y02D10/152
摘要： In one embodiment, the present invention includes a method for sending a first link handshake signal between a first subsystem and a power management unit (PMU) of a system on a chip (SoC) to request entry into a power saving state for the first subsystem, sending a second link handshake signal between the first subsystem and the PMU to acknowledge the request, and placing the first subsystem into the power saving state without further signaling between the PMU and the first subsystem. Other embodiments are described and claimed.

5. 发明申请

US20090249098A1 Power management for a system on a chip (SoC) 有权
标题翻译：芯片系统的电源管理（SoC）
公开(公告)号：US20090249098A1
公开(公告)日：2009-10-01
申请号：US12079185
申请日：2008-03-25
申请人： Woojong Han , Madhu Athreya , Ken Shoemaker , Arvind Mandhani , Mahesh Wagh , Ticky Thakkar
发明人： Woojong Han , Madhu Athreya , Ken Shoemaker , Arvind Mandhani , Mahesh Wagh , Ticky Thakkar
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/3243 , Y02D10/152
摘要： In one embodiment, the present invention includes a method for sending a first link handshake signal between a first subsystem and a power management unit (PMU) of a system on a chip (SoC) to request entry into a power saving state for the first subsystem, sending a second link handshake signal between the first subsystem and the PMU to acknowledge the request, and placing the first subsystem into the power saving state without further signaling between the PMU and the first subsystem. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于在芯片上的系统（SoC）的第一子系统和功率管理单元（PMU）之间发送第一链路握手信号以请求进入第一子系统的省电状态的方法在所述第一子系统和所述PMU之间发送第二链路握手信号以确认所述请求，以及将所述第一子系统置于省电状态，而不在所述PMU与所述第一子系统之间进一步发信号。描述和要求保护其他实施例。

6. 发明申请

US20130061077A1 Power Management For A System On A Chip (SoC) 有权
公开(公告)号：US20130061077A1
公开(公告)日：2013-03-07
申请号：US13611930
申请日：2012-09-12
申请人： Woojong Han , Madhu Athreya , Ken Shoemaker , Arvind Mandhani , Mahesh Wagh , Ticky Thakkar
发明人： Woojong Han , Madhu Athreya , Ken Shoemaker , Arvind Mandhani , Mahesh Wagh , Ticky Thakkar
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/3243 , Y02D10/152
摘要： In one embodiment, the present invention includes a method for sending a first link handshake signal between a first subsystem and a power management unit (PMU) of a system on a chip (SoC) to request entry into a power saving state for the first subsystem, sending a second link handshake signal between the first subsystem and the PMU to acknowledge the request, and placing the first subsystem into the power saving state without further signaling between the PMU and the first subsystem. Other embodiments are described and claimed.

7. 发明授权

US08781641B2 Method and apparatus for external processor thermal control 有权
标题翻译：外部处理器热控制的方法和装置
公开(公告)号：US08781641B2
公开(公告)日：2014-07-15
申请号：US12980648
申请日：2010-12-29
申请人： Eric C. Samson , John William Horigan , Robert T. Jackson , Ticky Thakkar
发明人： Eric C. Samson , John William Horigan , Robert T. Jackson , Ticky Thakkar
IPC分类号： G05D23/00
CPC分类号： G06F1/206
摘要： A system and method for throttling a slave component of a computer system to reduce an overall temperature of the computing system upon receiving a first signal is disclosed. The first signal may be from a master component indicating that a temperature for the master component has exceeded its threshold temperature. The slave component may send a second signal to indicate that a temperature for the slave component has exceeded its temperature. The master component would then initiate throttling of the master component to reduce the overall temperature of the computing system. The master component may be throttled to a degree less than the slave component. A first component may be designated the master component and the second component may be designated the slave component based on a selection policy.
摘要翻译：公开了一种用于节流计算机系统的从属组件以在接收到第一信号时降低计算系统的总体温度的系统和方法。第一信号可以来自主组件，指示主组件的温度已经超过其阈值温度。从组件可以发送第二信号以指示从组件的温度已超过其温度。然后，主组件将启动主组件的节流以降低计算系统的整体温度。主部件可以被节流到比从属部件小的程度。可以将第一组件指定为主组件，并且可以基于选择策略将第二组件指定为从组件。

8. 发明授权

US08286014B2 Power management for a system on a chip (SoC) 有权
标题翻译：芯片系统的电源管理（SoC）
公开(公告)号：US08286014B2
公开(公告)日：2012-10-09
申请号：US12079185
申请日：2008-03-25
申请人： Woojong Han , Madhu Athreya , Ken Shoemaker , Arvind Mandhani , Mahesh Wagh , Ticky Thakkar
发明人： Woojong Han , Madhu Athreya , Ken Shoemaker , Arvind Mandhani , Mahesh Wagh , Ticky Thakkar
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/3243 , Y02D10/152
摘要： In one embodiment, the present invention includes a method for sending a first link handshake signal between a first subsystem and a power management unit (PMU) of a system on a chip (SoC) to request entry into a power saving state for the first subsystem, sending a second link handshake signal between the first subsystem and the PMU to acknowledge the request, and placing the first subsystem into the power saving state without further signaling between the PMU and the first subsystem. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于在芯片上的系统（SoC）的第一子系统和功率管理单元（PMU）之间发送第一链路握手信号以请求进入第一子系统的省电状态的方法在所述第一子系统和所述PMU之间发送第二链路握手信号以确认所述请求，以及将所述第一子系统置于省电状态，而不在所述PMU与所述第一子系统之间进一步发信号。描述和要求保护其他实施例。

9. 发明授权

US6122725A Executing partial-width packed data instructions 失效
标题翻译：执行部分宽度打包的数据指令
公开(公告)号：US6122725A
公开(公告)日：2000-09-19
申请号：US53002
申请日：1998-03-31
申请人： Patrice Roussel , Ticky Thakkar , Mohammad A. Abdallah , Vladimir Pentkovski , James Coke
发明人： Patrice Roussel , Ticky Thakkar , Mohammad A. Abdallah , Vladimir Pentkovski , James Coke
IPC分类号： G06F9/30 , G06F9/302 , G06F9/318 , G06F9/38
CPC分类号： G06F9/3822 , G06F9/30014 , G06F9/30036 , G06F9/30109 , G06F9/3013 , G06F9/30145 , G06F9/30181 , G06F9/30185 , G06F9/30196
摘要： A method and apparatus are provided for executing scalar packed data instructions. According to one aspect of the invention, a processor includes a plurality of registers, a register renaming unit coupled to the plurality of registers, and a decoder coupled to the register renaming unit. The register renaming unit provides an architectural register file to store packed data operands each of which include a plurality of data elements. The decoder is configured to decode a first and second set of instructions (e.g., a set of full-width packed data instructions and a set of partial-width packed data instructions) that each specify one or more registers in the architectural register file. Each of the instructions in the first set of instructions specify operations to be performed on all of the data elements stored in the one or more specified registers. In contrast, each of the instructions in the second set of instructions specify operations to be performed on only a subset of the data element stored in the one or more specified registers.
摘要翻译：提供了一种用于执行标量打包数据指令的方法和装置。根据本发明的一个方面，处理器包括多个寄存器，耦合到多个寄存器的寄存器重命名单元和耦合到寄存器重命名单元的解码器。寄存器重命名单元提供架构寄存器文件以存储打包数据操作数，每个数据操作数包括多个数据元素。解码器被配置为对构造寄存器文件中的每个指定一个或多个寄存器的第一和第二组指令（例如，一组全宽度压缩数据指令和一组部分宽度压缩数据指令）进行解码。第一组指令中的每个指令指定要对存储在一个或多个指定寄存器中的所有数据元素执行的操作。相反，第二组指令中的每个指令指定仅对存储在一个或多个指定寄存器中的数据元素的子集执行的操作。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式