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    • 2. 发明授权
    • Interrupt disabling apparatus, system, and method
    • 中断禁用装置,系统和方法
    • US06823414B2
    • 2004-11-23
    • US10087382
    • 2002-03-01
    • Hiremane S. Radhakrishna
    • Hiremane S. Radhakrishna
    • G06F1324
    • G06F13/24
    • An interrupt processing apparatus, system, and article including a machine-accessible medium, along with a method of processing interrupts, optimize interrupt-handling by combining the activities of acknowledging and disabling the interrupt. In one embodiment, the apparatus may include an interrupt cause register coupled to an interrupt disabling register and an interrupt mask register. The system may include a processor coupled to an interrupt cause register using a bus, along with an interrupt disabling register coupled to an interrupt mask register and the interrupt disabling register. The method may include reading an interrupt cause register in response to receiving an interrupt, and transferring a mask value stored in an interrupt disabling register directly to an interrupt mask register so as to disable receiving further interrupts from the interrupt source.
    • 包括机器可访问介质的中断处理装置,系统和物品以及处理中断的方法通过组合确认和禁用中断的活动来优化中断处理。 在一个实施例中,该装置可以包括耦合到中断禁用寄存器和中断屏蔽寄存器的中断引起寄存器。 该系统可以包括使用总线耦合到中断引起寄存器的处理器,以及耦合到中断屏蔽寄存器和中断禁止寄存器的中断禁止寄存器。 该方法可以包括响应于接收到中断而读取中断原因寄存器,并将存储在中断禁用寄存器中的掩码值直接传送到中断屏蔽寄存器,以便禁止从中断源接收进一步的中断。