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1. 发明授权

US06496890B1 Bus hang prevention and recovery for data communication systems employing a shared bus interface with multiple bus masters 有权
标题翻译：采用与多个总线主机的共享总线接口的数据通信系统的总线挂起预防和恢复
公开(公告)号：US06496890B1
公开(公告)日：2002-12-17
申请号：US09454681
申请日：1999-12-03
申请人： Michael Joseph Azevedo , Brent Cameron Beardsley , Bitwoded Okbay , Carol Spanel , Andrew Dale Walls
发明人： Michael Joseph Azevedo , Brent Cameron Beardsley , Bitwoded Okbay , Carol Spanel , Andrew Dale Walls
IPC分类号： G06F1300
CPC分类号： G06F13/4036 , G06F13/28
摘要： A shared bus hang prevention and recovery scheme for a data communication system is provided, where a shared bus is connected to a plurality of bus masters and corresponding slaves and located between an external bus connected to a system processor, and an internal bus connected to an internal processor. Some of the masters are associated with the external bus and others are associated with the internal bus, and one of the bus masters is a control master associated with the internal processor. The scheme utilizes a shared bus hang prevention and recovery device having a circuitry and a control code. The circuitry is timing each pending request of the control master for the shared bus and initiating bus recovery if the shared bus is hung up, when the control master exceeded a pre-determined time period allowed for waiting to acquire the shared bus control and complete the transfer on the shared bus. The control code is used for monitoring and controlling the circuitry and terminating the transfer in progress causing the shared bus hang-up. During the bus recovery the circuitry prevents bus request grants to the master attached to the external bus until the master subsequent reset, and the control program instructions initiates transfers for all pending requests for the shared bus from the control master queue. Each transfer is being timed and terminated if the shared bus is hung up again. Upon the control master queue clearing, the internal processor executes the control program instructions to reset and reinitialize all masters and slaves on the shared bus.
摘要翻译：提供了一种用于数据通信系统的共享总线挂起预防和恢复方案，其中共享总线连接到多个总线主机和相应的从站，并且位于连接到系统处理器的外部总线与连接到系统处理器的内部总线之间内部处理器一些主机与外部总线相关，其他主机与内部总线相关，其中一个总线主机是与内部处理器相关的控制主机。该方案利用具有电路和控制码的共享总线挂起防止和恢复装置。如果控制主机超过了允许等待获取共享总线控制的预定时间段并且完成了共享总线控制并且完成在共享总线上传输。控制代码用于监视和控制电路，并终止正在进行的传输，从而导致共享总线挂断。在总线恢复期间，电路阻止对连接到外部总线的主机的总线请求授权，直到主机后续复位，并且控制程序指令从控制主机队列开始对所有未决请求的共享总线的传输。如果共享总线再次挂起，则每次传输都将被定时和终止。当控制主队列清除时，内部处理器执行控制程序指令，以复位和重新初始化共享总线上的所有主机和从机。

2. 发明授权

US06606677B1 High speed interrupt controller 失效
标题翻译：高速中断控制器
公开(公告)号：US06606677B1
公开(公告)日：2003-08-12
申请号：US09520876
申请日：2000-03-07
申请人： Bitwoded Okbay , Andrew Dale Walls , Michael Joseph Azevedo
发明人： Bitwoded Okbay , Andrew Dale Walls , Michael Joseph Azevedo
IPC分类号： G06F1324
CPC分类号： G06F13/24
摘要： A high speed interrupt controller and interrupt discrimination scheme for a data communication system is provided, usable in a subsystem of a data communication system. The controller and its scheme may be used for expanding the number of interrupts to be efficiently received and discriminated by a processor having a limited number of interrupt input lines. The present invention can be used for optimizing the management of data within a shared bus with multiple masters, wherein a shared bus is connected to a plurality of bus masters and corresponding slaves and located between an external bus connected to a system processor, and an internal bus connected to an internal processor. The architecture utilizes the high speed interrupt controller device having a circuitry which has a plurality of interrupt lines and may have one output line and a control code, located in the device interrupt handler. The circuitry consists of a status register where an appropriate bit is set when an interrupt is received from an external interrupt source device, and an interrupt mask register which enables and disables certain interrupts. The control code is used for monitoring and controlling the circuitry and servicing the interrupts received by the processor.
摘要翻译：提供了一种用于数据通信系统的高速中断控制器和中断识别方案，可用于数据通信系统的子系统。控制器及其方案可以用于扩展有效接收和鉴别具有有限数量的中断输入线的处理器的中断数量。本发明可用于优化具有多个主机的共享总线内的数据管理，其中共享总线连接到多个总线主机和对应的从机，并且位于连接到系统处理器的外部总线与内部总线连接到内部处理器。该架构利用具有多个中断线的电路的高速中断控制器装置，并且可以具有位于设备中断处理器中的一个输出线和控制代码。该电路由一个状态寄存器组成，当外部中断源设备接收到一个中断时，该位置位适当位，中断屏蔽寄存器使能和禁止某些中断。控制代码用于监控和控制电路并为处理器接收的中断服务。

3. 发明授权

US07284153B2 Apparatus, method, and system for logging diagnostic information 有权
标题翻译：用于记录诊断信息的装置，方法和系统
公开(公告)号：US07284153B2
公开(公告)日：2007-10-16
申请号：US10715266
申请日：2003-11-17
申请人： Bitwoded Okbay , Carol Spanel , Andrew Dale Walls
发明人： Bitwoded Okbay , Carol Spanel , Andrew Dale Walls
IPC分类号： G06F11/00
CPC分类号： G06F11/3636 , G06F11/364
摘要： A diagnostic tracing logger is presented for use in a multithread environment in which diagnostic trace log entries are captured and recorded. The trace logs are composed of sequences of memory addresses used to access instructions and operands, instruction op-codes and register specifiers, sequences of memory addresses, branch instructions or exceptions, the contents of registers or semiconductor memory locations, and the like. In one embodiment, a software module configures a plurality of buffers to capture bus traces, each trace triggered by a specific pattern. A buffer controller manages transfer of diagnostic trace information from the plurality of buffers to a diagnostic log without using processor memory cycles. The trace information is transferred to a selected buffer using a processor cache flush instruction. Diagnostic trace logging facilitates diagnosis of complex system and software interactions without the cost and overhead of prior art trace logging techniques.
摘要翻译：呈现诊断跟踪记录器，用于在其中捕获和记录诊断跟踪日志条目的多线程环境中使用。跟踪日志由用于访问指令和操作数，指令操作码和寄存器说明符，存储器地址序列，分支指令或异常，寄存器或半导体存储器位置的内容等的存储器地址的序列组成。在一个实施例中，软件模块配置多个缓冲器以捕获总线迹线，每个跟踪由特定模式触发。缓冲器控制器管理诊断跟踪信息从多个缓冲器到诊断日志的传送，而不使用处理器存储器周期。使用处理器高速缓存刷新指令将跟踪信息传输到选定的缓冲区。诊断跟踪记录便于诊断复杂的系统和软件交互，而不需要现有技术跟踪记录技术的成本和开销。

4. 发明申请

US20050015664A1 Apparatus, system, and method for managing errors in prefetched data 有权
标题翻译：用于管理预取数据中的错误的装置，系统和方法
公开(公告)号：US20050015664A1
公开(公告)日：2005-01-20
申请号：US10619816
申请日：2003-07-14
申请人： Mark Johnson , Bitwoded Okbay , Andrew Moy , Lih-Chung Kuo
发明人： Mark Johnson , Bitwoded Okbay , Andrew Moy , Lih-Chung Kuo
IPC分类号： G06F11/00 , G06F11/10
CPC分类号： G06F11/1008
摘要： An apparatus, system, and method are provided for managing errors in prefetched data. The apparatus, system, and method identify prefetched data that contains an uncorrectable error. In addition, the apparatus, system, and method initiate an error recovery process only for prefetched data that is actually used by a requesting device, module, or application. The apparatus includes a prefetch module that prefetches data packets, a validation module that determines whether a prefetched data packet contains an uncorrectable error, a transfer module that transfers prefetched data packets to a requester, and an error recovery module that selectively initiates error recovery for those data packets that contain an uncorrectable error and are actually transferred to the requester.
摘要翻译：提供了一种用于管理预取数据中的错误的装置，系统和方法。装置，系统和方法识别包含不可校正错误的预取数据。此外，装置，系统和方法仅针对由请求的设备，模块或应用实际使用的预取数据启动错误恢复过程。该装置包括预取数据分组的预取模块，确定预取数据分组是否包含不可校正错误的确认模块，将预取数据分组传送到请求者的传输模块，以及为那些选择性地启动错误恢复的错误恢复模块数据包包含不可纠正的错误，实际上传输到请求者。

5. 发明授权

US07437593B2 Apparatus, system, and method for managing errors in prefetched data 有权
标题翻译：用于管理预取数据中的错误的装置，系统和方法
公开(公告)号：US07437593B2
公开(公告)日：2008-10-14
申请号：US10619816
申请日：2003-07-14
申请人： Mark C. Johnson , Bitwoded Okbay , Andrew Moy , Lih-Chung Kuo
发明人： Mark C. Johnson , Bitwoded Okbay , Andrew Moy , Lih-Chung Kuo
IPC分类号： G06F11/00
CPC分类号： G06F11/1008
摘要： An apparatus, system, and method are provided for managing errors in prefetched data. The apparatus, system, and method identify prefetched data that contains an uncorrectable error. In addition, the apparatus, system, and method initiate an error recovery process only for prefetched data that is actually used by a requesting device, module, or application. The apparatus includes a prefetch module that prefetches data packets, a validation module that determines whether a prefetched data packet contains an uncorrectable error, a transfer module that transfers prefetched data packets to a requester, and an error recovery module that selectively initiates error recovery for those data packets that contain an uncorrectable error and are actually transferred to the requester.
摘要翻译：提供了一种用于管理预取数据中的错误的装置，系统和方法。装置，系统和方法识别包含不可校正错误的预取数据。此外，装置，系统和方法仅针对由请求的设备，模块或应用实际使用的预取数据启动错误恢复过程。该装置包括预取数据分组的预取模块，确定预取数据分组是否包含不可校正错误的确认模块，将预取数据分组传送到请求者的传输模块，以及为那些选择性地启动错误恢复的错误恢复模块数据包包含不可纠正的错误，实际上传输到请求者。

6. 发明申请

US20050138471A1 Apparatus, method, and system for logging diagnostic information 有权
标题翻译：用于记录诊断信息的装置，方法和系统
公开(公告)号：US20050138471A1
公开(公告)日：2005-06-23
申请号：US10715266
申请日：2003-11-17
申请人： Bitwoded Okbay , Carol Spanel , Andrew Walls
发明人： Bitwoded Okbay , Carol Spanel , Andrew Walls
IPC分类号： G06F11/00
CPC分类号： G06F11/3636 , G06F11/364
摘要： A diagnostic tracing logger is presented for use in a multithread environment in which diagnostic trace log entries are captured and recorded. The trace logs are composed of sequences of memory addresses used to access instructions and operands, instruction op-codes and register specifiers, sequences of memory addresses, branch instructions or exceptions, the contents of registers or semiconductor memory locations, and the like. In one embodiment, a software module configures a plurality of buffers to capture bus traces, each trace triggered by a specific pattern. A buffer controller manages transfer of diagnostic trace information from the plurality of buffers to a diagnostic log without using processor memory cycles. The trace information is transferred to a selected buffer using a processor cache flush instruction. Diagnostic trace logging facilitates diagnosis of complex system and software interactions without the cost and overhead of prior art trace logging techniques.
摘要翻译：呈现诊断跟踪记录器，用于在其中捕获和记录诊断跟踪日志条目的多线程环境中使用。跟踪日志由用于访问指令和操作数，指令操作码和寄存器说明符，存储器地址序列，分支指令或异常，寄存器或半导体存储器位置的内容等的存储器地址的序列组成。在一个实施例中，软件模块配置多个缓冲器以捕获总线迹线，每个跟踪由特定模式触发。缓冲器控制器管理诊断跟踪信息从多个缓冲器到诊断日志的传送，而不使用处理器存储器周期。使用处理器高速缓存刷新指令将跟踪信息传输到选定的缓冲区。诊断跟踪记录便于诊断复杂的系统和软件交互，而不需要现有技术跟踪记录技术的成本和开销。

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