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1. 发明专利

MX9604648A APARATO DE PROCESAMIENTO DE INFORMACION CON FUNCION DE COMPROBACION DE SEGURIDAD. 未知
公开(公告)号：MX9604648A
公开(公告)日：1997-09-30
申请号：MX9604648
申请日：1996-02-07
申请人： SEGA ENTERPRISES KK
发明人： OWAKI HIDETAKA , NAGASHIMA TAKESHI , KAGEYAMA YUKITOSHI
IPC分类号： G06F1/00 , G06F21/10 , G06F21/12 , G06F09/06 , G06F12/14
摘要： Un aparato de procesamiento de informacion tiene una funcion de comprobacion de seguridad para determinar la autenticidad de un programa que se va a ejecutar, y los datos de programa y de visualizacion o presentacion en pantalla se almacenan en un dispositivo de almacenamiento externo. El aparato de procesamiento de informacion, que tiene una CPU para ejecutar un programa, se conecta al dispositivo de almacenamiento externo y a un dispositivo de pantalla para presentar los datos de visualizacion. Durante la ejecucion del programa, los datos de visualizacion almacenados en el dispositivo de almacenamiento externo se presentan en el dispositivo de pantalla en consonancia con ese programa. Los datos de visualizacion se comparan con datos de referencia de comparacion que se almacenan en el aparato de procesamiento de informacion. Cuando los dos conjuntos de datos no coinciden, se detiene el funcionamiento de la CPU del aparato de procesamiento de informacion y se evita que se siga ejecutando el programa.

2. 发明公开

EP0025952A3 Circuit arrangement for a microcomputer 失效
标题翻译：微电脑的电路布置
公开(公告)号：EP0025952A3
公开(公告)日：1982-04-07
申请号：EP80105471
申请日：1980-09-12
申请人： Siemens Aktiengesellschaft
发明人： Schlang, Manfred, Dipl.-Ing.
IPC分类号： G06F13/00 , G06F09/06
CPC分类号： G06F9/3017 , G06F9/45504

3. 发明公开

EP0014581A3 Addressing system for and methods of addressing memories in computer systems 失效
标题翻译：在计算机系统中寻址记忆系统和寻址方法
公开(公告)号：EP0014581A3
公开(公告)日：1981-05-06
申请号：EP80300324
申请日：1980-02-04
申请人： Fanuc Ltd
发明人： Kurakake, Mitsuo
IPC分类号： G06F13/00 , G06F15/16 , G06F09/06 , G11C08/00
CPC分类号： G06F12/0284
摘要： A computer system has a processing units (CPU1 to CPU3), with independent address buses (BUS1 to BUS3), and memories (MEM1 to MEM4) each connectible to any of the address buses (BUS1 to BUS3). The addressing system provides each processing unit (CPU1 to CPU3) with an address modification register (REG1 to REG3) and an adder (AD1 to AD3). The adder (AD1, AD2 or AD3) adds the content (an address modification number) of the address modification register (REG1, REG2, or REG3) to an address output from the processing unit (CPU1, CPU2 or CPU3) to provide an added address which is used for memory addressing. This addressing system, and the method of addressing memories using stored address modification numbers which are added to addresses output from processing units, provides that independently of the allocation of memory space to a processing unit, the lead address of the memory space used by the unit can have, from the point of view of the processor, a zero (first) address.
摘要翻译：计算机系统具有处理单元（CPU1至CPU3），具有独立的地址总线（BUS1至BUS3）以及每个可连接到任何地址总线（BUS1至BUS3）的存储器（MEM1至MEM4）。寻址系统为每个处理单元（CPU1至CPU3）提供地址修改寄存器（REG1至REG3）和加法器（AD1至AD3）。加法器（AD1，AD2或AD3）将地址修改寄存器（REG1，REG2或REG3）的内容（地址修改号）添加到从处理单元（CPU1，CPU2或CPU3）输出的地址，用于存储器寻址的地址。 ...这种寻址系统以及使用存储的地址修改号码寻址存储器的方法，这些存储地址修改号码被添加到从处理单元输出的地址上，提供了独立于处理单元的存储器空间的分配，存储器的引导地址从处理器的角度来说，该单元使用的空间可以具有零（第一）地址。

4. 发明公开

EP0017666A3 Method of operating direct access storage means 失效
标题翻译：操作直接访问存储方法
公开(公告)号：EP0017666A3
公开(公告)日：1981-01-07
申请号：EP79105066
申请日：1979-12-10
申请人： International Business Machines Corporation
发明人： Malaccorto, Alexander Edward , Hunter, Paul Wayne
IPC分类号： G06F13/04 , G06F09/06
CPC分类号： G06F3/0601 , G06F13/126 , G06F2003/0697
摘要： A method is disclosed of operating a direct access storage device (DASD) forming part of a data processing system comprising a central processing unit (CPU) communicating with the DAS device through a channel and a DASD control device. In performing the method a command issued to the DAS subsystem which requires mechanical motion in the DAS device is stored in the subsystem and the subsystem provides a response to the channel indicating that the command has been carried out, without actually carrying out the command. The channel responds by issuing one or more additional commands in the chain to the subsystem which may be carried out without mechanical motion. When a command is issued to the subsystem which again requires mechanical motion of the device, the control device causes the stored command to be executed essentially simultaneously with the newly received command. This execution of the stored command out of its normal sequence and in parallel with another command involving mechanical motion of the DAS device decreases the time required to perform operations with the DASD subsystem.

5. 发明公开

EP0013291A3 Instruction fetch control system in a computer and method for controlling the computer 失效
标题翻译：计算机中的指令FETCH控制系统和用于控制计算机的方法
公开(公告)号：EP0013291A3
公开(公告)日：1980-10-01
申请号：EP79103615
申请日：1979-09-24
申请人： International Business Machines Corporation
发明人： Berglund, Neil Clair , Crowley, Richard Douglas , Kempke, William George , Richardson, William Cain
IPC分类号： G06F09/06 , G06F13/00
CPC分类号： G06F9/3017 , G06F9/268 , G06F9/30145 , G06F9/30181
摘要： An I-fetch control system for a computer includes a control store (30) for storing end op, 1-1, I-2 and return words. A microinstruction decode and control unit (170) responds to end op words to initialize and personalize computer components to facilitate subsequent execution of a high level instruction. The control unit (170), in conjunction with a next address logic (162), selects the next micro-instruction to be executed in response to a high level instruction. The control unit (170) and logic (162) are responsive to 1-1 words to personalize the computer and to select a microinstruction to begin E-phase of a high level instruction. In response to 1-2 control words, the control unit (170) and logic (162) select an operand fetch routine in the control store (30), and write a first E-phase address into a local store (138). The return word gates the first E-phase address from the local store (138) to select a microinstruction in the control store (30) to being E-phase.

6. 发明申请

WO1998027484A1 INSTALLATION METHOD AND INSTALLATION SYSTEM FOR COMPUTER PROGRAM 审中-公开
标题翻译：计算机程序的安装方法和安装系统
公开(公告)号：WO1998027484A1
公开(公告)日：1998-06-25
申请号：PCT/JP1997004674
申请日：1997-12-18
申请人： JAPAN AIRLINES CO., LTD. , SANA, Keishi , ICHIOKA, Hiroyuki
发明人： JAPAN AIRLINES CO., LTD.
IPC分类号： G06F09/06
CPC分类号： G06F8/61
摘要： A method by which a program can be efficiently installed on a computer in a system in which a number of computers with different configurations are used, in an environment in which a number of computers are connected to each other with a network or in an environment in which both independent computers and computers connected to a network exist is provided. Data necessary for a specified processing which is required in accordance with the environment of the computer on which the program is to be installed are read out of a parameter file and the data read out of the parameter file are calculated as a formula interpretation function which is expressed by a formula including the function and, if the function is actually included in the formula of the formula interpretation function, the function included in the formula interpretation function is executed and the required processing is performed in accordance with the result of the execution. By the required processing, the program is installed so as to be adapted to the environment of the computer on which the program is to be installed.
摘要翻译：在多个计算机通过网络或环境彼此连接的环境中，可以在其中使用具有不同配置的计算机的系统中的计算机上有效地安装程序的方法提供独立计算机和连接到网络的计算机。从参数文件中读出根据要安装程序的计算机的环境所需的指定处理所需的数据，并将从参数文件中读出的数据计算为公式解释函数，该解释函数为由包括该函数的公式表示，并且如果函数实际上包括在公式解释函数的公式中，则执行包括在公式解释函数中的函数，并且根据执行结果执行所需的处理。通过所需的处理，安装程序以适应于要安装该程序的计算机的环境。

7. 发明申请

WO1996018944A1 ASSEMBLY TYPE SOFTWARE DESIGN PROCESSING APPARATUS 审中-公开
标题翻译：组装型软件设计处理设备
公开(公告)号：WO1996018944A1
公开(公告)日：1996-06-20
申请号：PCT/KR1995000161
申请日：1995-12-13
申请人： YOO, Hong, Jun
IPC分类号： G06F09/06
CPC分类号： G06F8/20
摘要： An assembly type software design component, an assembly type software design processing apparatus and a software design processing method using the apparatus. Software design processing involves abstraction, disassembly, handling, transmission, conversion and other processings of assembly of standardized components, and development of software and their maintenance and inspection can be carried out easily.
摘要翻译：组装式软件设计组件，组装式软件设计处理装置和使用该装置的软件设计处理方法。软件设计处理涉及标准化组件的组装抽象，拆卸，处理，传输，转换和其他处理，软件开发及其维护和检查可以轻松进行。

8. 发明申请

WO1996002033A1 METHOD OF WRITING PROGRAM FOR SPECIFIC BUSINESS 审中-公开
标题翻译：编写具体业务方案
公开(公告)号：WO1996002033A1
公开(公告)日：1996-01-25
申请号：PCT/JP1995001391
申请日：1995-07-12
申请人： JR EAST JAPAN INFORMATION SYSTEMS CO., LTD. , INSTITUTE OF SOFTWARE SCIENTIFICAL CONSTRUCTIONS CO., LTD. , YUKI, Junichi
发明人： JR EAST JAPAN INFORMATION SYSTEMS CO., LTD. , INSTITUTE OF SOFTWARE SCIENTIFICAL CONSTRUCTIONS CO., LTD.
IPC分类号： G06F09/06
CPC分类号： G06F8/31 , G06F8/30
摘要： This invention provides a method of writing a source program for a specific business devoid of errors irrespective of the skill level of individual engineers. The method comprises the steps of extracting various kinds of definition member items in a business processing system of a specific business; forming a single function program segment (ASL) in association with each definition member item in such a form as to use the corresponding definition member item as a keyword and in such a system that the individual ASLs do not have a mutual control relationship; separately forming a control program (FAL) for organically connecting the ASLs by operating and controlling these groups of ASLs; and operating necessary ASLs by using the arrangement of a plurality of link sentences contained in the FAL so as to combine the FAL and the ASL. To make the individual FALs, a FAL function necessary for the specific business is first extracted from the FAL structure in the maximum state that is generated in advance. Further, FAL and ASL are combined from the link sentence arrangement determined by using the link sentence mesh and its semantics value, so that a source program is obtained.
摘要翻译：本发明提供一种编写不具有错误的特定业务的源程序的方法，而不管个别工程师的技能水平如何。该方法包括在特定业务的业务处理系统中提取各种定义成员项的步骤; 形成与每个定义成员项目相关联的单个功能程序段（ASL），其形式为使用对应的定义成员项作为关键字，并且在这样一个系统中，使各个ASL不具有相互控制关系; 通过操作和控制这些ASL组，分别形成用于有机地连接ASL的控制程序（FAL）; 以及通过使用包含在FAL中的多个链接句子的布置来操作必要的ASL，以便组合FAL和ASL。为了形成单个FAL，首先从预先生成的最大状态的FAL结构中提取特定业务所需的FAL功能。此外，从通过使用链接语句网格确定的链接句子布局及其语义值组合FAL和ASL，从而获得源程序。

9. 发明申请

WO1996001450A1 SECURITY SYSTEM FOR SOFTWARE 审中-公开
标题翻译：软件安全系统
公开(公告)号：WO1996001450A1
公开(公告)日：1996-01-18
申请号：PCT/JP1995001344
申请日：1995-07-05
申请人： KABUSHIKI KAISYA ADVANCE , WATANABE, Shinichirou , KUBAYASHI, Yasutaka
发明人： KABUSHIKI KAISYA ADVANCE
IPC分类号： G06F09/06
CPC分类号： G06F21/10 , G06F21/123 , G06F2211/007 , G06F2221/0737
摘要： A security system for software, which permits only the authorized people to use the software by a simple operation and gives an alarm if the software is found to be infected by a virus. In this system, a software supply portion prepares to supply a program as the supply object to a center portion and to a user portion. The center portion generates a conversion program by applying predetermined conversion to the program supplied thereto, and prepares to supply the converted program to the user portion. The user portion applies a predetermined conversion to the program so as to generate a converted program, compares this converted program with the converted program supplied from the center portion, and executes the program only when both are found coincident as a result of comparison.
摘要翻译：一种用于软件的安全系统，只允许授权人员通过简单的操作使用软件，并发出软件被病毒感染的警报。在该系统中，软件供给部准备向中心部和用户部提供作为供给对象的程序。中心部分通过对提供给其的程序应用预定的转换来产生转换程序，并且准备将转换的程序提供给用户部分。用户部分向程序应用预定的转换，以产生转换的程序，将该转换的程序与从中心部分提供的转换的程序进行比较，并且仅当作为比较的结果发现符合时才执行该程序。

10. 发明申请

WO1998025202A1 COOPERATION OF GLOBAL AND LOCAL REGISTER ALLOCATORS FOR BETTER HANDLING OF BIG PROCEDURES 审中-公开
标题翻译：全球和本地注册分配机构的合作，以更好地处理大型程序
公开(公告)号：WO1998025202A1
公开(公告)日：1998-06-11
申请号：PCT/US1997021378
申请日：1997-11-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： INTERNATIONAL BUSINESS MACHINES CORPORATION , AIZIKOWITZ, Nava, E. , BAR-HAIM, Roy, N. , EDELSTEIN, Orit , PROSSER, Edward, Curtis , ROEDIGER, Robert, Ralph
IPC分类号： G06F09/06
CPC分类号： G06F8/441
摘要： A method and device for optimizing a compiler involves cooperation between the global and local register allocators in assigning symbolic registers (12) to hardware registers (14). A large procedure may have many associated symbolic registers (12); the invention involves partitioning the symbolic registers (12) into at least two portions (10a, 10b, 10c), and allowing the global register allocator to assign one portion and the local register allocator to assign another portion. The registers (12) may be partitioned based on different criteria, such as local vs. global registers, or spill costs, or shallow vs. nested regions.
摘要翻译：一种用于优化编译器的方法和装置涉及在将符号寄存器（12）分配给硬件寄存器（14）之间的全局和本地寄存器分配器之间的协作。一个大的过程可能有许多关联的符号寄存器（12）; 本发明涉及将符号寄存器（12）划分成至少两个部分（10a，10b，10c），并允许全局寄存器分配器分配一个部分，并且本地寄存器分配器分配另一部分。寄存器（12）可以根据不同的标准进行分区，例如本地对全局寄存器，或溢出成本，或浅对嵌套区域。

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