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1. 发明公开

CN106601737A 半导体装置无效
公开(公告)号：CN106601737A
公开(公告)日：2017-04-26
申请号：CN201610900624.8
申请日：2016-10-17
申请人：台湾积体电路制造股份有限公司
发明人：江国诚 , 蔡庆威 , 王志豪 , 梁英强
IPC分类号： H01L27/088 , H01L29/08
CPC分类号： H01L27/11807 , H01L21/31116 , H01L21/31155 , H01L21/32135 , H01L21/32155 , H01L21/823431 , H01L21/823468 , H01L29/0847 , H01L29/66545 , H01L29/66803 , H01L29/7851 , H01L2027/11853 , H01L2027/11864 , H01L27/0886
摘要：一种半导体装置，包含第一鳍式场效晶体管及第二鳍式场效晶体管。第一鳍式场效晶体管包含第一栅极、第一源极及第一漏极，且具有源极/漏极间的第一距离。第二鳍式场效晶体管包含第二栅极、第二源极及第二漏极，且具有小于第一鳍式场效晶体管源极/漏极间距离的第二距离。在一些实施例中，第一鳍式场效晶体管装置为一种输入/输出装置，而第二鳍式场效晶体管装置为诸如一核心装置的非输入/输出装置。在一些实施例中，第一鳍式场效晶体管源极/漏极之间具有较大的距离，是因为第一鳍式场效晶体管装置的一附加间隔层而第二鳍式场效晶体管装置没有。其功效在于可减少短通道效应。

2. 发明公开

CN108025910A 可编程、自组装的具补丁纳米颗粒以及相关装置、系统和方法无效转让
公开(公告)号：CN108025910A
公开(公告)日：2018-05-11
申请号：CN201680048837.0
申请日：2016-07-21
申请人： DNP123公司
发明人：阿伦·T·桑托斯 , 德雷克·M·莱昂斯
IPC分类号： B82B1/00 , B82Y5/00 , B82Y40/00 , C12P19/34 , C25B9/16
CPC分类号： B81B7/0003 , A61K9/14 , B22F1/0044 , B22F1/0062 , B22F9/24 , B22F2301/255 , B81C1/00007 , B81C1/00126 , B81C2201/0149 , B82Y5/00 , B82Y40/00 , C07H21/04 , C25B9/16 , H01L27/11807 , H01L2027/11853
摘要：本发明一般地涉及纳米制造，并且在一些实施方案中涉及合成选择性结合具补丁纳米颗粒的方法和可由其制成的装置。在一些实施方案中，本发明涉及由具补丁纳米立方体组装任意形状结构的方法以及后续的装置和用途。例如，可如下对纳米立方体构建块打补丁：用选择性结合化学物质(例如，DNA、抗体‑抗原对，等)冲压其表面，或者使用自组装来使可对不相混性预编程的多种选择性结合补丁物质附接于纳米立方体。然后，可通过决定哪些面将在某一目标结构中彼此接合并将在这些面上具有选择性结合补丁的纳米立方体组合来设计和组装任意形状的结构。本发明的另一些方面还涉及制备这样的纳米立方体或其他纳米颗粒的方法、形成这样的纳米立方体的方法。

3. 发明公开

EP3161854A1 TECHNIQUES FOR FORMING A COMPACTED ARRAY OF FUNCTIONAL CELLS 审中-公开
标题翻译：法制造密度泛函单元的排列
公开(公告)号：EP3161854A1
公开(公告)日：2017-05-03
申请号：EP14896073.5
申请日：2014-06-25
申请人： Intel Corporation
发明人： ELSAYED, Rany, T. , GOEL, Niti , BOU-GHAZALE, Silvio, E. , ASKSAMIT, Randy, J.
IPC分类号： H01L21/027 , H01L21/768
CPC分类号： H01L27/0207 , G06F17/5068 , H01L21/0274 , H01L21/0277 , H01L21/823475 , H01L27/11 , H01L27/11807 , H01L29/16 , H01L2027/11853 , H01L2027/11866 , H01L2027/11875 , H03K19/00
摘要： Techniques are disclosed for forming a compacted array of functional cells using next-generation lithography (NGL) processes, such as electron-beam direct write (EBDW) and extreme ultraviolet lithography (EUVL), to form the boundaries of the cells in the array. The compacted array of cells may be used for field-programmable gate array (FPGA) structures configured with logic cells, static random-access memory (SRAM) structures configured with bit cells, or other memory or logic devices having cell-based structures. The techniques can be used to gain a reduction in area of 10 to 50 percent, for example, for the array of functional cells, because the NGL processes allow for higher precision and closer cuts for the cell boundaries, as compared to conventional 193 nm photolithography. In addition, the use of NGL processes to form the boundaries for the cells may also reduce lithography induced variations that would otherwise be present with conventional 193 nm photolithography.
摘要翻译：技术是圆盘游离缺失用于形成使用下一代光刻（NGL）的过程，：例如电子束直写（EBDW）和极紫外光刻（EUVL），以形成所述阵列中的单元的边界功能性细胞的压实的阵列。细胞的压实的阵列可用于现场可编程门阵列（FPGA）与逻辑单元配置的结构，静态随机存取存储器（SRAM）与位单元，或其它存储器或具有基于细胞的结构逻辑器件配置结构。的技术可以用来获得在10面积％至50％的降低，例如，对于功能单元的阵列，因为NGL工艺允许更高的精度和对小区边界更靠近切割，相比于传统的193nm光刻，此外，使用NGL工艺，以形成用于细胞因此可以减少光刻引起的变化，否则也将存在与常规的193nm的光刻法的边界。

4. 发明公开

EP3325402A1 PROGRAMMABLE, SELF-ASSEMBLING PATCHED NANOPARTICLES, AND ASSOCIATED DEVICES, SYSTEMS AND METHODS 审中-公开
公开(公告)号：EP3325402A1
公开(公告)日：2018-05-30
申请号：EP16828523.7
申请日：2016-07-21
申请人： DNP123 Company , Emerge Foundation
发明人： SANTOS, Aaron, T. , LYONS, Derek, M.
IPC分类号： B82B1/00 , B82Y5/00 , B82Y40/00 , C12P19/34 , C25B9/16
CPC分类号： B81B7/0003 , A61K9/14 , B22F1/0044 , B22F1/0062 , B22F9/24 , B22F2301/255 , B81C1/00007 , B81C2201/0149 , B82B3/0047 , B82Y5/00 , B82Y40/00 , C07H21/04 , C25B9/16 , H01L27/11807 , H01L2027/11853
摘要： The present invention generally relates to nanofabrication and, in some embodiments, to methods of synthesizing selectively binding patched nanoparticles and the devices that can be made from them. In some embodiments, the invention relates to methods of assembling arbitrarily shaped structures from patched nanocubes and the devices and uses that follow. For example, nanocube building blocks may be patched by stamping their faces with a selectively binding chemical species (e.g. DNA, antibody-antigen pairs, etc.), or by using self-assembly to attach to the nanocubes multiple selectively binding patch species whose immiscibility can be preprogrammed. Arbitrarily shaped structures can then be designed and assembled by deciding which faces will be bonded to each other in some target structure and combining nanocubes that have selectively binding patches on those faces. Other aspects of the invention are also directed to methods of making such nanocubes or other nanoparticles, methods of forming such nanocubes.

5. 发明公开

EP3161854A4 TECHNIQUES FOR FORMING A COMPACTED ARRAY OF FUNCTIONAL CELLS 审中-公开
公开(公告)号：EP3161854A4
公开(公告)日：2018-05-30
申请号：EP14896073
申请日：2014-06-25
申请人： INTEL CORP
发明人： ELSAYED RANY T , GOEL NITI , BOU-GHAZALE SILVIO E , ASKSAMIT RANDY J
IPC分类号： H01L21/027 , H01L21/768 , H01L27/02 , H01L27/11 , H01L27/118
CPC分类号： H01L27/0207 , G06F17/5068 , H01L21/0274 , H01L21/0277 , H01L21/823475 , H01L27/11 , H01L27/11807 , H01L29/16 , H01L2027/11853 , H01L2027/11866 , H01L2027/11875 , H03K19/00
摘要： Techniques are disclosed for forming a compacted array of functional cells using next-generation lithography (NGL) processes, such as electron-beam direct write (EBDW) and extreme ultraviolet lithography (EUVL), to form the boundaries of the cells in the array. The compacted array of cells may be used for field-programmable gate array (FPGA) structures configured with logic cells, static random-access memory (SRAM) structures configured with bit cells, or other memory or logic devices having cell-based structures. The techniques can be used to gain a reduction in area of 10 to 50 percent, for example, for the array of functional cells, because the NGL processes allow for higher precision and closer cuts for the cell boundaries, as compared to conventional 193 nm photolithography. In addition, the use of NGL processes to form the boundaries for the cells may also reduce lithography induced variations that would otherwise be present with conventional 193 nm photolithography.

6. 发明申请

WO2015199682A1 TECHNIQUES FOR FORMING A COMPACTED ARRAY OF FUNCTIONAL CELLS 审中-公开
标题翻译：形成功能性细胞压制阵列的技术
公开(公告)号：WO2015199682A1
公开(公告)日：2015-12-30
申请号：PCT/US2014/044105
申请日：2014-06-25
申请人： INTEL CORPORATION , ELSAYED, Rany, T. , GOEL, Niti , BOU-GHAZALE, Silvio, E. , ASKSAMIT, Randy, J.
发明人： ELSAYED, Rany, T. , GOEL, Niti , BOU-GHAZALE, Silvio, E. , ASKSAMIT, Randy, J.
IPC分类号： H01L21/027 , H01L21/768
CPC分类号： H01L27/0207 , G06F17/5068 , H01L21/0274 , H01L21/0277 , H01L21/823475 , H01L27/11 , H01L27/11807 , H01L29/16 , H01L2027/11853 , H01L2027/11866 , H01L2027/11875 , H03K19/00
摘要： Techniques are disclosed for forming a compacted array of functional cells using next-generation lithography (NGL) processes, such as electron-beam direct write (EBDW) and extreme ultraviolet lithography (EUVL), to form the boundaries of the cells in the array. The compacted array of cells may be used for field-programmable gate array (FPGA) structures configured with logic cells, static random-access memory (SRAM) structures configured with bit cells, or other memory or logic devices having cell-based structures. The techniques can be used to gain a reduction in area of 10 to 50 percent, for example, for the array of functional cells, because the NGL processes allow for higher precision and closer cuts for the cell boundaries, as compared to conventional 193 nm photolithography. In addition, the use of NGL processes to form the boundaries for the cells may also reduce lithography induced variations that would otherwise be present with conventional 193 nm photolithography.
摘要翻译：公开了用于使用下一代光刻（NGL）工艺（例如电子束直写（EBDW）和极紫外光刻（EUVL））形成功能电池的压实阵列的技术，以形成阵列中的电池的边界。紧凑的单元阵列可以用于配置有逻辑单元，配置有位单元的静态随机存取存储器（SRAM）结构或具有基于单元的结构的其他存储器或逻辑器件的现场可编程门阵列（FPGA）结构。与常规的193nm光刻相比，这些技术可以用于获得10至50％的面积减少，例如对于功能单元阵列，因为NGL工艺允许更高的精度和更小的细胞边界切割。此外，使用NGL工艺来形成单元的边界也可以减少光刻引起的变化，否则将以传统的193nm光刻法存在。

7. 发明专利

JP2011515841A Intersect in a restricted gate level layout architecture coupled transistor layout 有权
公开(公告)号：JP2011515841A
公开(公告)日：2011-05-19
申请号：JP2010550861
申请日：2009-03-12
申请人：テライノヴェイションズインコーポレイテッド
发明人：スコットティーベッカー
IPC分类号： H01L27/11 , H01L21/82 , H01L21/822 , H01L21/8244 , H01L27/04
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , G11C5/06 , G11C11/412 , H01L21/823475 , H01L23/49844 , H01L23/528 , H01L23/5386 , H01L27/0207 , H01L27/0218 , H01L27/088 , H01L27/092 , H01L27/1052 , H01L27/11 , H01L27/1104 , H01L2027/11853 , H01L2027/11875 , H01L2027/11887 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. Each of a number of conductive features within a gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature, with a centerline of each originating rectangular-shaped layout feature aligned in a parallel manner. The conductive features respectively form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. Widths of the first and second p-type diffusion regions are substantially equal, such that the first and second PMOS transistor devices have substantially equal widths. Widths of the first and second n-type diffusion regions are substantially equal, such that the first and second NMOS transistor devices have substantially equal widths. The first and second PMOS and first and second NMOS transistor devices form a cross-coupled transistor configuration.

8. 发明专利

JP5730424B2 制限付きゲートレベルレイアウトアーキテクチャにおける交差結合トランジスタレイアウト有权
标题翻译：在受限门级布局架构耦合的晶体管布局交叉
公开(公告)号：JP5730424B2
公开(公告)日：2015-06-10
申请号：JP2014063612
申请日：2014-03-26
申请人：テライノヴェイションズインコーポレイテッド
发明人：ベッカースコットティー
IPC分类号： H01L27/11 , H01L21/82 , H01L21/822 , H01L27/04 , H01L21/8238 , H01L27/092 , H01L21/8244
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , G11C11/412 , G11C5/06 , H01L21/823475 , H01L23/49844 , H01L23/528 , H01L23/5386 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L27/11 , H01L27/1104 , H01L2027/11853 , H01L2924/0002

9. 发明申请

WO2015199682A8 TECHNIQUES FOR FORMING A COMPACTED ARRAY OF FUNCTIONAL CELLS 审中-公开
标题翻译：形成功能性细胞压制阵列的技术
公开(公告)号：WO2015199682A8
公开(公告)日：2016-03-17
申请号：PCT/US2014044105
申请日：2014-06-25
申请人： INTEL CORP , ELSAYED RANY T , GOEL NITI , BOU-GHAZALE SILVIO E , AKSAMIT RANDY J
发明人： ELSAYED RANY T , GOEL NITI , BOU-GHAZALE SILVIO E , AKSAMIT RANDY J
IPC分类号： H01L21/027 , H01L21/768
CPC分类号： H01L27/0207 , G06F17/5068 , H01L21/0274 , H01L21/0277 , H01L21/823475 , H01L27/11 , H01L27/11807 , H01L29/16 , H01L2027/11853 , H01L2027/11866 , H01L2027/11875 , H03K19/00
摘要： Techniques are disclosed for forming a compacted array of functional cells using next-generation lithography (NGL) processes, such as electron-beam direct write (EBDW) and extreme ultraviolet lithography (EUVL), to form the boundaries of the cells in the array. The compacted array of cells may be used for field-programmable gate array (FPGA) structures configured with logic cells, static random-access memory (SRAM) structures configured with bit cells, or other memory or logic devices having cell-based structures. The techniques can be used to gain a reduction in area of 10 to 50 percent, for example, for the array of functional cells, because the NGL processes allow for higher precision and closer cuts for the cell boundaries, as compared to conventional 193 nm photolithography. In addition, the use of NGL processes to form the boundaries for the cells may also reduce lithography induced variations that would otherwise be present with conventional 193 nm photolithography.
摘要翻译：公开了用于使用下一代光刻（NGL）工艺（例如电子束直写（EBDW）和极紫外光刻（EUVL））形成功能电池的压实阵列的技术，以形成阵列中的电池的边界。紧凑的单元阵列可以用于配置有逻辑单元，配置有位单元的静态随机存取存储器（SRAM）结构或具有基于单元的结构的其他存储器或逻辑器件的现场可编程门阵列（FPGA）结构。与常规的193nm光刻相比，这些技术可以用于获得10至50％的面积减少，例如对于功能单元阵列，因为NGL工艺允许更高的精度和更小的细胞边界切割。此外，使用NGL工艺来形成单元的边界也可以减少光刻引起的变化，否则将以传统的193nm光刻法存在。

10. 发明申请

WO2009114680A2 CROSS-COUPLED TRANSISTOR LAYOUTS IN RESTRICTED GATE LEVEL LAYOUT ARCHITECTURE 审中-公开
标题翻译：限制门级布置架构中的交叉耦合晶体管层
公开(公告)号：WO2009114680A2
公开(公告)日：2009-09-17
申请号：PCT/US2009036937
申请日：2009-03-12
申请人： TELA INNOVATIONS INC , BECKER SCOTT T
发明人： BECKER SCOTT T
IPC分类号： H01L27/105 , H01L21/33 , H01L27/11 , H01L29/78
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , G11C5/06 , G11C11/412 , H01L21/823475 , H01L23/49844 , H01L23/528 , H01L23/5386 , H01L27/0207 , H01L27/0218 , H01L27/088 , H01L27/092 , H01L27/1052 , H01L27/11 , H01L27/1104 , H01L2027/11853 , H01L2027/11875 , H01L2027/11887 , H01L2924/0002 , H01L2924/00
摘要： A first P channel transistor and a first N channel transistor are defined by first and second gate electrodes, respectively. The second gate electrode is electrically connected to the first gate electrode. A second P channel transistor and a second N channel transistor are defined by third and fourth gate electrodes, respectively. The fourth gate electrode is electrically connected to the third gate electrode. Each of the first P channel transistor, first N channel transistor, second P channel transistor, and second N channel transistor has a respective diffusion terminal electrically connected to a common node. Each of the first, second, third, and fourth gate electrodes is defined to extend along any of a number of parallel oriented gate electrode tracks without physically contacting a gate level feature defined within any gate level feature layout channel associated with a gate electrode track adjacent thereto.
摘要翻译：第一P沟道晶体管和第一N沟道晶体管分别由第一和第二栅电极限定。第二栅电极电连接到第一栅电极。第二P沟道晶体管和第二N沟道晶体管分别由第三和第四栅电极限定。第四栅电极与第三栅电极电连接。第一P沟道晶体管，第一N沟道晶体管，第二P沟道晶体管和第二N沟道晶体管中的每一个具有电连接到公共节点的相应扩散端。第一，第二，第三和第四栅电极中的每一个被限定为沿着多个平行取向的栅极电极轨道中的任一个延伸，而不物理地接触在与栅极电极轨道相邻的任何栅极电平特征布局通道中限定的栅极电平特征于此。

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