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1. 发明申请

WO2015199682A1 TECHNIQUES FOR FORMING A COMPACTED ARRAY OF FUNCTIONAL CELLS 审中-公开
标题翻译：形成功能性细胞压制阵列的技术
公开(公告)号：WO2015199682A1
公开(公告)日：2015-12-30
申请号：PCT/US2014/044105
申请日：2014-06-25
申请人： INTEL CORPORATION , ELSAYED, Rany, T. , GOEL, Niti , BOU-GHAZALE, Silvio, E. , ASKSAMIT, Randy, J.
发明人： ELSAYED, Rany, T. , GOEL, Niti , BOU-GHAZALE, Silvio, E. , ASKSAMIT, Randy, J.
IPC分类号： H01L21/027 , H01L21/768
CPC分类号： H01L27/0207 , G06F17/5068 , H01L21/0274 , H01L21/0277 , H01L21/823475 , H01L27/11 , H01L27/11807 , H01L29/16 , H01L2027/11853 , H01L2027/11866 , H01L2027/11875 , H03K19/00
摘要： Techniques are disclosed for forming a compacted array of functional cells using next-generation lithography (NGL) processes, such as electron-beam direct write (EBDW) and extreme ultraviolet lithography (EUVL), to form the boundaries of the cells in the array. The compacted array of cells may be used for field-programmable gate array (FPGA) structures configured with logic cells, static random-access memory (SRAM) structures configured with bit cells, or other memory or logic devices having cell-based structures. The techniques can be used to gain a reduction in area of 10 to 50 percent, for example, for the array of functional cells, because the NGL processes allow for higher precision and closer cuts for the cell boundaries, as compared to conventional 193 nm photolithography. In addition, the use of NGL processes to form the boundaries for the cells may also reduce lithography induced variations that would otherwise be present with conventional 193 nm photolithography.
摘要翻译：公开了用于使用下一代光刻（NGL）工艺（例如电子束直写（EBDW）和极紫外光刻（EUVL））形成功能电池的压实阵列的技术，以形成阵列中的电池的边界。紧凑的单元阵列可以用于配置有逻辑单元，配置有位单元的静态随机存取存储器（SRAM）结构或具有基于单元的结构的其他存储器或逻辑器件的现场可编程门阵列（FPGA）结构。与常规的193nm光刻相比，这些技术可以用于获得10至50％的面积减少，例如对于功能单元阵列，因为NGL工艺允许更高的精度和更小的细胞边界切割。此外，使用NGL工艺来形成单元的边界也可以减少光刻引起的变化，否则将以传统的193nm光刻法存在。

2. 发明申请

WO2015199679A1 TECHNIQUES FOR FORMING INTEGRATED PASSIVE DEVICES 审中-公开
标题翻译：形成集成无源器件的技术
公开(公告)号：WO2015199679A1
公开(公告)日：2015-12-30
申请号：PCT/US2014/044101
申请日：2014-06-25
申请人： INTEL CORPORATION , ELSAYED, Rany, T. , GOEL, Niti , BOU-GHAZALE, Silvio, E. , ROY, Anshumali , YIP, Joseph, C.
发明人： ELSAYED, Rany, T. , GOEL, Niti , BOU-GHAZALE, Silvio, E. , ROY, Anshumali , YIP, Joseph, C.
IPC分类号： H01F17/00 , H01G4/32 , H01F41/04
CPC分类号： H01L23/66 , G03F7/2059 , H01F17/0006 , H01F41/042 , H01G4/012 , H01G4/40 , H01L28/10 , H01L28/60 , H01L2223/6672
摘要： Techniques are disclosed for forming integrated passive devices, such as inductors and capacitors, using next-generation lithography (NGL) processes, such as electron-beam direct write (EBDW) and extreme ultraviolet lithography (EUVL). The techniques can be used to form various different integrated passive devices, such as inductors (e.g., spiral inductors) and capacitors (e.g., metal finger capacitors), having higher density, precision, and quality factor (Q) values than if such devices were formed using 193 nm photolithography. The high Q and dense passive devices formed can be used in radio frequency (RF) and analog circuits to boost the performance of such circuits. The increased precision may be realized based on an improvement in, for example, line edge roughness (LER), achievable resolution/critical dimensions, sharpness of corners, and/or density of the formed structures.
摘要翻译：公开了使用诸如电子束直接写入（EBDW）和极紫外光刻（EUVL）的下一代光刻（NGL）工艺来形成诸如电感器和电容器的集成无源器件的技术。这些技术可以用于形成各种不同的集成无源器件，例如电感器（例如螺旋电感器）和电容器（例如，金属制电容器），其具有比如果这些器件的密度，精度和品质因数（Q）值更高的密度，精度和品质因数使用193nm光刻法形成。形成的高Q和致密无源器件可用于射频（RF）和模拟电路，以提高这种电路的性能。可以基于例如线边缘粗糙度（LER），可实现的分辨率/临界尺寸，拐角的锐度和/或形成的结构的密度的改进来实现提高的精度。

3. 发明申请

WO2016007140A1 TECHNIQUES TO ACHIEVE AREA REDUCTION THROUGH CO-OPTIMIZING LOGIC CORE BLOCKS AND MEMORY REDUNDANCIES 审中-公开
标题翻译：通过优化逻辑核心块和记忆冗余来实现减少面积的技术
公开(公告)号：WO2016007140A1
公开(公告)日：2016-01-14
申请号：PCT/US2014/045779
申请日：2014-07-08
申请人： INTEL CORPORATION , BOU-GHAZALE, Silvio, E. , GHOSH, Abhik , GOEL, Niti
发明人： BOU-GHAZALE, Silvio, E. , GHOSH, Abhik , GOEL, Niti
IPC分类号： G11C29/00 , G11C5/02
CPC分类号： G03F7/705 , G06F11/2041 , G06F17/5068 , G06F17/5081 , G11C5/025 , G11C29/702 , G11C29/814 , G11C29/816 , G11C29/88
摘要： Techniques are disclosed for achieving size reduction of embedded memory arrays through determining a spare-core layout. In an embodiment, input parameters comprising global process parameters are combined with design characteristics to compute yield values corresponding to potential redundancy configurations for a die. Resulting yields may be compared to determine which redundancy configuration is suitable to maintain a particular yield. A die configured with one or more spare cores (with no redundant memory therein) results in a yield which is equivalent to, or exceeds, the yield of a die with conventional memory redundancies. In some example cases, memory redundancy is eliminated from cores. Another embodiment provides a semiconductor structure having including an array of redundant cores, each including a composition of memory arrays and logic structures, wherein at least one of the memory arrays of each redundant core is implemented without at least one of row redundancy and column redundancy.
摘要翻译：公开了通过确定备用核心布局来实现嵌入式存储器阵列的尺寸减小的技术。在一个实施例中，包括全局过程参数的输入参数与设计特征组合以计算对应于芯片的潜在冗余配置的产量值。可以比较产生的产量以确定哪个冗余配置适合于维持特定的产量。配置有一个或多个备用核（其中没有冗余存储器）的管芯产生等于或超过具有常规存储器冗余的管芯的产量的产量。在某些示例情况下，从内核中消除内存冗余。另一实施例提供了一种半导体结构，其包括冗余核心阵列，每个冗余核心包括存储器阵列和逻辑结构的组合，其中每个冗余核心的至少一个存储器阵列被实现为行冗余和列冗余中的至少一个。

4. 发明申请

WO2015199682A8 TECHNIQUES FOR FORMING A COMPACTED ARRAY OF FUNCTIONAL CELLS 审中-公开
标题翻译：形成功能性细胞压制阵列的技术
公开(公告)号：WO2015199682A8
公开(公告)日：2016-03-17
申请号：PCT/US2014044105
申请日：2014-06-25
申请人： INTEL CORP , ELSAYED RANY T , GOEL NITI , BOU-GHAZALE SILVIO E , AKSAMIT RANDY J
发明人： ELSAYED RANY T , GOEL NITI , BOU-GHAZALE SILVIO E , AKSAMIT RANDY J
IPC分类号： H01L21/027 , H01L21/768
CPC分类号： H01L27/0207 , G06F17/5068 , H01L21/0274 , H01L21/0277 , H01L21/823475 , H01L27/11 , H01L27/11807 , H01L29/16 , H01L2027/11853 , H01L2027/11866 , H01L2027/11875 , H03K19/00
摘要： Techniques are disclosed for forming a compacted array of functional cells using next-generation lithography (NGL) processes, such as electron-beam direct write (EBDW) and extreme ultraviolet lithography (EUVL), to form the boundaries of the cells in the array. The compacted array of cells may be used for field-programmable gate array (FPGA) structures configured with logic cells, static random-access memory (SRAM) structures configured with bit cells, or other memory or logic devices having cell-based structures. The techniques can be used to gain a reduction in area of 10 to 50 percent, for example, for the array of functional cells, because the NGL processes allow for higher precision and closer cuts for the cell boundaries, as compared to conventional 193 nm photolithography. In addition, the use of NGL processes to form the boundaries for the cells may also reduce lithography induced variations that would otherwise be present with conventional 193 nm photolithography.
摘要翻译：公开了用于使用下一代光刻（NGL）工艺（例如电子束直写（EBDW）和极紫外光刻（EUVL））形成功能电池的压实阵列的技术，以形成阵列中的电池的边界。紧凑的单元阵列可以用于配置有逻辑单元，配置有位单元的静态随机存取存储器（SRAM）结构或具有基于单元的结构的其他存储器或逻辑器件的现场可编程门阵列（FPGA）结构。与常规的193nm光刻相比，这些技术可以用于获得10至50％的面积减少，例如对于功能单元阵列，因为NGL工艺允许更高的精度和更小的细胞边界切割。此外，使用NGL工艺来形成单元的边界也可以减少光刻引起的变化，否则将以传统的193nm光刻法存在。

5. 发明申请

WO2015199722A1 DECOUPLING CAPACITORS AND ARRANGEMENTS 审中-公开
标题翻译：解除电容器和安排
公开(公告)号：WO2015199722A1
公开(公告)日：2015-12-30
申请号：PCT/US2014/044595
申请日：2014-06-27
申请人： INTEL CORPORATION , BOU-GHAZALE, Silvio E. , ELSAYED, Rany T. , GOEL, Niti
发明人： BOU-GHAZALE, Silvio E. , ELSAYED, Rany T. , GOEL, Niti
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L23/5223 , H01L27/0629 , H01L27/0733 , H01L28/88 , H01L2924/0002 , H01L2924/00
摘要： Various embodiments of transistor assemblies, integrated circuit devices, and related methods are disclosed herein. In some embodiments, a transistor assembly may include a base layer in which a transistor is disposed, a first metal layer, and a second metal layer disposed between the base layer and the first metal layer. The transistor assembly may also include a capacitor, including a sheet of conductive material with a channel therein, disposed in the base layer or the second metal layer and coupled to a supply line of the transistor. Other embodiments may be disclosed and/or claimed.
摘要翻译：本文公开了晶体管组件，集成电路器件和相关方法的各种实施例。在一些实施例中，晶体管组件可以包括其中设置晶体管的基极层，第一金属层和设置在基极层和第一金属层之间的第二金属层。晶体管组件还可以包括电容器，其包括其中具有通道的导电材料片，设置在基极层或第二金属层中并耦合到晶体管的电源线。可以公开和/或要求保护其他实施例。

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