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1. 发明授权

US08595394B1 Method and system for dynamic buffering of disk I/O command chains 有权
标题翻译：磁盘I / O命令链的动态缓冲方法和系统
公开(公告)号：US08595394B1
公开(公告)日：2013-11-26
申请号：US10726151
申请日：2003-12-01
申请人： Radoslav Danilak , Krishnaraj S. Rao
发明人： Radoslav Danilak , Krishnaraj S. Rao
IPC分类号： G06F13/28 , G06F3/00 , G06F5/00
CPC分类号： G06F3/0659 , G06F3/061 , G06F3/0676 , G06F13/385
摘要： A method for dynamic buffering of disk I/O command chains for a computer system. The method includes receiving a plurality of disk I/O command chains from at least one thread executing on a processor of the computer system. A respective plurality of pointers for the disk I/O command chains are stored in a buffer of a disk controller. The disk I/O command chains are accessed for execution by the disk controller by serially accessing the pointers in the buffer.
摘要翻译：一种用于计算机系统的磁盘I / O命令链的动态缓冲的方法。该方法包括从在计算机系统的处理器上执行的至少一个线程接收多个盘I / O命令链。用于磁盘I / O命令链的相应多个指针被存储在磁盘控制器的缓冲器中。磁盘I / O命令链由磁盘控制器通过串行访问缓冲区中的指针进行访问。

2. 发明授权

US08694688B2 Disk controller for implementing efficient disk I/O for a computer system 有权
标题翻译：磁盘控制器，用于实现计算机系统的高效磁盘I / O
公开(公告)号：US08694688B2
公开(公告)日：2014-04-08
申请号：US12005816
申请日：2007-12-28
申请人： Radoslav Danilak , Krishnaraj S. Rao
发明人： Radoslav Danilak , Krishnaraj S. Rao
IPC分类号： G06F3/00 , G06F13/24 , G06F13/22
CPC分类号： G06F3/0659 , G06F3/061 , G06F3/0676 , G06F13/385
摘要： A hardware support system for implementing accelerated disk I/O for a computer system. The system includes a bus interface for interfacing with a processor and a system memory of the computer system, a disk I/O engine coupled to the bus interface, and a device interface coupled to the disk I/O engine for interfacing the disk I/O engine with a disk drive. The disk I/O engine is configured to cause a start up of the disk drive upon receiving a disk start up command from the processor. The disk I/O engine is further configured to execute a disk transaction by processing the disk transaction information from a bypass register coupled to the disk I/O engine.
摘要翻译：用于实现计算机系统的加速磁盘I / O的硬件支持系统。该系统包括用于与计算机系统的处理器和系统存储器接口的总线接口，耦合到总线接口的盘I / O引擎以及耦合到盘I / O引擎的设备接口，用于将盘I / O引擎与磁盘驱动器。磁盘I / O引擎被配置为在从处理器接收到磁盘启动命令时引起磁盘驱动器的启动。磁盘I / O引擎还被配置为通过从耦合到磁盘I / O引擎的旁路寄存器处理磁盘事务信息来执行磁盘事务。

3. 发明授权

US08700808B2 Hardware support system for accelerated disk I/O 有权
标题翻译：用于加速磁盘I / O的硬件支持系统
公开(公告)号：US08700808B2
公开(公告)日：2014-04-15
申请号：US12005745
申请日：2007-12-28
申请人： Radoslav Danilak , Krishnaraj S. Rao
发明人： Radoslav Danilak , Krishnaraj S. Rao
IPC分类号： G06F3/00
CPC分类号： G06F13/385
摘要： A hardware support system for implementing accelerated disk I/O for a computer system. The system includes a bus interface for interfacing with a processor and a system memory of the computer system, a disk I/O engine coupled to the bus interface, and a device interface coupled to the disk I/O engine for interfacing the disk I/O engine with a disk drive. The disk I/O engine is configured to cause a start up of the disk drive upon receiving a disk start up command from the processor. The disk I/O engine is further configured to execute a disk transaction by processing the disk transaction information from a bypass register coupled to the disk I/O engine.
摘要翻译：用于实现计算机系统的加速磁盘I / O的硬件支持系统。该系统包括用于与计算机系统的处理器和系统存储器接口的总线接口，耦合到总线接口的盘I / O引擎以及耦合到盘I / O引擎的设备接口，用于将盘I / O引擎与磁盘驱动器。磁盘I / O引擎被配置为在从处理器接收到磁盘启动命令时引起磁盘驱动器的启动。磁盘I / O引擎还被配置为通过从耦合到磁盘I / O引擎的旁路寄存器处理磁盘事务信息来执行磁盘事务。

4. 发明申请

US20080177914A1 Hardware support system for accelerated disk I/O 有权
标题翻译：用于加速磁盘I / O的硬件支持系统
公开(公告)号：US20080177914A1
公开(公告)日：2008-07-24
申请号：US12005816
申请日：2007-12-28
申请人： Radoslav Danilak , Krishnaraj S. Rao
发明人： Radoslav Danilak , Krishnaraj S. Rao
IPC分类号： G06F13/00
CPC分类号： G06F3/0659 , G06F3/061 , G06F3/0676 , G06F13/385
摘要： A hardware support system for implementing accelerated disk I/O for a computer system. The system includes a bus interface for interfacing with a processor and a system memory of the computer system, a disk I/O engine coupled to the bus interface, and a device interface coupled to the disk I/O engine for interfacing the disk I/O engine with a disk drive. The disk I/O engine is configured to cause a start up of the disk drive upon receiving a disk start up command from the processor. The disk I/O engine is further configured to execute a disk transaction by processing the disk transaction information from a bypass register coupled to the disk I/O engine.
摘要翻译：用于实现计算机系统的加速磁盘I / O的硬件支持系统。该系统包括用于与计算机系统的处理器和系统存储器接口的总线接口，耦合到总线接口的盘I / O引擎以及耦合到盘I / O引擎的设备接口，用于将盘I / O引擎与磁盘驱动器。磁盘I / O引擎被配置为在从处理器接收到磁盘启动命令时引起磁盘驱动器的启动。磁盘I / O引擎还被配置为通过从耦合到磁盘I / O引擎的旁路寄存器处理磁盘事务信息来执行磁盘事务。

5. 发明授权

US08386648B1 Hardware support system for accelerated disk I/O 有权
标题翻译：用于加速磁盘I / O的硬件支持系统
公开(公告)号：US08386648B1
公开(公告)日：2013-02-26
申请号：US10725663
申请日：2003-12-01
申请人： Radoslav Danilak , Krishnaraj S. Rao
发明人： Radoslav Danilak , Krishnaraj S. Rao
IPC分类号： G06F3/00
CPC分类号： G06F3/0659 , G06F3/061 , G06F3/0676 , G06F13/385
摘要： A hardware support system for implementing accelerated disk I/O for a computer system. The system includes a bus interface for interfacing with a processor and a system memory of the computer system, a disk I/O engine coupled to the bus interface, and a device interface coupled to the disk I/O engine for interfacing the disk I/O engine with a disk drive. The disk I/O engine is configured to cause a start up of the disk drive upon receiving a disk start up command from the processor. The disk I/O engine is further configured to execute a disk transaction by processing the disk transaction information from a bypass register coupled to the disk I/O engine.
摘要翻译：用于实现计算机系统的加速磁盘I / O的硬件支持系统。该系统包括用于与计算机系统的处理器和系统存储器接口的总线接口，耦合到总线接口的盘I / O引擎以及耦合到盘I / O引擎的设备接口，用于将盘I / O引擎与磁盘驱动器。磁盘I / O引擎被配置为在从处理器接收到磁盘启动命令时引起磁盘驱动器的启动。磁盘I / O引擎还被配置为通过从耦合到磁盘I / O引擎的旁路寄存器处理磁盘事务信息来执行磁盘事务。

6. 发明申请

US20080177925A1 Hardware support system for accelerated disk I/O 有权
公开(公告)号：US20080177925A1
公开(公告)日：2008-07-24
申请号：US12005745
申请日：2007-12-28
申请人： Radoslav Danilak , Krishnaraj S. Rao
发明人： Radoslav Danilak , Krishnaraj S. Rao
IPC分类号： G06F13/42 , G06F13/00
CPC分类号： G06F13/385
摘要： A hardware support system for implementing accelerated disk I/O for a computer system. The system includes a bus interface for interfacing with a processor and a system memory of the computer system, a disk I/O engine coupled to the bus interface, and a device interface coupled to the disk I/O engine for interfacing the disk I/O engine with a disk drive. The disk I/O engine is configured to cause a start up of the disk drive upon receiving a disk start up command from the processor. The disk I/O engine is further configured to execute a disk transaction by processing the disk transaction information from a bypass register coupled to the disk I/O engine.

7. 发明授权

US07633461B1 Graphics system including a plurality of heads 有权
标题翻译：图形系统包括多个头
公开(公告)号：US07633461B1
公开(公告)日：2009-12-15
申请号：US11408548
申请日：2006-04-21
申请人： Jonah Matthew Alben , Krishnaraj S. Rao
发明人： Jonah Matthew Alben , Krishnaraj S. Rao
IPC分类号： G09G5/00
CPC分类号： G06F3/1438 , G09G5/363
摘要： The graphics display system comprises a plurality of heads. Each of the heads includes a VGA controller and each of the heads is adapted for a display. The display system also includes a host coupled to the heads, wherein all the standard VGA settings for each of the heads could be programmed by a single command by the host. A method and system in accordance with the invention includes one VGA controller per head. In a broadcast mode a write transaction from the bus is broadcast to both heads. The output timing registers specific to a non-CRT output are not broadcast. To provide broadcast VGA to a CRT and/or a flat panel, software sets up the timing in extended registers and enables the display devices. The VGA application can provide mode settings via the appropriate write VGA registers and the correct display will be on each head.
摘要翻译：图形显示系统包括多个头。每个头部包括VGA控制器，并且每个头部适于显示器。显示系统还包括耦合到磁头的主机，其中用于每个磁头的所有标准VGA设置可以由主机通过单个命令编程。根据本发明的方法和系统包括每个头的一个VGA控制器。在广播模式中，来自总线的写事务被广播到两个头。不会广播特定于非CRT输出的输出定时寄存器。为了向CRT和/或平板提供广播VGA，软件设置扩展寄存器中的时序，并使显示设备成为可能。 VGA应用程序可以通过适当的写入VGA寄存器提供模式设置，正确的显示将在每个头上。

8. 发明授权

US07746349B1 Method and apparatus for display of data 有权
标题翻译：用于显示数据的方法和装置
公开(公告)号：US07746349B1
公开(公告)日：2010-06-29
申请号：US11083695
申请日：2005-03-16
申请人： Krishnaraj S. Rao , David G. Reed , Sean Jeffrey Treichler
发明人： Krishnaraj S. Rao , David G. Reed , Sean Jeffrey Treichler
IPC分类号： G06T1/60 , G09G5/39 , G06F13/28
CPC分类号： G09G5/222 , G06T1/20 , G09G2360/125
摘要： To display a row of characters in the VGA alphanumeric mode, the ASCII and attribute bits for all such characters are retrieved from the main memory and stored in a local cache memory. The font and unused bits that are also retrieved from the memory during the retrieval of ASCII and attribute bits are discarded. The stored ASCII and attribute bits for each such character is then used to compute the address of the associated font bits in the main memory. Next, for each character, the font bits are retrieved from the main memory using a burst read operation and using the computed address for that font. The font bits associated with all the characters in the row are stored in the local cache memory and are subsequently scanned out to be used in the display of the characters.
摘要翻译：要以VGA字母数字模式显示一行字符，所有这些字符的ASCII和属性位将从主存储器中检索并存储在本地缓存中。在检索ASCII和属性位期间也从存储器检索的字体和未使用的位将被丢弃。每个这样的字符的存储的ASCII和属性位然后用于计算主存储器中相关字体位的地址。接下来，对于每个字符，使用突发读取操作从主存储器中检索字体位，并使用所计算的该字体的地址。与行中的所有字符相关联的字体位存储在本地高速缓冲存储器中，随后被扫描以用于字符显示。

9. 发明授权

US07095386B2 Graphics system including a plurality of heads 有权
公开(公告)号：US07095386B2
公开(公告)日：2006-08-22
申请号：US09877462
申请日：2001-06-07
申请人： Jonah Matthew Alben , Krishnaraj S. Rao
发明人： Jonah Matthew Alben , Krishnaraj S. Rao
IPC分类号： G09G5/00
CPC分类号： G06F3/1438 , G09G5/363
摘要： A graphics display system is disclosed. The display system comprises a plurality of heads. Each of the plurality of heads includes a VGA controller and each of the plurality of heads is adapted for a display. The graphics display system also includes a host coupled to the plurality of heads, wherein all the standard VGA settings for each of the plurality of the heads could be programmed by a single command by the host. Each of the heads are adapted for a display. A system and method for providing a broadcast mode VGA feature is disclosed. A method and system in accordance with the present invention includes one VGA controller per head. In so doing, in a broadcast mode a write transaction from the bus is broadcast or written to both heads. Also, in a broadcast mode, the VGA read data from the bus always comes from one of the heads. The output timing registers specific to a non-CRT output are not broadcast. To provide broadcast VGA to a CRT and/or a flat panel, software sets up the timing in extended registers and enables the display devices. The VGA application can then provide mode settings via the appropriate write VGA registers and the correct display will be on each head.

10. 发明授权

US07301542B1 System and method for filtering graphics data on scanout to a monitor 有权
标题翻译：将扫描的图形数据过滤到监视器的系统和方法
公开(公告)号：US07301542B1
公开(公告)日：2007-11-27
申请号：US10954548
申请日：2004-09-29
申请人： Michael Toksvig , Walter Donovan , Jonah M. Alben , Krishnaraj S. Rao , Stephen D. Lew
发明人： Michael Toksvig , Walter Donovan , Jonah M. Alben , Krishnaraj S. Rao , Stephen D. Lew
IPC分类号： G06T1/60 , G06T9/00 , G06T1/00
CPC分类号： G09G5/395 , G06T5/20 , G09G5/391 , G09G2340/02
摘要： A graphics processing system performs filtering of oversampled data during a scanout operation. Sample values are read from an oversampled frame buffer and filtered during scanout; the filtered color values (one per pixel) are provided to a display device without an intervening step of storing the filtered data in a frame buffer. In one embodiment, the filtering circuit includes a memory interface configured to read data values corresponding to sample points from a frame buffer containing the oversampled data; and a filter configured to receive the data values provided by the memory interface, to compute a pixel value from the data values, and to transmit the pixel value for displaying by a display device, wherein the filter computes the pixel value during a scanout operation.
摘要翻译：图形处理系统在扫描输出操作期间对过采样数据执行滤波。从过采样帧缓冲区中读取采样值，并在扫描期间进行滤波; 滤波后的颜色值（每像素一个）被提供给显示设备，而没有将经滤波的数据存储在帧缓冲器中的中间步骤。在一个实施例中，滤波电路包括被配置为从包含过采样数据的帧缓冲器读取对应于采样点的数据值的存储器接口; 以及滤波器，被配置为接收由所述存储器接口提供的数据值，以从所述数据值计算像素值，并且传输所述像素值以供显示设备显示，其中，所述滤波器在扫描输出操作期间计算所述像素值。

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