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    • 4. 发明授权
    • Method of forming transistor devices with different threshold voltages using halo implant shadowing
    • 使用光晕植入物阴影形成具有不同阈值电压的晶体管器件的方法
    • US07598161B2
    • 2009-10-06
    • US11861534
    • 2007-09-26
    • Jingrong ZhouMark MichaelDonna Michael, legal representativeDavid WuJames F. BullerAkif Sultan
    • Jingrong ZhouMark MichaelDavid WuJames F. BullerAkif Sultan
    • H01L21/425
    • H01L21/26513H01L21/26586H01L21/823807H01L29/1083
    • The halo implant technique described herein employs a halo implant mask that creates a halo implant shadowing effect during halo dopant bombardment. A first transistor device structure and a second transistor device structure are formed on a wafer such that they are orthogonally oriented to each other. A common halo implant mask is created with features that prevent halo implantation of the diffusion region of the second transistor device structure during halo implantation of the diffusion region of the first transistor device structure, and with features that prevent halo implantation of the diffusion region of the first transistor device structure during halo implantation of the diffusion region of the second transistor device structure. The orthogonal orientation of the transistor device structures and the pattern of the halo implant mask obviates the need to create multiple implant masks to achieve different threshold voltages for the transistor device structures.
    • 本文描述的光晕植入技术采用在光晕掺杂剂轰击期间产生晕轮植入物阴影效应的光晕注入掩模。 第一晶体管器件结构和第二晶体管器件结构形成在晶片上,使得它们彼此正交地取向。 创建了常见的光晕注入掩模,其特征在于,在第一晶体管器件结构的扩散区域的晕圈注入期间防止第二晶体管器件结构的扩散区域的光晕注入,并且具有防止第 在第二晶体管器件结构的扩散区的晕圈注入期间的第一晶体管器件结构。 晶体管器件结构的正交取向和光晕注入掩模的图案消除了创建多个注入掩模以实现晶体管器件结构的不同阈值电压的需要。
    • 5. 发明授权
    • Distinguishing between dopant and line width variation components
    • 区分掺杂剂和线宽变化组分
    • US07582493B2
    • 2009-09-01
    • US11538872
    • 2006-10-05
    • Akif SultanJames F. BullerDavid Donggang Wu
    • Akif SultanJames F. BullerDavid Donggang Wu
    • H01L21/66
    • H01L22/12H01L22/14
    • A test structure includes first and second pluralities of transistors. The first plurality of transistors includes gate electrodes of a first length. The second plurality of transistors includes gate electrodes of a second length different than the first length. A channel area of the transistors in the first plurality is substantially equal to a channel area of the transistors in the second plurality. A method for using the test structure includes measuring a performance metric of the first and second pluralities of transistors. Variation in the performance metric associated with the first plurality of transistors is compared to variation in the performance metric associated with the second plurality of transistors to identify a random length variation component associated with the first plurality of transistors.
    • 测试结构包括第一和第二多个晶体管。 第一多个晶体管包括第一长度的栅电极。 第二多个晶体管包括与第一长度不同的第二长度的栅电极。 第一多个晶体管的沟道面积基本上等于第二多个晶体管的沟道面积。 使用该测试结构的方法包括测量第一和第二多个晶体管的性能度量。 将与第一多个晶体管相关联的性能度量的变化与与第二多个晶体管相关联的性能度量的变化进行比较,以识别与第一多个晶体管相关联的随机长度变化分量。
    • 6. 发明申请
    • Distinguishing Between Dopant and Line Width Variation Components
    • 区分掺杂剂和线宽变化组分
    • US20080085570A1
    • 2008-04-10
    • US11538872
    • 2006-10-05
    • Akif SultanJames F. BullerDavid Donggang Wu
    • Akif SultanJames F. BullerDavid Donggang Wu
    • H01L21/66
    • H01L22/12H01L22/14
    • A test structure includes first and second pluralities of transistors. The first plurality of transistors includes gate electrodes of a first length. The second plurality of transistors includes gate electrodes of a second length different than the first length. A channel area of the transistors in the first plurality is substantially equal to a channel area of the transistors in the second plurality. A method for using the test structure includes measuring a performance metric of the first and second pluralities of transistors. Variation in the performance metric associated with the first plurality of transistors is compared to variation in the performance metric associated with the second plurality of transistors to identify a random length variation component associated with the first plurality of transistors.
    • 测试结构包括第一和第二多个晶体管。 第一多个晶体管包括第一长度的栅电极。 第二多个晶体管包括与第一长度不同的第二长度的栅电极。 第一多个晶体管的沟道面积基本上等于第二多个晶体管的沟道面积。 使用测试结构的方法包括测量第一和第二多个晶体管的性能度量。 将与第一多个晶体管相关联的性能度量的变化与与第二多个晶体管相关联的性能度量的变化进行比较,以识别与第一多个晶体管相关联的随机长度变化分量。
    • 8. 发明授权
    • Methods of quantifying variations resulting from manufacturing-induced corner rounding of various features, and structures for testing same
    • 量化由各种特征的制造引起的角圆化引起的变化的方法以及用于测试相同的结构的方法
    • US07504270B2
    • 2009-03-17
    • US11425913
    • 2006-06-22
    • David D. WuMark W. MichaelAkif SultanJingrong Zhou
    • David D. WuMark W. MichaelAkif SultanJingrong Zhou
    • G10R31/26H01L21/66
    • H01L22/34G03F7/70658H01L22/12
    • The present invention is directed to methods of quantifying variations resulting from manufacturing-induced corner rounding of various features, and structures for testing same. In one illustrative embodiment, the method includes forming a plurality of test structures on a semiconducting substrate, each of the test structures having at least one physical dimension that varies relative to the other of the plurality of test structures, at least some of the test structures exhibiting at least some degree of manufacturing-induced corner rounding, forming at least one reference test structure, performing at least one electrical test on the plurality of test structures and on the reference test structure to thereby produce electrical test results, and analyzing the test results to determine an impact of the manufacturing-induced corner rounding on the performance of the plurality of test structures.
    • 本发明涉及量化由各种特征的制造引起的角舍入引起的变化的方法和用于测试相同结构的方法。 在一个说明性实施例中,该方法包括在半导体衬底上形成多个测试结构,每个测试结构具有相对于多个测试结构中的另一个变化的至少一个物理尺寸,至少一些测试结构 表现出至少一定程度的制造引起的角落四舍五入,形成至少一个参考测试结构,对多个测试结构和参考测试结构进行至少一次电测试,从而产生电测试结果,并分析测试结果 以确定制造性角落四舍五入对多个测试结构的性能的影响。
    • 9. 发明授权
    • Formation of ultra-shallow depth source/drain extensions for MOS transistors
    • 形成MOS晶体管的超浅深度源极/漏极延伸
    • US06727136B1
    • 2004-04-27
    • US10273291
    • 2002-10-18
    • James F. BullerDerick J. WristersDavid WuAkif Sultan
    • James F. BullerDerick J. WristersDavid WuAkif Sultan
    • H01L21336
    • H01L29/6659H01L21/823418H01L21/823814H01L29/1054H01L29/7833
    • A method of manufacturing a semiconductor device, comprising sequential steps of: (a) providing a semiconductor substrate including a pre-selected thickness strained lattice layer of a first semiconductor material at an upper surface thereof and an underlying layer of a second semiconductor material; and (b) introducing a dopant-containing species of one conductivity type into at least one pre-selected portion of the strained lattice layer of first semiconductor material to form a dopant-containing region therein with a junction at a depth substantially equal to the pre-selected thickness, wherein the second semiconductor material of the underlying layer inhibits diffusion thereinto of the dopant-containing species from the strained lattice layer, thereby controlling/limiting the depth of the junction to substantially the pre-selected thickness of the strained lattice layer.
    • 一种制造半导体器件的方法,包括以下顺序的步骤:(a)提供半导体衬底,该半导体衬底在其上表面包括预先选定的第一半导体材料的应变晶格层和第二半导体材料的下层; 和(b)将含有一种导电类型的含掺杂剂的物质引入到第一半导体材料的应变晶格层的至少一个预先选择的部分中,以在其中形成含有掺杂剂的区域,其中接合部的深度基本上等于预先 - 选择的厚度,其中下层的第二半导体材料抑制来自应变晶格层的含掺杂剂物质的扩散,从而将结的深度控制/限制到基本上预应变晶格层的预选厚度。
    • 10. 发明授权
    • Semiconductor device and methods for fabricating same
    • 半导体装置及其制造方法
    • US08076703B2
    • 2011-12-13
    • US12603353
    • 2009-10-21
    • Akif SultanJames F. BullerKaveri Mathur
    • Akif SultanJames F. BullerKaveri Mathur
    • H01L29/78
    • H01L27/1203H01L21/823807H01L21/823878H01L21/84H01L29/7843
    • A semiconductor device is provided which includes a substrate including an inactive region and an active region, a gate electrode structure having portions overlying the active region, a compressive layer overlying the active region, and a tensile layer overlying the inactive region and located outside the active region. The active region has a lateral edge which defines a width of the active region, and a transverse edge which defines a length of the active region. The gate electrode structure includes: a common portion spaced apart from the active region; a plurality of gate electrode finger portions integral with the common portion, and a plurality of fillet portions integral with the common portion and the gate electrode finger portions. A portion of each gate electrode finger portion overlies the active region. The fillet portions are disposed between the common portion and the gate electrode finger portions, and do not overlie the active region. The compressive layer also overlies the gate electrode finger portions, and the tensile layer is disposed adjacent the transverse edge of the active region.
    • 提供了一种半导体器件,其包括:基板,其包括非活性区域和有源区域;栅极电极结构,其具有覆盖有源区域的部分;覆盖有源区域的压缩层;以及覆盖非活性区域并位于有源区域外部的拉伸层 地区。 有源区域具有限定有源区域的宽度的横向边缘和限定有源区域的长度的横向边缘。 栅电极结构包括:与有源区间隔开的公共部分; 与公共部分成一体的多个栅极电极指部,以及与公共部分和栅电极指部分成一体的多个圆角部分。 每个栅电极指部分的一部分覆盖有源区。 圆角部分设置在公共部分和栅极电极指部分之间,并且不覆盖有源区域。 压电层也覆盖在栅极电极指部分上,并且拉伸层邻近有源区的横向边缘设置。