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1. 发明授权

US08094482B2 Nonvolatile memory apparatus and nonvolatile data storage medium 有权
标题翻译：非易失性存储装置和非易失性数据存储介质
公开(公告)号：US08094482B2
公开(公告)日：2012-01-10
申请号：US12529466
申请日：2008-10-28
申请人： Zhiqiang Wei , Takeshi Takagi , Ken Kawai , Kazuhiko Shimakawa
发明人： Zhiqiang Wei , Takeshi Takagi , Ken Kawai , Kazuhiko Shimakawa
IPC分类号： G11C11/00
CPC分类号： H01L27/101 , G11C11/5685 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/0073 , G11C2013/009 , G11C2211/5646 , G11C2213/31 , G11C2213/32 , G11C2213/34 , G11C2213/79
摘要： A nonvolatile memory apparatus and a nonvolatile data storage medium of the present invention, including nonvolatile memory elements each of which changes its resistance in response to electric pulses applied, comprises a first write circuit for performing first write in which a first electric pulse is applied to the nonvolatile memory element to switch a resistance value of the nonvolatile memory element from a first resistance value to a second resistance value and a second electric pulse which is opposite in polarity to the first electric pulse is applied to the nonvolatile memory element to switch the resistance value of the nonvolatile memory element from the second resistance value to the first resistance value.
摘要翻译：本发明的非易失性存储装置和非易失性数据存储介质，包括各自根据施加的电脉冲改变其电阻的非易失性存储元件，包括用于执行第一写入的第一写入电路，其中施加第一电脉冲到将非易失性存储元件的电阻值从第一电阻值切换到与第一电脉冲极性相反的第二电阻值和第二电脉冲的非易失性存储元件施加到非易失性存储元件，以将电阻非易失性存储元件的值从第二电阻值到第一电阻值。

2. 发明申请

US20100014343A1 NONVOLATILE MEMORY APPARATUS AND NONVOLATILE DATA STORAGE MEDIUM 有权
标题翻译：非易失性存储器和非易失性数据存储介质
公开(公告)号：US20100014343A1
公开(公告)日：2010-01-21
申请号：US12529466
申请日：2008-10-28
申请人： Zhiqiang Wei , Takeshi Takagi , Ken Kawai , Kazuhiko Shimakawa
发明人： Zhiqiang Wei , Takeshi Takagi , Ken Kawai , Kazuhiko Shimakawa
IPC分类号： G11C11/00 , G11C11/416
CPC分类号： H01L27/101 , G11C11/5685 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/0073 , G11C2013/009 , G11C2211/5646 , G11C2213/31 , G11C2213/32 , G11C2213/34 , G11C2213/79
摘要： [Objective] A nonvolatile memory apparatus and a nonvolatile data storage medium of the present invention, including nonvolatile memory elements each of which changes its resistance in response to electric pulses applied, comprises a first write circuit (106) for performing first write in which a first electric pulse is applied to the nonvolatile memory element to switch a resistance value of the nonvolatile memory element from a first resistance value to a second resistance value and a second electric pulse which is opposite in polarity to the first electric pulse is applied to the nonvolatile memory element to switch the resistance value of the nonvolatile memory element from the second resistance value to the first resistance value; and a second write circuit (108) for performing second write in which a third electric pulse is applied to the nonvolatile memory element to switch the resistance value of the nonvolatile memory element from a third resistance value to a fourth resistance value and a fourth electric pulse which is identical in polarity to the third electric pulse is applied to the nonvolatile memory element to switch the resistance value of the nonvolatile memory element from the fourth resistance value to a fifth resistance value.
摘要翻译： [目的]本发明的非易失性存储装置和非易失性数据存储介质，包括响应于施加的电脉冲改变其电阻的非易失性存储元件，包括用于执行第一写入的第一写入电路（106），其中将第一电脉冲施加到非易失性存储元件，以将非易失性存储元件的电阻值从第一电阻值切换到第二电阻值，并将与第一电脉冲极性相反的第二电脉冲施加到非易失性存储元件存储元件，用于将非易失性存储元件的电阻值从第二电阻值切换到第一电阻值; 以及第二写入电路（108），用于执行第二写入，其中第三电脉冲被施加到非易失性存储元件，以将非易失性存储元件的电阻值从第三电阻值切换到第四电阻值和第四电脉冲将与第三电脉冲相同的极性相加到非易失性存储元件，以将非易失性存储元件的电阻值从第四电阻值切换到第五电阻值。

3. 发明授权

US08179714B2 Nonvolatile storage device and method for writing into memory cell of the same 有权
标题翻译：非易失性存储装置和写入其中的存储单元的方法
公开(公告)号：US08179714B2
公开(公告)日：2012-05-15
申请号：US12865193
申请日：2009-10-16
申请人： Takeshi Takagi , Shunsaku Muraoka , Mitsuteru Iijima , Ken Kawai , Kazuhiko Shimakawa
发明人： Takeshi Takagi , Shunsaku Muraoka , Mitsuteru Iijima , Ken Kawai , Kazuhiko Shimakawa
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0007 , G11C13/0064 , G11C2013/0083 , G11C2013/009 , G11C2213/32 , G11C2213/56 , G11C2213/79
摘要： Provided is a nonvolatile storage device (200) capable of stably operating without increasing a size of a selection transistor included in each of memory cells. The nonvolatile storage device (200) includes: a semiconductor substrate (301) which has a P-type well (301a) of a first conductivity type; a memory cell array (202) which includes memory cells (M11) or the like each of which includes a variable resistance element (R11) and a transistor (N11) that are formed above the semiconductor substrate (301) and connected in series; and a substrate bias circuit (220) which applies, to the P-type well (301a), a bias voltage in a forward direction with respect to a source and a drain of the transistor (N11), when a voltage pulse for writing is applied to the variable resistance element (R11) included in the selected memory cell (M11) or the like.
摘要翻译：提供一种能够在不增加包含在每个存储单元中的选择晶体管的尺寸的情况下稳定地工作的非易失性存储装置（200）。非易失性存储装置（200）包括：具有第一导电型的P型阱（301a）的半导体基板（301）存储单元阵列（202），其包括存储单元（M11）等，每个存储单元包括形成在半导体衬底（301）上并串联连接的可变电阻元件（R11）和晶体管（N11）; 以及衬底偏置电路（220），当用于写入的电压脉冲为写入电压脉冲时，向P型阱（301a）施加相对于晶体管（N11）的源极和漏极的正向偏置电压应用于所选择的存储单元（M11）等中包含的可变电阻元件（R11）。

4. 发明申请

US20110007553A1 NONVOLATILE STORAGE DEVICE AND METHOD FOR WRITING INTO MEMORY CELL OF THE SAME 有权
标题翻译：非易失存储器件和用于写入其中的存储器单元的方法
公开(公告)号：US20110007553A1
公开(公告)日：2011-01-13
申请号：US12865193
申请日：2009-10-16
申请人： Takeshi Takagi , Shunsaku Muraoka , Mitsuteru Iijima , Ken Kawai , Kazuhiko Shimakawa
发明人： Takeshi Takagi , Shunsaku Muraoka , Mitsuteru Iijima , Ken Kawai , Kazuhiko Shimakawa
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0069 , G11C13/0007 , G11C13/0064 , G11C2013/0083 , G11C2013/009 , G11C2213/32 , G11C2213/56 , G11C2213/79
摘要： Provided is a nonvolatile storage device (200) capable of stably operating without increasing a size of a selection transistor included in each of memory cells. The nonvolatile storage device (200) includes: a semiconductor substrate (301) which has a P-type well (301a) of a first conductivity type; a memory cell array (202) which includes memory cells (M11) or the like each of which includes a variable resistance element (R11) and a transistor (N11) that are formed above the semiconductor substrate (301) and connected in series; and a substrate bias circuit (220) which applies, to the P-type well (301a), a bias voltage in a forward direction with respect to a source and a drain of the transistor (N11), when a voltage pulse for writing is applied to the variable resistance element (R11) included in the selected memory cell (M11) or the like.
摘要翻译：提供一种能够在不增加包含在每个存储单元中的选择晶体管的尺寸的情况下稳定地工作的非易失性存储装置（200）。非易失性存储装置（200）包括：具有第一导电型的P型阱（301a）的半导体基板（301）存储单元阵列（202），其包括存储单元（M11）等，每个存储单元包括形成在半导体衬底（301）上并串联连接的可变电阻元件（R11）和晶体管（N11）; 以及衬底偏置电路（220），当用于写入的电压脉冲为写入电压脉冲时，向P型阱（301a）施加相对于晶体管（N11）的源极和漏极的正向偏置电压应用于所选择的存储单元（M11）等中包含的可变电阻元件（R11）。

5. 发明授权

US08867259B2 Method of programming variable resistance nonvolatile memory element 有权
标题翻译：编程可变电阻非易失性存储元件的方法
公开(公告)号：US08867259B2
公开(公告)日：2014-10-21
申请号：US13704649
申请日：2012-08-09
申请人： Ken Kawai , Kazuhiko Shimakawa , Yoshikazu Katoh , Shunsaku Muraoka
发明人： Ken Kawai , Kazuhiko Shimakawa , Yoshikazu Katoh , Shunsaku Muraoka
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/0069 , G11C13/0007 , G11C13/004 , G11C13/0064 , G11C2013/0054 , G11C2013/0073 , G11C2013/0083 , G11C2013/0092 , G11C2213/56 , G11C2213/79
摘要： A method of programming a variable resistance nonvolatile memory element that removes a defect in a resistance change, ensures an operation widow, and stably sustains a resistance change operation, the method including: applying, when the detect in the resistance change occurs in the variable resistance nonvolatile memory element, a recovery voltage pulse at least once to the variable resistance nonvolatile memory element, the recovery voltage pulse including: a first recovery voltage pulse that has an amplitude greater than amplitudes of a normal high resistance writing voltage pulse and a low resistance writing voltage pulse; and a second recovery voltage pulse that is the low resistance writing voltage pulse following the first recovery voltage pulse.
摘要翻译：一种编程消除电阻变化缺陷的可变电阻非易失性存储元件的方法，确保操作遗ow，并稳定地维持电阻变化操作，该方法包括：当在可变电阻中发生电阻变化的检测时，非易失性存储元件，至少一次到可变电阻非易失性存储元件的恢复电压脉冲，恢复电压脉冲包括：第一恢复电压脉冲，其具有大于正常高电阻写入电压脉冲和低电阻写入的幅度的幅度电压脉冲; 以及第二恢复电压脉冲，其是跟随第一恢复电压脉冲的低电阻写入电压脉冲。

6. 发明授权

US08325508B2 Writing method for variable resistance nonvolatile memory element, and variable resistance nonvolatile memory device 有权
标题翻译：可变电阻非易失性存储元件和可变电阻非易失性存储器件的写入方法
公开(公告)号：US08325508B2
公开(公告)日：2012-12-04
申请号：US13001905
申请日：2010-06-08
申请人： Ken Kawai , Kazuhiko Shimakawa , Shunsaku Muraoka , Ryotaro Azuma
发明人： Ken Kawai , Kazuhiko Shimakawa , Shunsaku Muraoka , Ryotaro Azuma
IPC分类号： G11C11/00
CPC分类号： G11C11/5685 , G11C13/0007 , G11C13/0038 , G11C13/0064 , G11C13/0069 , G11C2013/0071 , G11C2013/0073 , G11C2013/0083 , G11C2213/56 , G11C2213/79
摘要： A writing method optimum for a variable resistance element which can maximize an operation window of the variable resistance element is provided. The writing method is performed for a variable resistance element that reversibly changes between a high resistance state and a low resistance state depending on a polarity of an applied voltage pulse. The writing method includes a preparation step (S50) and a writing step (S51, S51a, S51b). At the preparation step (S50), resistance values of the variable resistance element are measured by applying voltage pulses of voltages that are gradually increased to the variable resistance element, thereby determining the first voltage V1 for starting high resistance writing and the second voltage V2 having a maximum resistance value. At the HR writing step (S51a), a voltage pulse having a voltage Vp that is equal to or higher than the first voltage V1 and equal to or lower than the second voltage V2 is applied to the variable resistance element, thereby changing the variable resistance element from the low resistance state (S52) to the high resistance state (S53).
摘要翻译：提供了一种最佳可变电阻元件的写入方法，其可以使可变电阻元件的操作窗口最大化。对于根据施加的电压脉冲的极性在高电阻状态和低电阻状态之间可逆地变化的可变电阻元件执行写入方法。写入方法包括准备步骤（S50）和写入步骤（S51，S51a，S51b）。在准备步骤（S50）中，通过向可变电阻元件施加逐渐增加的电压的电压脉冲来测量可变电阻元件的电阻值，从而确定用于开始高电阻写入的第一电压V1和具有最大电阻值。在HR写入步骤（S51a）中，将具有等于或高于第一电压V1并且等于或低于第二电压V2的电压Vp的电压脉冲施加到可变电阻元件，从而改变可变电阻元件从低电阻状态（S52）到高电阻状态（S53）。

7. 发明申请

US20120230085A1 FORMING METHOD OF PERFORMING FORMING ON VARIABLE RESISTANCE NONVOLATILE MEMORY ELEMENT, AND VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE 有权
标题翻译：形成可变电阻非易失性存储器元件和可变电阻非易失性存储器件的形成方法
公开(公告)号：US20120230085A1
公开(公告)日：2012-09-13
申请号：US13511275
申请日：2011-09-28
申请人： Ken Kawai , Kazuhiko Shimakawa , Koji Katayama , Shunsaku Muraoka
发明人： Ken Kawai , Kazuhiko Shimakawa , Koji Katayama , Shunsaku Muraoka
IPC分类号： G11C11/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C2013/0073 , G11C2013/0083 , G11C2213/32 , G11C2213/72 , G11C2213/79 , H01L27/2409 , H01L45/08 , H01L45/1233 , H01L45/146
摘要： In forming, an automatic forming circuit (210) included in a nonvolatile memory device (200) causes a constant current IL to flow in a selected memory cell having a considerably high initial resistance. When the forming generates a filament path in the memory cell and thereby a resistance value is decreased, a potential of a node NBL and a potential of a node Nin are also decreased. If the potentials become lower than that of a reference voltage Vref, an output NO of a difference amplifier (303) for detecting forming success is activated, and a forming success signal Vfp is activated after a delay time depending on the number n of flip flops FF1 to FFn and a clock signal CLK. Thereby, a switch transistor (301) is in a non-conducting state and the forming on a variable resistance element is automatically terminated.
摘要翻译：在形成时，包括在非易失性存储器件（200）中的自动形成电路（210）使得恒定电流IL流过具有相当高的初始电阻的所选择的存储单元。当形成在存储单元中产生细丝通路并由此电阻值减小时，节点NBL的电位和节点Nin的电位也减小。如果电位变得低于参考电压Vref的电位，则激活用于检测成形成功的差分放大器（303）的输出NO，并且根据触发器的数量n在延迟时间之后激活形成成功信号Vfp FF1〜FFn和时钟信号CLK。由此，开关晶体管（301）处于非导通状态，可变电阻元件上的形成自动终止。

8. 发明申请

US20110216577A1 VARIABLE RESISTANCE NONVOLATILE STORAGE DEVICE 有权
标题翻译：可变电阻非易失存储器件
公开(公告)号：US20110216577A1
公开(公告)日：2011-09-08
申请号：US13126257
申请日：2010-08-26
申请人： Hiroshi Tomotani , Kazuhiko Shimakawa , Ken Kawai
发明人： Hiroshi Tomotani , Kazuhiko Shimakawa , Ken Kawai
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0026 , G11C13/0028 , G11C13/0038 , G11C13/0064 , G11C2013/0066 , G11C2013/0078 , G11C2213/15 , G11C2213/79 , G11C2213/82 , H01L27/10 , H01L45/00 , H01L49/00
摘要： The variable resistance nonvolatile storage device reduces variations in a resistance value of a variable resistance element (100) in the low resistance state, performs stable operations, and includes an LR write circuit (500) (i) applying a voltage to a memory cell (102) so that a resistance state of the variable resistance element included in the memory cell is changed from high to low, and (ii) including a first driving circuit (510) and a second driving circuit (520) which apply voltages to the memory cell and which have connected output terminals. When applying a voltage to the memory cell, the first driving circuit supplies a first current, and the second driving circuit (i) supplies a second current when a voltage at the output terminal of the first driving circuit is higher than a reference voltage VREF, and (ii) is in a high impedance state when the voltage is lower than the VREF.
摘要翻译：可变电阻非易失性存储装置减小了在低电阻状态下的可变电阻元件（100）的电阻值的变化，执行稳定的操作，并且包括LR写入电路（500）（i）向存储单元施加电压 102），使得包含在存储单元中的可变电阻元件的电阻状态从高变为低，并且（ii）包括向存储器施加电压的第一驱动电路（510）和第二驱动电路（520）并具有连接的输出端子。当向存储单元施加电压时，第一驱动电路提供第一电流，并且当第一驱动电路的输出端的电压高于参考电压VREF时，第二驱动电路（i）提供第二电流，和（ii）当电压低于VREF时处于高阻抗状态。

9. 发明申请

US20140078811A1 VARIABLE RESISTANCE NONVOLATILE MEMORY ELEMENT WRITING METHOD AND VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE 有权
标题翻译：可变电阻非易失性存储器元件写入方法和可变电阻非易失性存储器件
公开(公告)号：US20140078811A1
公开(公告)日：2014-03-20
申请号：US13990209
申请日：2012-11-21
申请人： Ken Kawai , Kazuhiko Shimakawa , Yoshikazu Katoh , Yuichiro Ikeda
发明人： Ken Kawai , Kazuhiko Shimakawa , Yoshikazu Katoh , Yuichiro Ikeda
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/00 , G11C13/004 , G11C13/0064 , G11C2013/0073 , G11C2013/0092
摘要： Provided is a method of writing to a variable resistance nonvolatile memory element which is capable of both improving retention characteristics and enlarging a window of operation. In the method of writing, to write “1” data (LR), first a weak HR writing process is performed in which a weak HR writing voltage pulse set for changing the variable resistance nonvolatile memory element to an intermediate resistance state is applied and, subsequently, a LR writing process is performed in which a LR writing voltage pulse set for changing the variable resistance nonvolatile memory element from the intermediate resistance state to a LR state is applied.
摘要翻译：提供一种写入能够改善保持特性和扩大操作窗口的可变电阻非易失性存储元件的方法。在写入方法中，为了写入“1”数据（LR），首先执行将用于将可变电阻非易失性存储元件变更为中间电阻状态而设定的弱的HR写入电压脉冲的弱的HR写入处理，随后，执行LR写入处理，其中设置用于将可变电阻非易失性存储元件从中间电阻状态改变为LR状态的LR写入电压脉冲。

10. 发明申请

US20130188414A1 VARIABLE RESISTANCE NONVOLATILE MEMORY ELEMENT WRITING METHOD AND VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE 有权
标题翻译：可变电阻非易失性存储器元件写入方法和可变电阻非易失性存储器件
公开(公告)号：US20130188414A1
公开(公告)日：2013-07-25
申请号：US13581925
申请日：2012-03-22
申请人： Ken Kawai , Kazuhiko Shimakawa , Yoshikazu Katoh
发明人： Ken Kawai , Kazuhiko Shimakawa , Yoshikazu Katoh
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0007 , G11C13/0064 , G11C2013/0073 , G11C2013/0083 , G11C2013/0092
摘要： A variable resistance nonvolatile memory element writing method of, by applying a voltage pulse to a memory cell including a variable resistance element, reversibly changing the variable resistance element between a first resistance state and a second resistance state according to a polarity of the applied voltage pulse is provided. The variable resistance nonvolatile memory element writing method includes applying a first preliminary voltage pulse and subsequently applying the first voltage pulse to the variable resistance element to change the variable resistance element from the second resistance state to the first resistance state, the first preliminary voltage pulse being smaller in voltage absolute value than the second threshold voltage and different in polarity from the first voltage pulse.
摘要翻译：一种可变电阻非易失性存储元件写入方法，通过向包括可变电阻元件的存储单元施加电压脉冲，根据所施加的电压脉冲的极性可逆地改变第一电阻状态和第二电阻状态之间的可变电阻元件被提供。可变电阻非易失性存储元件写入方法包括施加第一初步电压脉冲，并随后将第一电压脉冲施加到可变电阻元件，以将可变电阻元件从第二电阻状态改变到第一电阻状态，第一初步电压脉冲为电压绝对值比第二阈值电压小，并且极性与第一电压脉冲不同。

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