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1. 发明申请

US20140050003A1 VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE AND DRIVING METHOD OF VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE 有权
标题翻译：可变电阻非易失性存储器件和可变电阻非易失性存储器件的驱动方法
公开(公告)号：US20140050003A1
公开(公告)日：2014-02-20
申请号：US14113054
申请日：2012-05-24
申请人： Hiroshi Tomotani , Kazuhiko Shimakawa
发明人： Hiroshi Tomotani , Kazuhiko Shimakawa
IPC分类号： G11C29/00 , G11C13/00
CPC分类号： G11C29/70 , G11C13/004 , G11C13/0069 , G11C29/52 , G11C29/808 , G11C29/832 , G11C29/883 , G11C2029/5006 , G11C2213/15 , G11C2213/71 , G11C2213/72
摘要： A stable operation is implemented by reducing an abnormal current. A variable resistance nonvolatile memory device includes: a memory cell array having memory cells each including a variable resistance element and a current steering element that are connected in series, each of the memory cells being located at a three-dimensional cross point of one of bit lines and one of word lines, and the current steering element being assumed to be conducting when a voltage exceeding a predetermined threshold voltage is applied; and a detection circuit that detects a faulty memory cell that is in a second low resistance state where a resistance value is lower than a resistance value in a first low resistance state. Both the bit line and the word line that are connected to the faulty memory cell detected by the detection circuit are fixed in the inactive state.
摘要翻译：通过减少异常电流实现稳定运行。可变电阻非易失性存储器件包括：存储单元阵列，其具有各自包括串联连接的可变电阻元件和电流导向元件的存储单元，每个存储单元位于位之一的三维交叉点线路和字线之一，并且当施加超过预定阈值电压的电压时，假定当前的导向元件正在导通; 以及检测电路，其检测处于第二低电阻状态的电阻值低于第一低电阻状态下的电阻值的故障存储单元。连接到由检测电路检测到的故障存储单元的位线和字线均固定在不活动状态。

2. 发明授权

US08942050B2 Method of inspecting variable resistance nonvolatile memory device and variable resistance nonvolatile memory device 有权
标题翻译：检查可变电阻非易失性存储器件和可变电阻非易失性存储器件的方法
公开(公告)号：US08942050B2
公开(公告)日：2015-01-27
申请号：US13637428
申请日：2011-09-07
申请人： Hiroshi Tomotani , Kazuhiko Shimakawa , Ryotaro Azuma , Yoshikazu Katoh , Yuichiro Ikeda
发明人： Hiroshi Tomotani , Kazuhiko Shimakawa , Ryotaro Azuma , Yoshikazu Katoh , Yuichiro Ikeda
IPC分类号： G11C7/06 , G11C13/00 , G11C29/50
CPC分类号： G11C13/0007 , G11C13/00 , G11C13/003 , G11C29/50008 , G11C2213/15
摘要： A method of inspecting a variable resistance nonvolatile memory device detecting a faulty memory cell of a memory cell array employing a current steering element, and a variable resistance nonvolatile memory device are provided. The method of inspecting a variable resistance nonvolatile memory device having a memory cell array, a memory cell selection circuit, and a read circuit includes: determining that a current steering element has a short-circuit fault when a variable resistance element is in a low resistance state and a current higher than or equal to a predetermined current passes through the current steering element, when the resistance state of the memory cell is read using a second voltage; and determining whether the variable resistance element is in the low or high resistance state, when the resistance state of the memory cell is read using a first voltage.
摘要翻译：提供了检测使用电流导向元件的存储单元阵列的故障存储单元的可变电阻非易失性存储器件和可变电阻非易失性存储器件的方法。检查具有存储单元阵列的可变电阻非易失性存储器件，存储单元选择电路和读取电路的方法包括：当可变电阻元件处于低电阻时，确定当前的导向元件具有短路故障当使用第二电压读取存储单元的电阻状态时，高于或等于预定电流的电流通过电流导向元件; 以及当使用第一电压读取存储单元的电阻状态时，确定可变电阻元件是处于低电阻还是高电阻状态。

3. 发明授权

US09082515B2 Variable resistance nonvolatile memory device and driving method of variable resistance nonvolatile memory device 有权
标题翻译：可变电阻非易失性存储器件和可变电阻非易失性存储器件的驱动方法
公开(公告)号：US09082515B2
公开(公告)日：2015-07-14
申请号：US14113054
申请日：2012-05-24
申请人： Hiroshi Tomotani , Kazuhiko Shimakawa
发明人： Hiroshi Tomotani , Kazuhiko Shimakawa
IPC分类号： G11C11/00 , G11C29/00 , G11C13/00 , G11C29/52 , G11C29/50
CPC分类号： G11C29/70 , G11C13/004 , G11C13/0069 , G11C29/52 , G11C29/808 , G11C29/832 , G11C29/883 , G11C2029/5006 , G11C2213/15 , G11C2213/71 , G11C2213/72
摘要： A stable operation is implemented by reducing an abnormal current. A variable resistance nonvolatile memory device includes: a memory cell array having memory cells each including a variable resistance element and a current steering element that are connected in series, each of the memory cells being located at a three-dimensional cross point of one of bit lines and one of word lines, and the current steering element being assumed to be conducting when a voltage exceeding a predetermined threshold voltage is applied; and a detection circuit that detects a faulty memory cell that is in a second low resistance state where a resistance value is lower than a resistance value in a first low resistance state. Both the bit line and the word line that are connected to the faulty memory cell detected by the detection circuit are fixed in the inactive state.
摘要翻译：通过减少异常电流实现稳定运行。可变电阻非易失性存储器件包括：存储单元阵列，其具有各自包括串联连接的可变电阻元件和电流导向元件的存储单元，每个存储单元位于位之一的三维交叉点线路和字线之一，并且当施加超过预定阈值电压的电压时，假定当前的导向元件正在导通; 以及检测电路，其检测处于第二低电阻状态的电阻值低于第一低电阻状态下的电阻值的故障存储单元。连接到由检测电路检测到的故障存储单元的位线和字线均固定在不活动状态。

4. 发明授权

US08848422B2 Variable resistance nonvolatile memory device and driving method thereof 有权
标题翻译：可变电阻非易失性存储器件及其驱动方法
公开(公告)号：US08848422B2
公开(公告)日：2014-09-30
申请号：US13641719
申请日：2012-04-19
申请人： Hiroshi Tomotani , Kazuhiko Shimakawa , Yuichiro Ikeda
发明人： Hiroshi Tomotani , Kazuhiko Shimakawa , Yuichiro Ikeda
IPC分类号： G11C11/00 , G11C13/00 , G11C29/50
CPC分类号： G11C13/0069 , G11C13/0007 , G11C13/004 , G11C29/50 , G11C2029/5006 , G11C2213/72
摘要： A variable resistance nonvolatile memory device includes a memory cell array, a memory cell selection circuit, a write circuit, and a read circuit. The read circuit determines that a selected memory cell has a short-circuit fault when a current higher than or equal to a predetermined current passes through the selected memory cell. The write circuit sets another memory cell different from the faulty memory cell and located on at least a bit or word line including the faulty memory cell to a second high resistance state where a resistance value is higher than a resistance value in the first high resistance state, by applying a second high-resistance write pulse to the other memory cell.
摘要翻译：可变电阻非易失性存储器件包括存储单元阵列，存储单元选择电路，写入电路和读取电路。当电流高于或等于预定电流通过所选择的存储单元时，读取电路确定所选存储单元具有短路故障。写入电路设置与故障存储器单元不同的另一个存储单元，并且至少位于包括故障存储单元的位或字线至第二高电阻状态，其中电阻值高于第一高电阻状态下的电阻值通过对另一个存储单元施加第二高阻写入脉冲。

5. 发明申请

US20110216577A1 VARIABLE RESISTANCE NONVOLATILE STORAGE DEVICE 有权
标题翻译：可变电阻非易失存储器件
公开(公告)号：US20110216577A1
公开(公告)日：2011-09-08
申请号：US13126257
申请日：2010-08-26
申请人： Hiroshi Tomotani , Kazuhiko Shimakawa , Ken Kawai
发明人： Hiroshi Tomotani , Kazuhiko Shimakawa , Ken Kawai
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0026 , G11C13/0028 , G11C13/0038 , G11C13/0064 , G11C2013/0066 , G11C2013/0078 , G11C2213/15 , G11C2213/79 , G11C2213/82 , H01L27/10 , H01L45/00 , H01L49/00
摘要： The variable resistance nonvolatile storage device reduces variations in a resistance value of a variable resistance element (100) in the low resistance state, performs stable operations, and includes an LR write circuit (500) (i) applying a voltage to a memory cell (102) so that a resistance state of the variable resistance element included in the memory cell is changed from high to low, and (ii) including a first driving circuit (510) and a second driving circuit (520) which apply voltages to the memory cell and which have connected output terminals. When applying a voltage to the memory cell, the first driving circuit supplies a first current, and the second driving circuit (i) supplies a second current when a voltage at the output terminal of the first driving circuit is higher than a reference voltage VREF, and (ii) is in a high impedance state when the voltage is lower than the VREF.
摘要翻译：可变电阻非易失性存储装置减小了在低电阻状态下的可变电阻元件（100）的电阻值的变化，执行稳定的操作，并且包括LR写入电路（500）（i）向存储单元施加电压 102），使得包含在存储单元中的可变电阻元件的电阻状态从高变为低，并且（ii）包括向存储器施加电压的第一驱动电路（510）和第二驱动电路（520）并具有连接的输出端子。当向存储单元施加电压时，第一驱动电路提供第一电流，并且当第一驱动电路的输出端的电压高于参考电压VREF时，第二驱动电路（i）提供第二电流，和（ii）当电压低于VREF时处于高阻抗状态。

6. 发明授权

US06628536B2 Semiconductor memory device 有权
公开(公告)号：US06628536B2
公开(公告)日：2003-09-30
申请号：US10076426
申请日：2002-02-19
申请人： Hiroshi Tomotani
发明人： Hiroshi Tomotani
IPC分类号： G11C502
CPC分类号： G11C8/14 , H01L27/1104
摘要： A semiconductor memory device with a high-capacity memory cell array includes a plurality of global word lines per memory cell row of the memory cell array. The global word lines are formed in two wiring layers (upper and lower layers). This substantially reduces the number of memory cells connected per global word line without increasing the memory cell size, allowing for an improved operation speed of the memory cells and reduced power consumption.

7. 发明授权

US06452862B1 Semiconductor memory device having hierarchical word line structure 有权
公开(公告)号：US06452862B1
公开(公告)日：2002-09-17
申请号：US09981981
申请日：2001-10-19
申请人： Hiroshi Tomotani
发明人： Hiroshi Tomotani
IPC分类号： G11C800
CPC分类号： G11C8/10 , G11C8/12 , G11C8/14 , G11C11/418
摘要： The semiconductor memory device includes a memory cell array, a block selection circuit, a row decoder, a word driver, and a column decoder. The memory cell array includes a plurality of memory cells, a plurality of main word lines and a plurality of bit line pairs. The plurality of main word lines are provided corresponding to the rows, that is, m main word lines are provided per row (where m is an integer equal to or greater than two). The plurality of bit line pairs are provided corresponding to the columns. The memory cell array is divided into a plurality of memory blocks in the column direction. Each of the plurality of memory blocks further includes a plurality of sub word lines. The plurality of sub word lines are provided corresponding to the rows. Each of the plurality of sub word lines is connected to one of the m main word lines of the corresponding row.

8. 发明授权

US06188628B1 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US06188628B1
公开(公告)日：2001-02-13
申请号：US09547418
申请日：2000-04-11
申请人： Hiroshi Tomotani
发明人： Hiroshi Tomotani
IPC分类号： G11C700
CPC分类号： G11C7/22 , G11C5/14
摘要： The semiconductor storage device of this invention includes a memory cell array; word lines; bit lines; a peripheral circuit for controlling the potentials of the word lines and the bit lines; a peripheral circuit power line for connecting a power voltage supply terminal to the peripheral circuit; a peripheral circuit power switch; a memory cell array power line; a constant voltage supply line for connecting the word lines to ground; a word line switch for fixing a voltage disposed on the constant voltage supply line; and the like. The potential of the word lines is fixed by controlling the word line switch to be placed in a conducting state before switching the peripheral circuit power switch. Thus, data in the memory cells can be prevented from being destroyed by a transient current caused in turning on/off the switch.
摘要翻译：本发明的半导体存储装置包括存储单元阵列; 字线位线用于控制字线和位线的电位的外围电路; 用于将电源电压端子连接到外围电路的外围电路电源线; 外围电路电源开关; 存储单元阵列电源线; 用于将字线连接到地的恒压电源线; 用于固定设置在恒压电源线上的电压的字线开关; 等等。在切换外围电路电源开关之前，通过控制字线开关置于导通状态来固定字线的电位。因此，可以防止存储器单元中的数据被打开/关闭开关所引起的瞬态电流破坏。

9. 发明授权

US08699261B2 Variable resistance nonvolatile memory device and driving method thereof 有权
标题翻译：可变电阻非易失性存储器件及其驱动方法
公开(公告)号：US08699261B2
公开(公告)日：2014-04-15
申请号：US13698154
申请日：2012-07-04
申请人： Hiroshi Tomotani , Kazuhiko Shimakawa
发明人： Hiroshi Tomotani , Kazuhiko Shimakawa
IPC分类号： G11C11/00
CPC分类号： G11C13/0021 , G11C13/0007 , G11C13/0069 , G11C29/50008 , G11C29/76 , G11C2213/32 , G11C2213/56 , G11C2213/71 , G11C2213/72
摘要： A highly-reliable variable resistance nonvolatile memory device capable of a stable operation and a driving method of the variable resistance nonvolatile memory device are provided. A variable resistance nonvolatile memory device includes a memory cell array, a memory cell selection circuit, a write circuit, and a read circuit. The write circuit sets a variable resistance element of another memory cell different from a faulty memory cell and located on at least one of a bit line and a word line that includes the faulty memory cell to a second high resistance state where a resistance value is higher than a resistance value in a first low resistance state, by applying a second high-resistance write pulse to the other memory cell.
摘要翻译：提供一种能够稳定工作的高可靠性可变电阻非易失性存储装置和可变电阻非易失性存储装置的驱动方法。可变电阻非易失性存储器件包括存储单元阵列，存储单元选择电路，写电路和读电路。写入电路设置与故障存储单元不同的另一个存储单元的可变电阻元件，并且位于包含故障存储单元的位线和字线中的至少一个上，电阻值较高的第二高电阻状态比第一低电阻状态下的电阻值高，通过对另一个存储单元施加第二高电阻写入脉冲。

10. 发明授权

US08625328B2 Variable resistance nonvolatile storage device 有权
标题翻译：可变电阻非易失性存储装置
公开(公告)号：US08625328B2
公开(公告)日：2014-01-07
申请号：US13126257
申请日：2010-08-26
申请人： Hiroshi Tomotani , Kazuhiko Shimakawa , Ken Kawai
发明人： Hiroshi Tomotani , Kazuhiko Shimakawa , Ken Kawai
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0026 , G11C13/0028 , G11C13/0038 , G11C13/0064 , G11C2013/0066 , G11C2013/0078 , G11C2213/15 , G11C2213/79 , G11C2213/82 , H01L27/10 , H01L45/00 , H01L49/00
摘要： The variable resistance nonvolatile storage device reduces variations in a resistance value of a variable resistance element (100) in the low resistance state, performs stable operations, and includes an LR write circuit (500) (i) applying a voltage to a memory cell (102) so that a resistance state of the variable resistance element included in the memory cell is changed from high to low, and (ii) including a first driving circuit (510) and a second driving circuit (520) which apply voltages to the memory cell and which have connected output terminals. When applying a voltage to the memory cell, the first driving circuit supplies a first current, and the second driving circuit (i) supplies a second current when a voltage at the output terminal of the first driving circuit is higher than a reference voltage VREF, and (ii) is in a high impedance state when the voltage is lower than the VREF.
摘要翻译：可变电阻非易失性存储装置减小了在低电阻状态下的可变电阻元件（100）的电阻值的变化，执行稳定的操作，并且包括LR写入电路（500）（i）向存储单元施加电压 102），使得包含在存储单元中的可变电阻元件的电阻状态从高变为低，并且（ii）包括向存储器施加电压的第一驱动电路（510）和第二驱动电路（520）并具有连接的输出端子。当向存储单元施加电压时，第一驱动电路提供第一电流，并且当第一驱动电路的输出端的电压高于参考电压VREF时，第二驱动电路（i）提供第二电流，和（ii）当电压低于VREF时处于高阻抗状态。

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