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1. 发明授权

US06544904B1 Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06544904B1
公开(公告)日：2003-04-08
申请号：US10157882
申请日：2002-05-31
申请人： Yuuki Kamiura , Hiroshi Tobimatsu , Kouji Oda , Mahito Sawada , Koji Shibata , Hiroyuki Kawata
发明人： Yuuki Kamiura , Hiroshi Tobimatsu , Kouji Oda , Mahito Sawada , Koji Shibata , Hiroyuki Kawata
IPC分类号： H01L2131
CPC分类号： H01L21/76802 , H01L21/31144 , H01L21/76832 , H01L24/05 , H01L2924/351 , H01L2924/00
摘要： A method of manufacturing a semiconductor device is provided, which prevents a polyimide film from coming unstuck from a film to be subjected to isotropic etching, and further prevents deposits adhered to respective side faces of the films from coming off, during a heat treatment for imidizing the polyimide film. Isotropic etching is performed on a silicon nitride film 4 using, as a mask, a polyimide film 5 having a predetermined pattern formed therein. Next, a heat treatment is carried out to imidize the polyimide film 5 prior to performing anisotropic etching on a silicon oxide film 3. During the heat treatment for imidizing the polyimide film 5, since deposits, which are to be generated by anisotropic etching, are not yet adhered to the respective side faces of the films, the polyimide film 5 does not come unstuck from the silicon nitride film 4. Further, the deposits which are adhered to the respective side face of the films after the heat treatment will not come off.
摘要翻译：提供一种制造半导体器件的方法，其防止聚酰亚胺膜从薄膜脱落以进行各向同性蚀刻，并且进一步防止在用于酰亚胺化的热处理期间粘附到膜的各个侧面的沉积物脱落聚酰亚胺薄膜。在氮化硅膜4上进行各向同性蚀刻，使用形成有预定图案的聚酰亚胺膜5作为掩模。接下来，在对氧化硅膜3进行各向异性蚀刻之前，进行热处理以对聚酰亚胺膜5进行酰亚胺化。在酰亚胺化聚酰亚胺膜5的热处理中，由于通过各向异性蚀刻产生的沉积物为还没有粘附到膜的各个侧面，聚酰亚胺膜5不会从氮化硅膜4脱落。此外，附着在热处理后的膜的相应侧面的沉积物将不会脱落。

2. 发明授权

US06645859B1 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06645859B1
公开(公告)日：2003-11-11
申请号：US10170579
申请日：2002-06-14
申请人： Mahito Sawada , Hiroshi Tobimatsu , Kouji Oda , Yuuki Kamiura , Kouji Shibata , Hiroyuki Kawata
发明人： Mahito Sawada , Hiroshi Tobimatsu , Kouji Oda , Yuuki Kamiura , Kouji Shibata , Hiroyuki Kawata
IPC分类号： H01L2144
CPC分类号： H01L21/02164 , H01L21/022 , H01L21/02271 , H01L21/02274 , H01L21/31612 , H01L21/76832 , H01L21/76834 , H01L21/76837
摘要： A manufacturing method of a semiconductor device allowing successful filling of an insulating film by HDP-CVD (High Density Plasma-Chemical Vapor Deposition) in a gap or valley between densely placed interconnections is provided. The method includes the steps of forming semiconductor elements on a semiconductor substrate, forming on the semiconductor elements a plurality of interconnections with top protective layers side by side to electrically connect the semiconductor elements, forming a protective insulating film by CVD other than HDP-CVD to cover top and side surfaces of the interconnections and a bottom surface of a gap between the interconnections, and forming an insulating film by HDP-CVD to cover the protective insulating film and to fill in the gap between the interconnections covered with the protective insulating film.
摘要翻译：提供了通过HDP-CVD（高密度等离子体 - 化学气相沉积）在密集布置的互连之间的间隙或谷中成功地填充绝缘膜的半导体器件的制造方法。该方法包括以下步骤：在半导体衬底上形成半导体元件，在半导体元件上形成与顶部保护层并排的多个互连以电连接半导体元件，通过除HDP-CVD之外的CVD形成保护绝缘膜以形成保护绝缘膜互连的顶盖和侧表面以及互连之间的间隙的底表面，并且通过HDP-CVD形成绝缘膜以覆盖保护绝缘膜并填充被保护绝缘膜覆盖的互连之间的间隙。

3. 发明授权

US06759317B2 Method of manufacturing semiconductor device having passivation film and buffer coating film 失效
标题翻译：具有钝化膜和缓冲涂膜的半导体器件的制造方法
公开(公告)号：US06759317B2
公开(公告)日：2004-07-06
申请号：US09910824
申请日：2001-07-24
申请人： Hiroshi Tobimatsu , Yuuki Kamiura , Seiji Okura , Mahito Sawada
发明人： Hiroshi Tobimatsu , Yuuki Kamiura , Seiji Okura , Mahito Sawada
IPC分类号： H01L2144
CPC分类号： H01L21/76804
摘要： An interconnection is formed on a semiconductor substrate having a semiconductor element formed thereon. Next, a passivation film is formed on the semiconductor substrate including the interconnection. Further, a polyimide film, which is served as a buffer coating film, is formed on the passivation film. Further, the polyimide film is patterned. Next, the passivation film is subject to etching while the patterned polyimide film is taken as a mask. Next, a hardened layer, which is formed on the surface of the polyimide film as a result of etching, is removed through ashing process. Next, the semiconductor substrate after ashing process is cured so as to transform the polyimide film into imide.
摘要翻译：在其上形成有半导体元件的半导体衬底上形成互连。接下来，在包括互连的半导体衬底上形成钝化膜。此外，在钝化膜上形成用作缓冲涂膜的聚酰亚胺膜。此外，对聚酰亚胺膜进行图案化。接下来，在将图案化的聚酰亚胺膜作为掩模的同时，钝化膜进行蚀刻。接下来，通过灰化处理去除在聚酰亚胺膜的表面上形成的蚀刻结果的硬化层。接下来，使灰化处理后的半导体基板固化，将聚酰亚胺膜变为酰亚胺。

4. 发明申请

US20070096322A1 Interconnection structure of semiconductor device 失效
标题翻译：半导体器件的互连结构
公开(公告)号：US20070096322A1
公开(公告)日：2007-05-03
申请号：US11635495
申请日：2006-12-08
申请人： Koyu Asai , Hiroshi Tobimatsu , Hiroyuki Kawata , Mahito Sawada
发明人： Koyu Asai , Hiroshi Tobimatsu , Hiroyuki Kawata , Mahito Sawada
IPC分类号： H01L23/52
CPC分类号： H01L23/522 , H01L21/768 , H01L23/5226 , H01L23/53228 , H01L2924/0002 , H01L2924/00
摘要： An interconnection is provided with a dummy interconnection connected to an interconnection body, and the dummy interconnection is provided with a stress concentration portion in which tensile stress higher than that of the interconnection body is generated. In proximity to the stress concentration portion, an insulating film formed by high-density plasma CVD is provided, and the tensile stress is generated in the stress concentration portion by the insulating film. With this structure, the occurrence of a void can be prevented at any position in the interconnection body.
摘要翻译：互连设置有连接到互连体的虚拟互连，并且虚设互连设置有应力集中部，其中产生比互连体高的拉伸应力。在应力集中部分附近，设置通过高密度等离子体CVD形成的绝缘膜，并且通过绝缘膜在应力集中部分产生拉伸应力。利用这种结构，可以防止在互连体中的任何位置发生空隙。

5. 发明授权

US07489040B2 Interconnection structure of semiconductor device 失效
标题翻译：半导体器件的互连结构
公开(公告)号：US07489040B2
公开(公告)日：2009-02-10
申请号：US11635495
申请日：2006-12-08
申请人： Koyu Asai , Hiroshi Tobimatsu , Hiroyuki Kawata , Mahito Sawada
发明人： Koyu Asai , Hiroshi Tobimatsu , Hiroyuki Kawata , Mahito Sawada
IPC分类号： H01L23/48
CPC分类号： H01L23/522 , H01L21/768 , H01L23/5226 , H01L23/53228 , H01L2924/0002 , H01L2924/00
摘要： An interconnection is provided with a dummy interconnection connected to an interconnection body, and the dummy interconnection is provided with a stress concentration portion in which tensile stress higher than that of the interconnection body is generated. In proximity to the stress concentration portion, an insulating film formed by high-density plasma CVD is provided, and the tensile stress is generated in the stress concentration portion by the insulating film. With this structure, the occurrence of a void can be prevented at any position in the interconnection body.
摘要翻译：互连设置有连接到互连体的虚拟互连，并且虚设互连设置有应力集中部，其中产生比互连体高的拉伸应力。在应力集中部分附近，设置通过高密度等离子体CVD形成的绝缘膜，并且通过绝缘膜在应力集中部分产生拉伸应力。利用这种结构，可以防止在互连体中的任何位置发生空隙。

6. 发明授权

US07154184B2 Interconnection structure of semiconductor device 失效
公开(公告)号：US07154184B2
公开(公告)日：2006-12-26
申请号：US10725384
申请日：2003-12-03
申请人： Koyu Asai , Hiroshi Tobimatsu , Hiroyuki Kawata , Mahito Sawada
发明人： Koyu Asai , Hiroshi Tobimatsu , Hiroyuki Kawata , Mahito Sawada
IPC分类号： H01L23/48
CPC分类号： H01L23/522 , H01L21/768 , H01L23/5226 , H01L23/53228 , H01L2924/0002 , H01L2924/00
摘要： An interconnection is provided with a dummy interconnection connected to an interconnection body, and the dummy interconnection is provided with a stress concentration portion in which tensile stress higher than that of the interconnection body is generated. In proximity to the stress concentration portion, an insulating film formed by high-density plasma CVD is provided, and the tensile stress is generated in the stress concentration portion by the insulating film. With this structure, the occurrence of a void can be prevented at any position in the interconnection body.

7. 发明申请

US20110092037A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110092037A1
公开(公告)日：2011-04-21
申请号：US12977573
申请日：2010-12-23
申请人： Tadashi Yamaguchi , Koyu Asai , Mahito Sawada , Kiyoteru Kobayashi , Tatsunori Murata , Satoshi Shimizu
发明人： Tadashi Yamaguchi , Koyu Asai , Mahito Sawada , Kiyoteru Kobayashi , Tatsunori Murata , Satoshi Shimizu
IPC分类号： H01L21/336
CPC分类号： H01L21/76802 , H01L21/76801 , H01L21/76828 , H01L21/76829 , H01L21/76837 , H01L23/53295 , H01L23/564 , H01L2924/0002 , H01L2924/13091 , H01L2924/00
摘要： In order to block hydrogen ions produced when forming an interlayer insulating film by HDP-CVD or the like to thereby suppress an adverse effect of the hydrogen ions on a device, in a semiconductor device including a contact layer, a metal interconnection and an interlayer insulating film on a semiconductor substrate having a gate electrode formed thereon, the interlayer insulating film is formed on the metal interconnection by bias-applied plasma CVD using source gas containing hydrogen atoms, and a silicon oxynitride film is provided in the underlayer of the metal interconnection and the interlayer insulating film.
摘要翻译：为了阻止通过HDP-CVD等形成层间绝缘膜时产生的氢离子，从而抑制氢离子对器件的不利影响，在包括接触层，金属互连和层间绝缘的半导体器件中在其上形成有栅电极的半导体衬底上，通过使用含氢原子的气体的偏压施加等离子体CVD在金属互连上形成层间绝缘膜，并且在金属互连的底层设置氮氧化硅膜，层间绝缘膜。

8. 发明申请

US20060081992A1 Semiconductor device with a fluorinated silicate glass film as an interlayer metal dielectric film, and manufacturing method thereof 审中-公开
公开(公告)号：US20060081992A1
公开(公告)日：2006-04-20
申请号：US11291994
申请日：2005-12-02
申请人： Seiji Okura , Koji Oda , Mahito Sawada
发明人： Seiji Okura , Koji Oda , Mahito Sawada
IPC分类号： H01L23/52
CPC分类号： H01L23/53295 , H01L21/76825 , H01L21/76826 , H01L21/76829 , H01L21/76834 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A plurality of metal wire layers consisting of a first metal wire layer and a second metal wire layer are formed on a semiconductor substrate. A fluorinated silicate glass film serving as an interlayer metal dielectric film is formed between the first and second metal wire layers. A silicon nitride film serving as a protective insulation film is formed on the fluorinated silicate glass film layer. An adhesive layer made of, for example, a P-SiO film, P-SiON film, or PE-SiO film, is formed between the fluorinated silicate glass film and the silicon nitride film.

9. 发明授权

US06579787B2 Semiconductor device with a fluorinated silicate glass film as an interlayer metal dielectric film, and manufacturing method thereof 有权
公开(公告)号：US06579787B2
公开(公告)日：2003-06-17
申请号：US09802951
申请日：2001-03-12
申请人： Seiji Okura , Koji Oda , Mahito Sawada
发明人： Seiji Okura , Koji Oda , Mahito Sawada
IPC分类号： H01L214763
CPC分类号： H01L23/53295 , H01L21/76825 , H01L21/76826 , H01L21/76829 , H01L21/76834 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A plurality of metal wire layers consisting of a first metal wire layer and a second metal wire layer are formed on a semiconductor substrate. A fluorinated silicate glass film serving as an interlayer metal dielectric film is formed between the first and second metal wire layers. A silicon nitride film serving as a protective insulation film is formed on the fluorinated silicate glass film layer. An adhesive layer made of, for example, a P—SiO film, P—SiON film, or PE—SiO film, is formed between the fluorinated silicate glass film and the silicon nitride film.

10. 发明授权

US06213852B1 Polishing apparatus and method of manufacturing a semiconductor device using the same 失效
标题翻译：抛光装置及其制造方法
公开(公告)号：US06213852B1
公开(公告)日：2001-04-10
申请号：US09350920
申请日：1999-07-12
申请人： Kazuyuki Fujii , Takanori Sasaki , Mahito Sawada , Kouichiro Tsutahara
发明人： Kazuyuki Fujii , Takanori Sasaki , Mahito Sawada , Kouichiro Tsutahara
IPC分类号： B24B2900
CPC分类号： B24B37/04 , B24B57/02
摘要： A method of manufacturing a semiconductor device using a polishing apparatus is provided. A top ring holding a wafer is arranged on a pad. A polishing chemical liquid supply line for supplying a polishing chemical liquid is arranged above the pad in a direction ahead of rotation with respect to the top ring. Around the center of rotation of the pad, a partition plate having a columnar side surface is arranged. Above the pad on a side which goes away from the top ring when the pad is rotated, a polishing chemical liquid draining mechanism is arranged extending continuously from the partition plate to the outer periphery of the pad. Accordingly, a polishing apparatus is obtained by which the amount of polishing of the surface to be polished of the semiconductor substrate is stabilized and generation of microscratches on the surface to be polished can be suppressed.
摘要翻译：提供了使用抛光装置制造半导体器件的方法。保持晶片的顶环布置在垫上。用于供给研磨用化学液的研磨用药液供给配线相对于上述环设置在相对于上述旋转方向的方向上。围绕垫的旋转中心，布置有具有柱状侧表面的隔板。在衬垫旋转时离开顶环的一侧的衬垫上方，抛光化学液排放机构被布置成从隔板连续延伸到衬垫的外周。因此，可以获得能够稳定半导体基板的被研磨面的研磨量并且能够抑制待研磨面的微细化的研磨装置。

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