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1. 发明授权

US08703368B2 Lithography process 有权
标题翻译：平版印刷工艺
公开(公告)号：US08703368B2
公开(公告)日：2014-04-22
申请号：US13550036
申请日：2012-07-16
申请人： Yung-Yao Lee , Ying Ying Wang , Heng-Hsin Liu , Chin-Hsiang Lin
发明人： Yung-Yao Lee , Ying Ying Wang , Heng-Hsin Liu , Chin-Hsiang Lin
IPC分类号： G03F9/00
CPC分类号： G03F7/70633
摘要： A process for use in lithography, such as photolithography for patterning a semiconductor wafer, is disclosed. The process includes receiving an incoming semiconductor wafer having various features and layers formed thereon. A unit-induced overlay (uniiOVL) correction is received and a deformation measurement is performed on the incoming semiconductor wafer in an overlay module. A deformation-induced overlay (defiOVL) correction is generated from the deformation measurement results by employing a predetermined algorithm on the deformation measurement results. The defiOVL and uniiOVL corrections are fed-forward to an exposure module and an exposure process is performed on the incoming semiconductor wafer.
摘要翻译：公开了一种用于光刻的方法，例如用于图案化半导体晶片的光刻技术。该方法包括接收具有形成在其上的各种特征和层的输入半导体晶片。接收单元引起的覆盖（uniOVL）校正，并且在覆盖模块中对输入的半导体晶片进行变形测量。通过对变形测量结果采用预定的算法，从变形测量结果生成变形诱导的覆盖（defiOVL）校正。 defiVV和unioVL校正被反馈到曝光模块，并且对输入的半导体晶片进行曝光处理。

2. 发明申请

US20140017604A1 LITHOGRAPHY PROCESS 有权
标题翻译： LITHOGRAPHY过程
公开(公告)号：US20140017604A1
公开(公告)日：2014-01-16
申请号：US13550036
申请日：2012-07-16
申请人： Yung-Yao Lee , Ying Ying Wang , Heng-Hsin Liu , Chin-Hsiang Lin
发明人： Yung-Yao Lee , Ying Ying Wang , Heng-Hsin Liu , Chin-Hsiang Lin
IPC分类号： G03F7/20
CPC分类号： G03F7/70633
摘要： A process for use in lithography, such as photolithography for patterning a semiconductor wafer, is disclosed. The process includes receiving an incoming semiconductor wafer having various features and layers formed thereon. A unit-induced overlay (uniiOVL) correction is received and a deformation measurement is performed on the incoming semiconductor wafer in an overlay module. A deformation-induced overlay (defiOVL) correction is generated from the deformation measurement results by employing a predetermined algorithm on the deformation measurement results. The defiOVL and uniiOVL corrections are fed-forward to an exposure module and an exposure process is performed on the incoming semiconductor wafer.
摘要翻译：公开了一种用于光刻的方法，例如用于图案化半导体晶片的光刻技术。该方法包括接收具有形成在其上的各种特征和层的输入半导体晶片。接收单元引起的覆盖（uniOVL）校正，并且在覆盖模块中对输入的半导体晶片进行变形测量。通过对变形测量结果采用预定的算法，从变形测量结果生成变形诱导的覆盖（defiOVL）校正。 defiVV和unioVL校正被反馈到曝光模块，并且对输入的半导体晶片进行曝光处理。

3. 发明申请

US20130286395A1 Tool Induced Shift Reduction Determination for Overlay Metrology 有权
标题翻译：刀具诱导换位测量用于覆盖计量学
公开(公告)号：US20130286395A1
公开(公告)日：2013-10-31
申请号：US13457832
申请日：2012-04-27
申请人： Yung-Yao Lee , Ying Ying Wang , Heng-Hsin Liu , Heng-Jen Lee
发明人： Yung-Yao Lee , Ying Ying Wang , Heng-Hsin Liu , Heng-Jen Lee
IPC分类号： G01B11/00
CPC分类号： G01B11/00 , G03F7/70633
摘要： One embodiment relates to a method for semiconductor workpiece processing. In this method, a baseline tool induced shift (TIS) is measured by performing a baseline number of TIS measurements on a first semiconductor workpiece. After the baseline TIS has been determined, the method determines a subsequent TIS based on a subsequent number of TIS measurements taken on a first subsequent semiconductor workpiece. The subsequent number of TIS measurements is less than the baseline number of TIS measurements.
摘要翻译：一个实施例涉及一种用于半导体工件加工的方法。在该方法中，通过在第一半导体工件上执行TIS测量的基线数量来测量基线工具诱发位移（TIS）。在确定基线TIS之后，该方法基于在第一后续半导体工件上进行的随后的TIS测量数确定随后的TIS。随后的TIS测量数量小于TIS测量的基线数量。

4. 发明授权

US08860941B2 Tool induced shift reduction determination for overlay metrology 有权
标题翻译：刀具诱导移位减少确定重叠度量
公开(公告)号：US08860941B2
公开(公告)日：2014-10-14
申请号：US13457832
申请日：2012-04-27
申请人： Yung-Yao Lee , Ying Ying Wang , Heng-Hsin Liu , Heng-Jen Lee
发明人： Yung-Yao Lee , Ying Ying Wang , Heng-Hsin Liu , Heng-Jen Lee
IPC分类号： G01B11/00
CPC分类号： G01B11/00 , G03F7/70633
摘要： One embodiment relates to a method for semiconductor workpiece processing. In this method, a baseline tool induced shift (TIS) is measured by performing a baseline number of TIS measurements on a first semiconductor workpiece. After the baseline TIS has been determined, the method determines a subsequent TIS based on a subsequent number of TIS measurements taken on a first subsequent semiconductor workpiece. The subsequent number of TIS measurements is less than the baseline number of TIS measurements.
摘要翻译：一个实施例涉及一种用于半导体工件加工的方法。在该方法中，通过在第一半导体工件上执行TIS测量的基线数量来测量基线工具诱发位移（TIS）。在确定基线TIS之后，该方法基于在第一后续半导体工件上进行的随后的TIS测量数确定随后的TIS。随后的TIS测量数量小于TIS测量的基线数量。

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