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1. 发明授权

US08581655B2 Clock signal supplying method and circuit for shift registers 有权
标题翻译：时钟信号提供方法和移位寄存器电路
公开(公告)号：US08581655B2
公开(公告)日：2013-11-12
申请号：US13270382
申请日：2011-10-11
申请人： Yung-Chih Chen , Kuo-Chang Su , Chun-Huan Chang , Yu-Chung Yang
发明人： Yung-Chih Chen , Kuo-Chang Su , Chun-Huan Chang , Yu-Chung Yang
IPC分类号： G06F1/04
CPC分类号： G09G3/3677 , G09G2300/0408 , G09G2300/0417 , G09G2310/0286 , G11C19/00
摘要： A clock signal supplying method for shift registers includes following steps: receiving a clock signal; and transmitting the clock signal to two first stage signal transmission paths simultaneously, the first stage signal transmission paths determined by a first control signal whether to be conducted, and further conducted at different time.
摘要翻译：用于移位寄存器的时钟信号提供方法包括以下步骤：接收时钟信号; 并且将时钟信号同时发送到两个第一级信号传输路径，由第一控制信号确定的第一级信号传输路径是否被导通，并且在不同的时间进一步进行。

2. 发明申请

US20120161842A1 CLOCK SIGNAL SUPPLYING METHOD AND CIRCUIT FOR SHIFT REGISTERS 有权
标题翻译：用于移位寄存器的时钟信号提供方法和电路
公开(公告)号：US20120161842A1
公开(公告)日：2012-06-28
申请号：US13270382
申请日：2011-10-11
申请人： Yung-Chih CHEN , Kuo-Chang Su , Chun-Huan Chang , Yu-Chung Yang
发明人： Yung-Chih CHEN , Kuo-Chang Su , Chun-Huan Chang , Yu-Chung Yang
IPC分类号： G06F1/04
CPC分类号： G09G3/3677 , G09G2300/0408 , G09G2300/0417 , G09G2310/0286 , G11C19/00
摘要： A clock signal supplying method for shift registers includes following steps: receiving a clock signal; and transmitting the clock signal to two first stage signal transmission paths simultaneously, the first stage signal transmission paths determined by a first control signal whether to be conducted, and further conducted at different time.
摘要翻译：用于移位寄存器的时钟信号提供方法包括以下步骤：接收时钟信号; 并且将时钟信号同时发送到两个第一级信号传输路径，由第一控制信号确定的第一级信号传输路径是否被导通，并且在不同的时间进一步进行。

3. 发明授权

US08325127B2 Shift register and architecture of same on a display panel 有权
标题翻译：移位寄存器和结构在显示面板上
公开(公告)号：US08325127B2
公开(公告)日：2012-12-04
申请号：US12823237
申请日：2010-06-25
申请人： Chun-Huan Chang , Kuo-Chang Su , Yung-Chih Chen , Chun-Hsin Liu
发明人： Chun-Huan Chang , Kuo-Chang Su , Yung-Chih Chen , Chun-Hsin Liu
IPC分类号： G06F3/038 , G11C19/00
CPC分类号： G11C19/287 , G09G3/20 , G09G3/3677 , G09G2310/0205 , G09G2310/0281 , G09G2310/0286 , G09G2310/0297 , G09G2310/06
摘要： The present invention relates to a shift register and GOA architecture of the same in a display panel comprising a substrate and a plurality of pixels spatially formed on the substrate defining a number of pixel rows, each pixel row having a height of H. The shift register has the plurality of shift register stages disposed spatially and sequentially on the substrate in such a way that the layout of each shift register stage has a height of (j*H), j being an integer greater than one. Each shift register stages is configured to generate j scanning signals for driving j neighboring pixel rows, respectively.
摘要翻译：本发明涉及一种显示面板中的移位寄存器和GOA结构，包括基板和空间上形成在衬底上的多个像素，其限定多个像素行，每个像素行具有高度H.移位寄存器具有多个移位寄存器级，以这样的方式在基板上空间和顺序地布置，使得每个移位寄存器级的布局具有（j * H）的高度，j是大于1的整数。每个移位寄存器级被配置为分别产生用于驱动j个相邻像素行的j个扫描信号。

4. 发明申请

US20110316833A1 Shift Register and Architecture of Same on a Display Panel 有权
标题翻译：移位寄存器和显示面板上的相同结构
公开(公告)号：US20110316833A1
公开(公告)日：2011-12-29
申请号：US12823237
申请日：2010-06-25
申请人： Chun-Huan Chang , Kuo-Chang Su , Yung-Chih Chen , Chun-Hsin Liu
发明人： Chun-Huan Chang , Kuo-Chang Su , Yung-Chih Chen , Chun-Hsin Liu
IPC分类号： G06F3/038 , G11C19/00
CPC分类号： G11C19/287 , G09G3/20 , G09G3/3677 , G09G2310/0205 , G09G2310/0281 , G09G2310/0286 , G09G2310/0297 , G09G2310/06
摘要： The present invention relates to a shift register and GOA architecture of the same in a display panel comprising a substrate and a plurality of pixels spatially formed on the substrate defining a number of pixel rows, each pixel row having a height of H. The shift register has the plurality of shift register stages disposed spatially and sequentially on the substrate in such a way that the layout of each shift register stage has a height of (j*H), j being an integer greater than one. Each shift register stages is configured to generate j scanning signals for driving j neighboring pixel rows, respectively.
摘要翻译：本发明涉及一种显示面板中的移位寄存器和GOA结构，包括基板和空间上形成在衬底上的多个像素，其限定多个像素行，每个像素行具有高度H.移位寄存器具有多个移位寄存器级，以这样的方式在基板上空间和顺序地布置，使得每个移位寄存器级的布局具有（j * H）的高度，j是大于1的整数。每个移位寄存器级被配置为分别产生用于驱动j个相邻像素行的j个扫描信号。

5. 发明授权

US08494108B2 Switch device and shift register circuit using the same 有权
标题翻译：开关器件和移位寄存器电路使用相同
公开(公告)号：US08494108B2
公开(公告)日：2013-07-23
申请号：US13186489
申请日：2011-07-20
申请人： Kuo-Hua Hsu , Yung-Chih Chen , Chun-Huan Chang
发明人： Kuo-Hua Hsu , Yung-Chih Chen , Chun-Huan Chang
IPC分类号： G11C19/00
CPC分类号： G11C19/28 , G09G3/3677 , G09G2300/0408 , G09G2310/0283 , G09G2310/0286 , G09G2330/021
摘要： A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes an input unit and a pull-up unit. The pull-up unit is utilized for pulling up a gate signal according to a system clock and a driving control voltage. The input unit is employed for outputting the driving control voltage according to a control signal and an input signal. The input unit includes a switch device having a first transistor and a second transistor. The first transistor has a first end for receiving the input signal, a gate end for receiving the control signal, and a second end. The second transistor has a first end electrically connected to the second end of the first transistor, a gate end electrically connected to the first end of the first transistor, and a second end for outputting the driving control voltage.
摘要翻译：移位寄存器电路包括用于提供多个门信号的多个移位寄存器级。每个移位寄存器级包括输入单元和上拉单元。上拉单元用于根据系统时钟和驱动控制电压提升门信号。输入单元用于根据控制信号和输入信号输出驱动控制电压。输入单元包括具有第一晶体管和第二晶体管的开关器件。第一晶体管具有用于接收输入信号的第一端，用于接收控制信号的门极端和第二端。第二晶体管具有电连接到第一晶体管的第二端的第一端，电连接到第一晶体管的第一端的栅极端和用于输出驱动控制电压的第二端。

6. 发明申请

US20120170707A1 SWITCH DEVICE AND SHIFT REGISTER CIRCUIT USING THE SAME 有权
标题翻译：切换装置和移位寄存器电路
公开(公告)号：US20120170707A1
公开(公告)日：2012-07-05
申请号：US13186489
申请日：2011-07-20
申请人： Kuo-Hua Hsu , Yung-Chih Chen , Chun-Huan Chang
发明人： Kuo-Hua Hsu , Yung-Chih Chen , Chun-Huan Chang
IPC分类号： G11C19/28 , H03K17/687
CPC分类号： G11C19/28 , G09G3/3677 , G09G2300/0408 , G09G2310/0283 , G09G2310/0286 , G09G2330/021
摘要： A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes an input unit and a pull-up unit. The pull-up unit is utilized for pulling up a gate signal according to a system clock and a driving control voltage. The input unit is employed for outputting the driving control voltage according to a control signal and an input signal. The input unit includes a switch device having a first transistor and a second transistor. The first transistor has a first end for receiving the input signal, a gate end for receiving the control signal, and a second end. The second transistor has a first end electrically connected to the second end of the first transistor, a gate end electrically connected to the first end of the first transistor, and a second end for outputting the driving control voltage.
摘要翻译：移位寄存器电路包括用于提供多个门信号的多个移位寄存器级。每个移位寄存器级包括输入单元和上拉单元。上拉单元用于根据系统时钟和驱动控制电压提升门信号。输入单元用于根据控制信号和输入信号输出驱动控制电压。输入单元包括具有第一晶体管和第二晶体管的开关器件。第一晶体管具有用于接收输入信号的第一端，用于接收控制信号的门极端和第二端。第二晶体管具有电连接到第一晶体管的第二端的第一端，电连接到第一晶体管的第一端的栅极端和用于输出驱动控制电压的第二端。

7. 发明申请

US20120320021A1 DISPLAY PANEL AND GATE DRIVING CIRCUIT AND DRIVING METHOD FOR GATE DRIVING CIRCUIT 有权
标题翻译：显示面板和门驱动电路及门驱动电路的驱动方法
公开(公告)号：US20120320021A1
公开(公告)日：2012-12-20
申请号：US13363458
申请日：2012-02-01
申请人： Chun-Huan Chang , Wan-Jung Chen , Yu-Chung Yang
发明人： Chun-Huan Chang , Wan-Jung Chen , Yu-Chung Yang
IPC分类号： G06F3/038 , G09G5/00
CPC分类号： G09G3/3655 , G09G3/3677 , G09G2310/0286 , G09G2310/08 , G11C19/28
摘要： An exemplary gate driving circuit is adapted for driving a display panel including multiple pixels and includes a first gate driving unit string and a second gate driving unit string. The first gate driving unit string includes multiple cascade-connected first gate driving units and receives a start pulse. The first gate driving units are for generating output pulses to drive the pixels. The second gate driving unit string includes multiple cascade-connected second gate driving units and receives the start pulse. The second gate driving units are for generating output pulses to drive the pixels. The output pulse generated from one of the second gate driving units is provided to one of first gate driving units to determine whether to disable the output pulse of the first gate driving unit which receives the output pulse generated from the second gate driving units.
摘要翻译：示例性栅极驱动电路适于驱动包括多个像素的显示面板，并且包括第一栅极驱动单元串和第二栅极驱动单元串。第一栅极驱动单元串包括多个级联连接的第一栅极驱动单元并接收起始脉冲。第一门驱动单元用于产生用于驱动像素的输出脉冲。第二栅极驱动单元串包括多个级联连接的第二栅极驱动单元并接收起始脉冲。第二栅极驱动单元用于产生用于驱动像素的输出脉冲。从第二栅极驱动单元之一产生的输出脉冲被提供给第一栅极驱动单元中的一个，以确定是否禁止接收从第二栅极驱动单元产生的输出脉冲的第一栅极驱动单元的输出脉冲。

8. 发明授权

US08711132B2 Display panel and gate driving circuit and driving method for gate driving circuit 有权
标题翻译：栅极驱动电路的显示面板和栅极驱动电路及驱动方法
公开(公告)号：US08711132B2
公开(公告)日：2014-04-29
申请号：US13363458
申请日：2012-02-01
申请人： Chun-Huan Chang , Wan-Jung Chen , Yu-Chung Yang
发明人： Chun-Huan Chang , Wan-Jung Chen , Yu-Chung Yang
IPC分类号： G06F3/038
CPC分类号： G09G3/3655 , G09G3/3677 , G09G2310/0286 , G09G2310/08 , G11C19/28
摘要： An exemplary gate driving circuit is adapted for driving a display panel including multiple pixels and includes a first gate driving unit string and a second gate driving unit string. The first gate driving unit string includes multiple cascade-connected first gate driving units and receives a start pulse. The first gate driving units are for generating output pulses to drive the pixels. The second gate driving unit string includes multiple cascade-connected second gate driving units and receives the start pulse. The second gate driving units are for generating output pulses to drive the pixels. The output pulse generated from one of the second gate driving units is provided to one of first gate driving units to determine whether to disable the output pulse of the first gate driving unit which receives the output pulse generated from the second gate driving units.
摘要翻译：示例性栅极驱动电路适于驱动包括多个像素的显示面板，并且包括第一栅极驱动单元串和第二栅极驱动单元串。第一栅极驱动单元串包括多个级联连接的第一栅极驱动单元并接收起始脉冲。第一门驱动单元用于产生用于驱动像素的输出脉冲。第二栅极驱动单元串包括多个级联连接的第二栅极驱动单元并接收起始脉冲。第二栅极驱动单元用于产生用于驱动像素的输出脉冲。从第二栅极驱动单元之一产生的输出脉冲被提供给第一栅极驱动单元中的一个，以确定是否禁止接收从第二栅极驱动单元产生的输出脉冲的第一栅极驱动单元的输出脉冲。

9. 发明授权

US08890785B2 Display panel and gate driving circuit thereof 有权
标题翻译：显示面板及其栅极驱动电路
公开(公告)号：US08890785B2
公开(公告)日：2014-11-18
申请号：US13449322
申请日：2012-04-18
申请人： Kun-Yueh Lin , Chun-Hsin Liu , Chun-Huan Chang , Ya-Ting Lin
发明人： Kun-Yueh Lin , Chun-Hsin Liu , Chun-Huan Chang , Ya-Ting Lin
IPC分类号： G09G3/36 , G09G3/20
CPC分类号： G09G3/3659 , G09G3/2074 , G09G2310/0286
摘要： A display panel and its gate driving circuit are provided. The gate driving circuit includes a plurality of shift registers. Each of the shift registers includes a first scan signal generator for generating a first scan signal, a second scan signal generator for generating a second scan signal, a first control unit for generating a first control signal, and a second control unit for generating a second control signal. Here, the first control signal and the second control signal are shared by the first scan signal generator and the second scan signal generator. Based on the above, the abatement of signal intensity of the first scan signal and the second scan signal caused by circuit sharing can be precluded, and a chip area occupied by each of the shift registers can be reduced.
摘要翻译：提供显示面板及其栅极驱动电路。栅极驱动电路包括多个移位寄存器。每个移位寄存器包括用于产生第一扫描信号的第一扫描信号发生器，用于产生第二扫描信号的第二扫描信号发生器，用于产生第一控制信号的第一控制单元和产生第二扫描信号的第二扫描信号的第二控制单元控制信号。这里，第一控制信号和第二控制信号由第一扫描信号发生器和第二扫描信号发生器共享。基于上述，可以排除由电路共享引起的第一扫描信号和第二扫描信号的信号强度的减少，并且可以减少每个移位寄存器占用的码片区域。

10. 发明授权

US08314766B2 Liquid crystal display panel 有权
标题翻译：液晶显示面板
公开(公告)号：US08314766B2
公开(公告)日：2012-11-20
申请号：US12404352
申请日：2009-03-16
申请人： Chun-Huan Chang
发明人： Chun-Huan Chang
IPC分类号： G02F1/13 , G02F1/1345 , G09G3/36
CPC分类号： G09G3/3648 , G09G2300/0426 , G09G2310/0232 , G09G2320/0233
摘要： A liquid crystal display panel includes a display area, a wiring area, and an external circuit area, wherein the wiring area is between the display area and the external circuit area. The liquid crystal display panel includes many pixel structures, external pads and wiring sets. Each wiring set includes a plurality of upper-layer main wires disposed on one plane and lower-layer main wires disposed on another plane, wherein the two planes are parallel. In addition, each upper-layer main wire corresponds to one lower-layer main wire and the shadow which the upper-layer main wire vertically projects on the surface overlaps a part of the corresponding lower-layer main wire. The light leakage around the display area can be eliminated by proper arrangement of main wiring sets, and therefore the display quality is improved.
摘要翻译：液晶显示面板包括显示区域，布线区域和外部电路区域，其中布线区域在显示区域和外部电路区域之间。液晶显示面板包括许多像素结构，外部焊盘和接线组。每个布线组包括设置在一个平面上的多个上层主线和设置在另一平面上的下层主线，其中两个平面平行。此外，每个上层主线对应于一个下层主线，并且上层主线垂直突出在该表面上的阴影与相应的下层主线的一部分重叠。可以通过适当布置主布线组来消除显示区周围的漏光，从而提高显示质量。

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