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1. 发明授权

US09087492B2 Bus-line arrangement in a gate driver 有权
标题翻译：总线排列在门驱动器中
公开(公告)号：US09087492B2
公开(公告)日：2015-07-21
申请号：US13453581
申请日：2012-04-23
申请人： Chun Huan Chang , Chun-Hsin Liu , Kun-Yueh Lin , Ya-Ting Lin
发明人： Chun Huan Chang , Chun-Hsin Liu , Kun-Yueh Lin , Ya-Ting Lin
IPC分类号： G06F3/038 , G09G3/36 , G06F17/50 , G06F1/10
CPC分类号： G09G3/3677 , G06F1/10 , G06F17/5077 , G09G2300/0426 , G09G2310/0205
摘要： A method for use in a display panel is disclosed. The method includes providing M bus lines in the bus area for receiving a plurality of clock signals, M being a positive integer greater than 3; providing a plurality of signal lines to separately provide the clock signals from the M bus line to the circuit area, the circuit area configured to provide the plurality of sequential gate line signals in response to the clock signals, the plurality of signal lines including a plurality of adjacent signal-line pairs, each adjacent signal-line pair having a resistance difference, said signal lines including a maximum resistance value and a minimum resistance value, and wherein the M bus lines are arranged such that the resistance difference in any one of the adjacent signal-line pairs is smaller than a value difference between the maximum resistance value and the minimum resistance value.
摘要翻译：公开了一种在显示面板中使用的方法。该方法包括在总线区域中提供M个总线线路，用于接收多个时钟信号，M为大于3的正整数; 提供多条信号线，以将来自M总线的时钟信号分别提供给电路区域，电路区域被配置为响应于时钟信号提供多个顺序的栅极线信号，多个信号线包括多个相邻的信号线对，每个相邻的信号线对具有电阻差，所述信号线包括最大电阻值和最小电阻值，并且其中M总线布置成使得所述M个总线线路中的任一个中的电阻差相邻的信号线对小于最大电阻值和最小电阻值之间的值差。

2. 发明授权

US08890785B2 Display panel and gate driving circuit thereof 有权
标题翻译：显示面板及其栅极驱动电路
公开(公告)号：US08890785B2
公开(公告)日：2014-11-18
申请号：US13449322
申请日：2012-04-18
申请人： Kun-Yueh Lin , Chun-Hsin Liu , Chun-Huan Chang , Ya-Ting Lin
发明人： Kun-Yueh Lin , Chun-Hsin Liu , Chun-Huan Chang , Ya-Ting Lin
IPC分类号： G09G3/36 , G09G3/20
CPC分类号： G09G3/3659 , G09G3/2074 , G09G2310/0286
摘要： A display panel and its gate driving circuit are provided. The gate driving circuit includes a plurality of shift registers. Each of the shift registers includes a first scan signal generator for generating a first scan signal, a second scan signal generator for generating a second scan signal, a first control unit for generating a first control signal, and a second control unit for generating a second control signal. Here, the first control signal and the second control signal are shared by the first scan signal generator and the second scan signal generator. Based on the above, the abatement of signal intensity of the first scan signal and the second scan signal caused by circuit sharing can be precluded, and a chip area occupied by each of the shift registers can be reduced.
摘要翻译：提供显示面板及其栅极驱动电路。栅极驱动电路包括多个移位寄存器。每个移位寄存器包括用于产生第一扫描信号的第一扫描信号发生器，用于产生第二扫描信号的第二扫描信号发生器，用于产生第一控制信号的第一控制单元和产生第二扫描信号的第二扫描信号的第二控制单元控制信号。这里，第一控制信号和第二控制信号由第一扫描信号发生器和第二扫描信号发生器共享。基于上述，可以排除由电路共享引起的第一扫描信号和第二扫描信号的信号强度的减少，并且可以减少每个移位寄存器占用的码片区域。

3. 发明申请

US20130100006A1 DISPLAY PANEL AND GATE DRIVING CIRCUIT THEREOF 有权
标题翻译：显示面板和门驱动电路
公开(公告)号：US20130100006A1
公开(公告)日：2013-04-25
申请号：US13449322
申请日：2012-04-18
申请人： Kun-Yueh Lin , Chun-Hsin Liu , Chun-Huan Chang , Ya-Ting Lin
发明人： Kun-Yueh Lin , Chun-Hsin Liu , Chun-Huan Chang , Ya-Ting Lin
IPC分类号： G09G3/36
CPC分类号： G09G3/3659 , G09G3/2074 , G09G2310/0286
摘要： A display panel and its gate driving circuit are provided. The gate driving circuit includes a plurality of shift registers. Each of the shift registers includes a first scan signal generator for generating a first scan signal, a second scan signal generator for generating a second scan signal, a first control unit for generating a first control signal, and a second control unit for generating a second control signal. Here, the first control signal and the second control signal are shared by the first scan signal generator and the second scan signal generator. Based on the above, the abatement of signal intensity of the first scan signal and the second scan signal caused by circuit sharing can be precluded, and a chip area occupied by each of the shift registers can be reduced.
摘要翻译：提供显示面板及其栅极驱动电路。栅极驱动电路包括多个移位寄存器。每个移位寄存器包括用于产生第一扫描信号的第一扫描信号发生器，用于产生第二扫描信号的第二扫描信号发生器，用于产生第一控制信号的第一控制单元和产生第二扫描信号的第二扫描信号的第二控制单元控制信号。这里，第一控制信号和第二控制信号由第一扫描信号发生器和第二扫描信号发生器共享。基于上述，可以排除由电路共享引起的第一扫描信号和第二扫描信号的信号强度的减少，并且可以减少每个移位寄存器占用的码片区域。

4. 发明授权

US08411007B2 LCD display visual enhancement driving circuit and method 有权
标题翻译：液晶显示器视觉增强驱动电路及方法
公开(公告)号：US08411007B2
公开(公告)日：2013-04-02
申请号：US12660315
申请日：2010-02-23
申请人： Yung-Chih Chen , Yu-Chung Yang , Kun-Yueh Lin , Chun-Hsin Liu
发明人： Yung-Chih Chen , Yu-Chung Yang , Kun-Yueh Lin , Chun-Hsin Liu
IPC分类号： G09G3/36
CPC分类号： G09G3/3648 , G09G2300/0443 , G09G2300/0447 , G09G2300/0814 , G09G2300/0852 , G09G2300/0876 , G09G2310/0251 , G09G2320/0242 , G09G2320/028
摘要： A pixel in a liquid crystal display panel comprises a first sub-pixel area having a first sub-pixel electrode and a second sub-pixel area having a second sub-pixel electrode. Each sub-pixel electrode is associated with a capacitor. When a gate-line signal and a data voltage is provided to the pixel, the voltage level on the first sub-pixel electrode is substantially equal to or slightly higher than the voltage level on the second sub-pixel electrode and the capacitor associated with each sub-pixel electrode is charged. When the gate-line signal has entirely passed on partially passed, a circuit element causes the capacitor associated with the second sub-pixel electrode to transfer its charge to another capacitor, resulting in a reduction of the voltage level on the second sub-pixel electrode.
摘要翻译：液晶显示面板中的像素包括具有第一子像素电极的第一子像素区域和具有第二子像素电极的第二子像素区域。每个子像素电极与电容器相关联。当向像素提供栅极线信号和数据电压时，第一子像素电极上的电压电平基本上等于或略高于第二子像素电极和与每个子像素电极相关联的电容器的电压电平子像素电极被充电。当栅极线信号完全通过时，电路元件使与第二子像素电极相关联的电容器将其电荷转移到另一个电容器，导致第二子像素电极上的电压电平降低。

5. 发明授权

US08325127B2 Shift register and architecture of same on a display panel 有权
标题翻译：移位寄存器和结构在显示面板上
公开(公告)号：US08325127B2
公开(公告)日：2012-12-04
申请号：US12823237
申请日：2010-06-25
申请人： Chun-Huan Chang , Kuo-Chang Su , Yung-Chih Chen , Chun-Hsin Liu
发明人： Chun-Huan Chang , Kuo-Chang Su , Yung-Chih Chen , Chun-Hsin Liu
IPC分类号： G06F3/038 , G11C19/00
CPC分类号： G11C19/287 , G09G3/20 , G09G3/3677 , G09G2310/0205 , G09G2310/0281 , G09G2310/0286 , G09G2310/0297 , G09G2310/06
摘要： The present invention relates to a shift register and GOA architecture of the same in a display panel comprising a substrate and a plurality of pixels spatially formed on the substrate defining a number of pixel rows, each pixel row having a height of H. The shift register has the plurality of shift register stages disposed spatially and sequentially on the substrate in such a way that the layout of each shift register stage has a height of (j*H), j being an integer greater than one. Each shift register stages is configured to generate j scanning signals for driving j neighboring pixel rows, respectively.
摘要翻译：本发明涉及一种显示面板中的移位寄存器和GOA结构，包括基板和空间上形成在衬底上的多个像素，其限定多个像素行，每个像素行具有高度H.移位寄存器具有多个移位寄存器级，以这样的方式在基板上空间和顺序地布置，使得每个移位寄存器级的布局具有（j * H）的高度，j是大于1的整数。每个移位寄存器级被配置为分别产生用于驱动j个相邻像素行的j个扫描信号。

6. 发明申请

US20110316833A1 Shift Register and Architecture of Same on a Display Panel 有权
标题翻译：移位寄存器和显示面板上的相同结构
公开(公告)号：US20110316833A1
公开(公告)日：2011-12-29
申请号：US12823237
申请日：2010-06-25
申请人： Chun-Huan Chang , Kuo-Chang Su , Yung-Chih Chen , Chun-Hsin Liu
发明人： Chun-Huan Chang , Kuo-Chang Su , Yung-Chih Chen , Chun-Hsin Liu
IPC分类号： G06F3/038 , G11C19/00
CPC分类号： G11C19/287 , G09G3/20 , G09G3/3677 , G09G2310/0205 , G09G2310/0281 , G09G2310/0286 , G09G2310/0297 , G09G2310/06
摘要： The present invention relates to a shift register and GOA architecture of the same in a display panel comprising a substrate and a plurality of pixels spatially formed on the substrate defining a number of pixel rows, each pixel row having a height of H. The shift register has the plurality of shift register stages disposed spatially and sequentially on the substrate in such a way that the layout of each shift register stage has a height of (j*H), j being an integer greater than one. Each shift register stages is configured to generate j scanning signals for driving j neighboring pixel rows, respectively.
摘要翻译：本发明涉及一种显示面板中的移位寄存器和GOA结构，包括基板和空间上形成在衬底上的多个像素，其限定多个像素行，每个像素行具有高度H.移位寄存器具有多个移位寄存器级，以这样的方式在基板上空间和顺序地布置，使得每个移位寄存器级的布局具有（j * H）的高度，j是大于1的整数。每个移位寄存器级被配置为分别产生用于驱动j个相邻像素行的j个扫描信号。

7. 发明申请

US20120134460A1 LAYOUT STRUCTURE OF SHIFT REGISTER CIRCUIT 审中-公开
标题翻译：移位寄存器电路的布局结构
公开(公告)号：US20120134460A1
公开(公告)日：2012-05-31
申请号：US13090593
申请日：2011-04-20
申请人： Ying-Chen CHEN , Hao-Chieh Lee , Chun-Huan Chang , Chun-Hsin Liu , Wan-Jung Chen
发明人： Ying-Chen CHEN , Hao-Chieh Lee , Chun-Huan Chang , Chun-Hsin Liu , Wan-Jung Chen
IPC分类号： G11C19/00
CPC分类号： G11C19/28 , G09G3/3674 , G09G2310/0286
摘要： An exemplary layout structure of a shift register circuit includes a first shift register and a second shift register arranged adjacent to the first shift register. The first shift register and the second shift register each receive a first signal and a second signal phase-inverted with respect to the first signal. Moreover, the first shift register and the second shift register share a common signal routing trace for receiving the first signal. The common signal routing trace is arranged extending into between the first shift register and the second shift register.
摘要翻译：移位寄存器电路的示例性布局结构包括与第一移位寄存器相邻布置的第一移位寄存器和第二移位寄存器。第一移位寄存器和第二移位寄存器各自接收相对于第一信号相位反转的第一信号和第二信号。此外，第一移位寄存器和第二移位寄存器共享用于接收第一信号的公共信号路由跟踪。公共信号路由跟踪被布置成延伸到第一移位寄存器和第二移位寄存器之间。

8. 发明授权

US08422620B2 Shift registers 有权
标题翻译：移位寄存器
公开(公告)号：US08422620B2
公开(公告)日：2013-04-16
申请号：US12607156
申请日：2009-10-28
申请人： Kuo-Chang Su , Tsung-Ting Tsai , Yung-Chih Chen , Chun-Hsin Liu
发明人： Kuo-Chang Su , Tsung-Ting Tsai , Yung-Chih Chen , Chun-Hsin Liu
IPC分类号： G11C19/00
CPC分类号： G11C19/28
摘要： A shift register is provided and includes a first shift registering unit and a second shift registering unit. The first shift registering unit generates a first trigger signal at a first output terminal and includes a first pull-down circuit. The second shift registering unit receives the first trigger signal and generates a second trigger signal at a second output terminal. The first trigger signal and the second trigger signal are sequentially asserted. The second shift registering unit includes a second pull-down circuit. The first pull-down circuit and the second pull-down circuit perform pull-down operations at different times. When the first pull-down circuit does not perform the pull-down operation, the second pull-down circuit performs pull-down operations to the first output terminal.
摘要翻译：提供一个移位寄存器，包括一个第一移位寄存单元和一个第二移位寄存单元。第一移位寄存单元在第一输出端产生第一触发信号，并包括第一下拉电路。第二移位寄存单元接收第一触发信号并在第二输出端产生第二触发信号。第一触发信号和第二触发信号被依次断言。第二移位登记单元包括第二下拉电路。第一下拉电路和第二下拉电路在不同时间执行下拉操作。当第一下拉电路不执行下拉操作时，第二下拉电路对第一输出端子执行下拉操作。

9. 发明授权

US08055005B2 Bluetooth earphone and lanyard structure thereof 失效
标题翻译：蓝牙耳机及其挂绳结构
公开(公告)号：US08055005B2
公开(公告)日：2011-11-08
申请号：US11797308
申请日：2007-05-02
申请人： Chun-Hsin Liu , Chung-Chun Wu , Jui-Chi Liao
发明人： Chun-Hsin Liu , Chung-Chun Wu , Jui-Chi Liao
IPC分类号： H04R25/00 , H04R9/08 , H04R11/04 , H04R17/02 , H04R19/04 , H04R21/02 , H04R1/00 , A45F5/00 , A45F3/14
CPC分类号： A45F5/00 , A45F2005/006 , Y10T24/1374 , Y10T24/1394
摘要： A Bluetooth earphone and a lanyard structure thereof are provided. The Bluetooth earphone includes an earphone body and a lanyard structure. The lanyard structure includes a lanyard and a clip element. The lanyard is disposed on the clip element. The clip element includes two hooks gripping the earphone body for combining the lanyard structure with the earphone body.
摘要翻译：提供蓝牙耳机及其挂绳结构。蓝牙耳机包括耳机主体和挂绳结构。挂绳结构包括挂绳和夹子元件。挂绳安装在夹子上。夹子元件包括抓住耳机主体的两个钩子，用于将挂绳结构与耳机主体组合。

10. 发明申请

US20090243981A1 Driving module of display device and method for extending lifetime of the driving module 审中-公开
标题翻译：显示装置的驱动模块和延长驱动模块寿命的方法
公开(公告)号：US20090243981A1
公开(公告)日：2009-10-01
申请号：US12185821
申请日：2008-08-05
申请人： Yung-Chih Chen , Chun-Hsin Liu , Po-Yuan Liu , Min-Feng Chiang
发明人： Yung-Chih Chen , Chun-Hsin Liu , Po-Yuan Liu , Min-Feng Chiang
IPC分类号： G09G3/36
CPC分类号： G09G3/3677 , G09G3/006 , G09G2330/08
摘要： A driving module drives a display device having a plurality of pixel switches. The driving module includes a gate driving circuit, a plurality of switch components, and a shorting line. The gate driving circuit includes a plurality of output ends correspondingly coupled to the plurality of the pixel switches through a plurality of gate lines for outputting a plurality of gate driving signals and turning on the plurality of the pixel switches. The plurality of the gate lines are coupled to the shorting line through the switch components. Each control end of the switch components is coupled to the gate driving circuit for receiving the gate driving signals in order to refresh the state of the switch components.
摘要翻译：驱动模块驱动具有多个像素开关的显示装置。驱动模块包括栅极驱动电路，多个开关部件和短路线。栅极驱动电路包括通过多条栅极线对应地耦合到多个像素开关的多个输出端，用于输出多个栅极驱动信号并导通多个像素开关。多个栅极线通过开关部件耦合到短路线。开关部件的每个控制端耦合到栅极驱动电路，用于接收栅极驱动信号，以刷新开关部件的状态。

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