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1. 发明申请

US20060105533A1 Method for engineering hybrid orientation/material semiconductor substrate 审中-公开
标题翻译：工程混合取向/材料半导体衬底的方法
公开(公告)号：US20060105533A1
公开(公告)日：2006-05-18
申请号：US10990180
申请日：2004-11-16
申请人： Yung Chong , Liang Hsia , Chew Ang
发明人： Yung Chong , Liang Hsia , Chew Ang
IPC分类号： H01L21/8228
CPC分类号： H01L21/823807
摘要： The embodiments provide a structure and a method of manufacturing a semiconductor structure that has a different material in the area where PMOS devices will be formed than in the area where NMOS devices will be formed which is characterized as follows. An embodiment comprises the following steps. A substrate is provided. The substrate has a NMOS area and a PMOS area. We form a NMOS mask over the NMOS area. We form a first semiconductor layer over the PMOS area. We remove the mask. We form a second semiconductor layer over the NMOS area. Then we form an isolation region in the substrate between at least portions of the NMOS and the PMOS areas. We form PMOS devices in the PMOS area and form NMOS devices in the NMOS area.
摘要翻译：实施例提供一种制造半导体结构的结构和方法，该半导体结构在将要形成PMOS器件的区域中将具有不同于在其上将形成NMOS器件的区域中的材料，其特征如下。实施例包括以下步骤。提供基板。衬底具有NMOS区域和PMOS区域。我们在NMOS区域上形成NMOS掩模。我们在PMOS区域上形成第一半导体层。我们删除面具。我们在NMOS区域上形成第二个半导体层。然后，在NMOS和PMOS区域的至少一部分之间，在衬底中形成隔离区。我们在PMOS区域中形成PMOS器件，并在NMOS区域中形成NMOS器件。

2. 发明申请

US20060160290A1 Method to fabricate variable work function gates for FUSI devices 有权
标题翻译：为FUSI设备制造可变功能门的方法
公开(公告)号：US20060160290A1
公开(公告)日：2006-07-20
申请号：US11039428
申请日：2005-01-20
申请人： Yung Chong , Dong Sohn , Chew-Hue Ang , Purakh Vermo , Liang Hsia
发明人： Yung Chong , Dong Sohn , Chew-Hue Ang , Purakh Vermo , Liang Hsia
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823835 , H01L21/823842
摘要： An embodiment of fabrication of a variable work function gates in a FUSI device is described. The embodiment uses a work function doping implant to dope the polysilicon to achieve a desired work function. Selective epitaxy growth (SEG) is used to form silicon over the source/drain regions. The doped poly-Si gate is fully silicided to form fully silicided gates that have a desired work function. We provide a substrate having a NMOS region and a PMOS region. We form a gate dielectric layer and a gate layer over said substrate. We perform a (gate Vt) gate layer implant process to implant impurities such as P+, As+, B+, BF2+, N+, Sb+, In+, C+, Si+, Ge+ or Ar+ into the gate layer gate in the NMOS gate regions and said PMOS gate regions. We form a cap layer over said gate layer. We pattern said cap layer, said gate layer and said gate dielectric layer to form a NMOS gate and a PMOS gate. Spacers are formed and S/D regions are formed. A metal is deposited over said substrate surface. We anneal said metal layer to form fully silicided NMOS gate and fully silicided PMOS gate.
摘要翻译：描述了在FUSI设备中制造可变功函数门的实施例。该实施例使用功函数掺杂注入来掺杂多晶硅以实现所需的功函数。选择性外延生长（SEG）用于在源极/漏极区域上形成硅。掺杂的多晶硅栅极被完全硅化以形成具有所需功函数的完全硅化栅极。我们提供具有NMOS区和PMOS区的衬底。我们在所述衬底上形成栅极介电层和栅极层。我们进行（栅极Vt）栅极层注入工艺，将诸如P +，As +，B +，BF 2 +，N +，Sb +，In +，C +，Si +，Ge +或Ar +的杂质注入栅极层 NMOS栅极区域和所述PMOS栅极区域中的栅极。我们在所述栅极层上形成覆盖层。我们对所述盖层，所述栅极层和所述栅极电介质层进行图案化以形成NMOS栅极和PMOS栅极。形成间隔物并形成S / D区域。在所述衬底表面上沉积金属。我们退火所述金属层以形成完全硅化的NMOS栅极和完全硅化的PMOS栅极。

3. 发明申请

US20060160343A1 Laser activation of implanted contact plug for memory bitline fabrication 有权
标题翻译：用于存储器位线制造的植入接触插塞的激光激活
公开(公告)号：US20060160343A1
公开(公告)日：2006-07-20
申请号：US11039429
申请日：2005-01-20
申请人： Yung Chong , Dong Sohn , Liang Hsia
发明人： Yung Chong , Dong Sohn , Liang Hsia
IPC分类号： H01L21/3205
CPC分类号： H01L27/105 , H01L21/28512 , H01L21/76897 , H01L27/11568 , H01L27/11573 , H01L29/665 , H01L29/7833
摘要： An example method of forming a bitline contact region and bitline contact plug for a memory device using a laser irradiation activation process. An example embodiment comprises: providing a substrate having a logic region and a SONOS memory region. We form in the memory region, a memory transistor comprised of a memory gate dielectric, a memory gate electrode, memory LDD regions, memory spacers on the sidewalls of the memory gate electrode. We then perform a “memory Cell Source Line” implant to form a memory source line in the memory region adjacent to the memory gate electrode. We form silicide over the memory gate electrode and on the memory source line. We form an ILD dielectric layer over the substrate surface. We form a contact opening in the ILD dielectric layer over the memory Drain in the memory area. We etch an opening in the substrate in the drain region adjacent to the memory gate electrode. The opening exposes the memory cell first well and exposes the memory drain on the sidewall of the opening. We perform a bitline contact plug implant to from a doped contact region under the opening. We activate the doped contact region to form an activated doped contact region using a laser irradiation process. The laser irradiation process improves the electrical activation of the doped contact region without interfering with the silicide and S/D regions of the logic devices.
摘要翻译：使用激光照射激活过程形成用于存储器件的位线接触区域和位线接触插塞的示例性方法。示例实施例包括：提供具有逻辑区域和SONOS存储器区域的衬底。在存储区域中形成存储器晶体管，该存储晶体管由存储栅极电介质，存储栅极电极，存储器LDD区域，存储器栅电极的侧壁上的存储器间隔构成。然后，我们执行“存储单元源线”注入，以在与存储器栅电极相邻的存储器区域中形成存储器源极线。我们在存储器栅电极和存储器源极线上形成硅化物。我们在衬底表面上形成一个ILD电介质层。我们在存储器区域中的存储器漏极上的ILD电介质层中形成接触开口。我们蚀刻在与存储栅电极相邻的漏极区中的衬底中的开口。开口第一次暴露存储单元并暴露开口侧壁上的存储器漏极。我们从开口下方的掺杂接触区域执行位线接触插入注入。我们激活掺杂接触区域，以使用激光照射工艺形成激活的掺杂接触区域。激光照射过程改善了掺杂接触区域的电激活，而不会干扰逻辑器件的硅化物和S / D区域。

4. 发明申请

US20070235802A1 Method to control source/drain stressor profiles for stress engineering 有权
标题翻译：控制应力工程源/排泄应力曲线的方法
公开(公告)号：US20070235802A1
公开(公告)日：2007-10-11
申请号：US11399016
申请日：2006-04-05
申请人： Yung Chong , Zhijiong Luo , Judson Holt
发明人： Yung Chong , Zhijiong Luo , Judson Holt
IPC分类号： H01L21/8234
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： An example embodiment of a strained channel transistor structure comprises the following: a strained channel region comprising a first semiconductor material with a first natural lattice constant; a gate dielectric layer overlying the strained channel region; a gate electrode overlying the gate dielectric layer; and a source region and drain region oppositely adjacent to the strained channel region, one or both of the source region and drain region are comprised of a stressor region comprised of a second semiconductor material with a second natural lattice constant different from the first natural lattice constant; the stressor region has a graded concentration of a dopant impurity and/or of a stress inducing molecule. Another example embodiment is a process to form the graded impurity or stress inducing molecule stressor embedded S/D region, whereby the location/profile of the S/D stressor is not defined by the recess depth/profile.
摘要翻译：应变通道晶体管结构的示例性实施例包括以下：包含具有第一自然晶格常数的第一半导体材料的应变通道区域; 覆盖在应变通道区上的栅介质层; 覆盖所述栅介质层的栅电极; 以及源极区域和漏极区域，其与所述应变通道区域相邻地邻近，所述源极区域和漏极区域中的一个或两个由包含第二半导体材料的应力区域构成，所述第二半导体材料具有不同于所述第一自然晶格常数的第二自然晶格常数 ; 应力区域具有掺杂剂杂质和/或应力诱导分子的分级浓度。另一个示例性实施例是形成渐变杂质或应力诱导分子应力嵌入S / D区域的过程，由此S / D应力器的位置/轮廓不由凹槽深度/轮廓限定。

5. 发明申请

US20070132038A1 Embedded stressor structure and process 有权
标题翻译：嵌入式应力器结构与过程
公开(公告)号：US20070132038A1
公开(公告)日：2007-06-14
申请号：US11297522
申请日：2005-12-08
申请人： Yung Chong , Zhijiong Luo , Joo Kim , Brian Greene , Kern Rim
发明人： Yung Chong , Zhijiong Luo , Joo Kim , Brian Greene , Kern Rim
IPC分类号： H01L29/76
CPC分类号： H01L21/823814 , H01L21/823807 , H01L29/165 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： An example embodiments are structures and methods for forming an FET with embedded stressor S/D regions (e.g., SiGe), a doped layer below the embedded S/D region adjacent to the isolation regions, and a stressor liner over reduced spacers of the FET gate. An example method comprising the following. We provide a gate structure over a first region in a substrate. The gate structure is comprised of gate dielectric, a gate, and sidewall spacers. We provide isolation regions in the first region spaced from the gate structure; and a channel region in the substrate under the gate structure. We form S/D recesses in the first region in the substrate adjacent to the sidewall spacers. We form S/D stressor regions filling the S/D recesses. The S/D stressor regions can be thicker adjacent to the gate structure than adjacent to the isolation regions; We implant dopant ions into the S/D stressor regions and into the substrate below the S/D stressor regions adjacent to the isolation regions to form upper stressor doped regions.
摘要翻译：示例性实施例是用于形成具有嵌入的应力源S / D区域（例如，SiGe）的FET的结构和方法，位于与隔离区域相邻的嵌入式S / D区域下方的掺杂层，以及FET上减少的间隔物上的应力衬垫门。包括以下的示例性方法。我们在衬底的第一区域上提供栅极结构。栅极结构由栅极电介质，栅极和侧壁间隔物组成。我们提供与栅极结构间隔开的第一区域中的隔离区域; 以及栅极结构下的衬底中的沟道区。我们在邻近侧壁间隔物的衬底的第一区域中形成S / D凹槽。形成填充S / D凹槽的S / D应力区域。与隔离区相邻的S / D应力区可以比栅极结构更厚; 我们将掺杂剂离子注入到S / D应力区域中并进入与隔离区域相邻的S / D应力区域下方的衬底中以形成上部应力源掺杂区域。

6. 发明申请

US20070122955A1 METHOD OF MANUFACTURING A SEMICONDUCTOR STRUCTURE 失效
标题翻译：制造半导体结构的方法
公开(公告)号：US20070122955A1
公开(公告)日：2007-05-31
申请号：US11164568
申请日：2005-11-29
申请人： Zhijiong Luo , Yung Chong , Huilong Zhu
发明人： Zhijiong Luo , Yung Chong , Huilong Zhu
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L21/823814 , H01L21/823807 , H01L21/823835 , H01L21/823842 , H01L21/823864 , H01L29/4975 , H01L29/66545 , H01L29/6656 , H01L29/66636 , H01L29/7848
摘要： There is provided a method of manufacturing a field effect transistor (FET) that includes the steps of forming a gate structure on a semiconductor substrate, and forming a recess in the substrate and embedding a second semiconductor material in the recess. The gate structure includes a gate dielectric layer, conductive layers and an insulating layer. Forming said gate structure includes a step of recessing the conductive layer in the gate structure, and the steps of recessing the conductive layer and forming the recess in the substrate are performed in a single step. There is also provided a FET device.
摘要翻译：提供了一种制造场效应晶体管（FET）的方法，该方法包括以下步骤：在半导体衬底上形成栅极结构，并在衬底中形成凹陷并将第二半导体材料嵌入凹槽中。栅极结构包括栅极电介质层，导电层和绝缘层。形成所述栅极结构包括使栅极结构中的导电层凹陷的步骤，并且在单个步骤中执行使导电层凹陷并且在衬底中形成凹部的步骤。还提供了一种FET器件。

7. 发明申请

US20070196996A1 Semiconductor devices and methods of manufacturing thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070196996A1
公开(公告)日：2007-08-23
申请号：US11356666
申请日：2006-02-17
申请人： Jin-Ping Han , Yung Chong
发明人： Jin-Ping Han , Yung Chong
IPC分类号： H01L21/76
CPC分类号： H01L21/823807 , H01L21/76232 , H01L21/823878 , H01L29/7846
摘要： Semiconductor devices and methods of manufacturing thereof are disclosed. Isolation regions are formed that include a stress-altering material at least partially lining a trench formed within a workpiece. The isolation regions include an insulating material disposed over the stress-altering material.
摘要翻译：公开了半导体器件及其制造方法。形成隔离区域，其包括至少部分地衬在工件内形成的沟槽的应力改变材料。隔离区域包括设置在应力变化材料上方的绝缘材料。

8. 发明申请

US20070138570A1 Formation of raised source/drain structures in NFET with embedded SiGe in PFET 有权
标题翻译：在PFET中嵌入SiGe的NFET中形成凸起的源极/漏极结构
公开(公告)号：US20070138570A1
公开(公告)日：2007-06-21
申请号：US11305584
申请日：2005-12-16
申请人： Yung Chong , Zhijiong Luo , Joo Kim , Judson Holt
发明人： Yung Chong , Zhijiong Luo , Joo Kim , Judson Holt
IPC分类号： H01L29/76 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/66636
摘要： A structure and method for forming raised source/drain structures in a NFET device and embedded SiGe source/drains in a PFET device. We provide a NFET gate structure over a NFET region in a substrate and PFET gate structure over a PFET region. We provide NFET SDE regions adjacent to the NFET gate and provide PFET SDE regions adjacent to the PFET gate. We form recesses in the PFET region in the substrate adjacent to the PFET second spacers. We form a PFET embedded source/drain stressor in the recesses. We form a NFET S/D epitaxial Si layer over the NFET SDE regions and a PFET S/D epitaxial Si layer over PFET embedded source/drain stressor. The epitaxial Si layer over PFET embedded source/drain stressor is consumed in a subsequent salicide step to form a stable and low resistivity silicide over the PFET embedded source/drain stressor. We perform a NFET S/D implant by implanting N-type ions into NFET region adjacent to the NFET gate structure and into the NFET S/D stressor Si layer to form the raised NFET source/drains.
摘要翻译：用于在NFET器件中形成凸起的源极/漏极结构并在PFET器件中形成嵌入的SiGe源极/漏极的结构和方法。我们在衬底上的NFET区域和PFET区域上的PFET栅极结构提供NFET栅极结构。我们提供与NFET栅极相邻的NFET SDE区域，并提供与PFET栅极相邻的PFET SDE区域。我们在邻近PFET第二间隔物的衬底中的PFET区域中形成凹陷。我们在凹槽中形成PFET嵌入式源极/漏极应力器。我们在NFET SDE区域上形成NFET S / D外延Si层，并在PFET嵌入式源极/漏极应力器上形成PFET S / D外延Si层。在随后的自对准硅化物步骤中，在PFET嵌入式源极/漏极应力源上的外延Si层被消耗，以在PFET嵌入式源极/漏极应力器上形成稳定和低电阻率的硅化物。我们通过将N型离子注入到与NFET栅极结构相邻的NFET区域中并进入NFET S / D应力Si层来形成NFET S / D注入，以形成升高的NFET源极/漏极。

9. 发明申请

US20070205469A1 Integrated circuit isolation system 有权
标题翻译：集成电路隔离系统
公开(公告)号：US20070205469A1
公开(公告)日：2007-09-06
申请号：US11369239
申请日：2006-03-06
申请人： Yung Chong , Zhijiong Luo
发明人： Yung Chong , Zhijiong Luo
IPC分类号： H01L29/76
CPC分类号： H01L21/76232 , H01L21/823481
摘要： A method of manufacturing a self-aligned inverted T-shaped isolation structure. An integrated circuit isolation system including providing a substrate, forming a base insulator region in the substrate, and depositing an insulator column having a narrower width than the base insulator region on the base insulator region.
摘要翻译：一种制造自对准倒置T形隔离结构的方法。一种集成电路隔离系统，包括提供衬底，在所述衬底中形成基极绝缘体区域，以及沉积具有比所述基极绝缘体区域上的所述基底绝缘体区域窄的宽度的绝缘体柱。

10. 发明申请

US20070020864A1 Method and structure to prevent silicide strapping of source/drain to body in semiconductor devices with source/drain stressor 有权
标题翻译：用于防止源/漏应力源的半导体器件中源极/漏极穿过物体的方法和结构
公开(公告)号：US20070020864A1
公开(公告)日：2007-01-25
申请号：US11182681
申请日：2005-07-16
申请人： Yung Chong , Brian Greene
发明人： Yung Chong , Brian Greene
IPC分类号： H01L21/336
CPC分类号： H01L29/665 , H01L29/165 , H01L29/6653 , H01L29/6656 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： The example embodiments disclose devices and methods to prevent silicide strapping of the Source/Drain to Body in semiconductor devices with S/D stressor. We provide isolation regions in the substrate and a gate structure over the substrate. We form recesses in the substrate adjacent to the gate structure with disposable spacers and adjacent to the isolation regions. We provide stressor regions filling the recesses. The stress region can have a pit adjacent the isolation regions. We form stressor spacers at least partially in the pit on the sidewalls of the stressor regions. We form silicide regions over the stressor regions. The spacer on the stressor regions sidewalls inhibit the formation of silicide at the stressor region edge during the silicide process, thus preventing silicide strapping of the Source/Drain to Body.
摘要翻译：示例性实施例公开了用于在具有S / D应力源的半导体器件中防止源极/漏极到体的硅化物贴带的器件和方法。我们提供衬底中的隔离区域和衬底上的栅极结构。我们在邻近栅极结构的衬底的基板上形成有一次性间隔件并与隔离区相邻的凹槽。我们提供填充凹槽的压力区。应力区域可以具有邻近隔离区域的凹坑。我们在应力区域的侧壁上的凹坑中至少部分地形成应力源间隔物。我们在应力区域形成硅化物区域。应力区域侧壁上的间隔物在硅化物处理期间抑制了应力区域边缘处的硅化物的形成，从而防止了源/漏对体的硅化物带。

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