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1. 发明申请

US20060160343A1 Laser activation of implanted contact plug for memory bitline fabrication 有权
标题翻译：用于存储器位线制造的植入接触插塞的激光激活
公开(公告)号：US20060160343A1
公开(公告)日：2006-07-20
申请号：US11039429
申请日：2005-01-20
申请人： Yung Chong , Dong Sohn , Liang Hsia
发明人： Yung Chong , Dong Sohn , Liang Hsia
IPC分类号： H01L21/3205
CPC分类号： H01L27/105 , H01L21/28512 , H01L21/76897 , H01L27/11568 , H01L27/11573 , H01L29/665 , H01L29/7833
摘要： An example method of forming a bitline contact region and bitline contact plug for a memory device using a laser irradiation activation process. An example embodiment comprises: providing a substrate having a logic region and a SONOS memory region. We form in the memory region, a memory transistor comprised of a memory gate dielectric, a memory gate electrode, memory LDD regions, memory spacers on the sidewalls of the memory gate electrode. We then perform a “memory Cell Source Line” implant to form a memory source line in the memory region adjacent to the memory gate electrode. We form silicide over the memory gate electrode and on the memory source line. We form an ILD dielectric layer over the substrate surface. We form a contact opening in the ILD dielectric layer over the memory Drain in the memory area. We etch an opening in the substrate in the drain region adjacent to the memory gate electrode. The opening exposes the memory cell first well and exposes the memory drain on the sidewall of the opening. We perform a bitline contact plug implant to from a doped contact region under the opening. We activate the doped contact region to form an activated doped contact region using a laser irradiation process. The laser irradiation process improves the electrical activation of the doped contact region without interfering with the silicide and S/D regions of the logic devices.
摘要翻译：使用激光照射激活过程形成用于存储器件的位线接触区域和位线接触插塞的示例性方法。示例实施例包括：提供具有逻辑区域和SONOS存储器区域的衬底。在存储区域中形成存储器晶体管，该存储晶体管由存储栅极电介质，存储栅极电极，存储器LDD区域，存储器栅电极的侧壁上的存储器间隔构成。然后，我们执行“存储单元源线”注入，以在与存储器栅电极相邻的存储器区域中形成存储器源极线。我们在存储器栅电极和存储器源极线上形成硅化物。我们在衬底表面上形成一个ILD电介质层。我们在存储器区域中的存储器漏极上的ILD电介质层中形成接触开口。我们蚀刻在与存储栅电极相邻的漏极区中的衬底中的开口。开口第一次暴露存储单元并暴露开口侧壁上的存储器漏极。我们从开口下方的掺杂接触区域执行位线接触插入注入。我们激活掺杂接触区域，以使用激光照射工艺形成激活的掺杂接触区域。激光照射过程改善了掺杂接触区域的电激活，而不会干扰逻辑器件的硅化物和S / D区域。

2. 发明申请

US20060160290A1 Method to fabricate variable work function gates for FUSI devices 有权
标题翻译：为FUSI设备制造可变功能门的方法
公开(公告)号：US20060160290A1
公开(公告)日：2006-07-20
申请号：US11039428
申请日：2005-01-20
申请人： Yung Chong , Dong Sohn , Chew-Hue Ang , Purakh Vermo , Liang Hsia
发明人： Yung Chong , Dong Sohn , Chew-Hue Ang , Purakh Vermo , Liang Hsia
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823835 , H01L21/823842
摘要： An embodiment of fabrication of a variable work function gates in a FUSI device is described. The embodiment uses a work function doping implant to dope the polysilicon to achieve a desired work function. Selective epitaxy growth (SEG) is used to form silicon over the source/drain regions. The doped poly-Si gate is fully silicided to form fully silicided gates that have a desired work function. We provide a substrate having a NMOS region and a PMOS region. We form a gate dielectric layer and a gate layer over said substrate. We perform a (gate Vt) gate layer implant process to implant impurities such as P+, As+, B+, BF2+, N+, Sb+, In+, C+, Si+, Ge+ or Ar+ into the gate layer gate in the NMOS gate regions and said PMOS gate regions. We form a cap layer over said gate layer. We pattern said cap layer, said gate layer and said gate dielectric layer to form a NMOS gate and a PMOS gate. Spacers are formed and S/D regions are formed. A metal is deposited over said substrate surface. We anneal said metal layer to form fully silicided NMOS gate and fully silicided PMOS gate.
摘要翻译：描述了在FUSI设备中制造可变功函数门的实施例。该实施例使用功函数掺杂注入来掺杂多晶硅以实现所需的功函数。选择性外延生长（SEG）用于在源极/漏极区域上形成硅。掺杂的多晶硅栅极被完全硅化以形成具有所需功函数的完全硅化栅极。我们提供具有NMOS区和PMOS区的衬底。我们在所述衬底上形成栅极介电层和栅极层。我们进行（栅极Vt）栅极层注入工艺，将诸如P +，As +，B +，BF 2 +，N +，Sb +，In +，C +，Si +，Ge +或Ar +的杂质注入栅极层 NMOS栅极区域和所述PMOS栅极区域中的栅极。我们在所述栅极层上形成覆盖层。我们对所述盖层，所述栅极层和所述栅极电介质层进行图案化以形成NMOS栅极和PMOS栅极。形成间隔物并形成S / D区域。在所述衬底表面上沉积金属。我们退火所述金属层以形成完全硅化的NMOS栅极和完全硅化的PMOS栅极。

3. 发明申请

US20050164436A1 Method of forming a relaxed semiconductor buffer layer on a substrate with a large lattice mismatch 有权
标题翻译：在具有大晶格失配的衬底上形成松散半导体缓冲层的方法
公开(公告)号：US20050164436A1
公开(公告)日：2005-07-28
申请号：US10865433
申请日：2004-06-10
申请人： Jin Liu , Dong Sohn , Liang Hsia
发明人： Jin Liu , Dong Sohn , Liang Hsia
IPC分类号： C30B29/52 , H01L21/20 , H01L29/10 , H01L21/338 , C30B1/00 , H01L21/36
CPC分类号： C30B29/52 , H01L21/02381 , H01L21/0245 , H01L21/02463 , H01L21/02502 , H01L21/0251 , H01L21/02532 , H01L21/02543 , H01L21/0262 , H01L29/1054
摘要： A method of forming a relaxed silicon—germanium layer for use as an underlying layer for a subsequent, overlying tensile strain silicon layer, has been developed. The method features initial growth of a underlying first silicon—germanium layer on a semiconductor substrate, compositionally graded to feature the largest germanium content at the interface of the first silicon—germanium layer and the semiconductor substrate, with the level of germanium decreasing as the growth of the graded first silicon—germanium layer progresses. This growth sequence allows the largest lattice mismatch and greatest level of threading dislocations to be present at the bottom of the graded silicon—germanium layer, with the magnitude of lattice mismatch and threading dislocations decreasing as the growth of the graded silicon—germanium layer progresses. In situ growth of an overlying silicon—germanium layer featuring uniform or non—graded germanium content, results in a relaxed silicon—germanium layer with a minimum of dislocations propagating from the underlying graded silicon—germanium layer. In situ growth of a silicon layer results in a tensile strain, low defect density layer to be used for MOSFET device applications.
摘要翻译：已经开发了形成用于随后的上覆拉伸应变硅层的下层的松弛硅锗层的方法。该方法的特征在于半导体衬底上的底层第一硅 - 锗层的初始生长，其组成分级以在第一硅 - 锗层和半导体衬底的界面处具有最大的锗含量，锗的含量随着生长的分级第一硅锗层进行。该生长序列允许最大的晶格失配和最高级别的穿透位错存在于渐变硅 - 锗层的底部，随着梯度硅 - 锗层的生长进行，晶格失配和穿透位错的大小减小。具有均匀或非分级锗含量的上覆硅锗层的原位生长导致松弛的硅 - 锗层，其中最小的位错从下面的梯度硅 - 锗层传播。硅层的原位生长导致用于MOSFET器件应用的拉伸应变，低缺陷密度层。

4. 发明申请

US20060160303A1 Method for forming high-K charge storage device 有权
公开(公告)号：US20060160303A1
公开(公告)日：2006-07-20
申请号：US11039430
申请日：2005-01-20
申请人： Chew-Hoe Ang , Dong Sohn , Liang Hsia
发明人： Chew-Hoe Ang , Dong Sohn , Liang Hsia
IPC分类号： H01L21/336
CPC分类号： H01L29/513 , H01L21/28282 , H01L29/792
摘要： Structures and methods of fabricating of a floating gate non-volatile memory device. In a first example embodiment, We form a bottom tunnel layer comprised of a lower oxide tunnel layer and a upper hafnium oxide tunnel layer; a charge storage layer comprised of a tantalum oxide and a top blocking layer preferably comprised of a lower hafnium oxide storage layer and an upper oxide storage layer. We form a gate electrode over the top blocking layer. We pattern the layers to form a gate structure and form source/drain regions to complete the memory device. In a second example embodiment, we form a floating gate non-volatile memory device comprised of: a bottom tunnel layer comprised essentially of silicon oxide; a charge storage layer comprised of a tantalum oxide; a top blocking layer comprised essentially of silicon oxide; and a gate electrode. The embodiments also comprise anneals and nitridation steps.

5. 发明申请

US20060110865A1 Method of forming ultra thin silicon oxynitride for gate dielectric applications 有权
标题翻译：形成用于栅极电介质应用的超薄氮氧化硅的方法
公开(公告)号：US20060110865A1
公开(公告)日：2006-05-25
申请号：US10992894
申请日：2004-11-19
申请人： Jinping Liu , Hwa Koh , Dong Sohn , Liang Hsia
发明人： Jinping Liu , Hwa Koh , Dong Sohn , Liang Hsia
IPC分类号： H01L21/84 , H01L21/31
CPC分类号： H01L21/0214 , H01L21/02238 , H01L21/02332 , H01L21/265 , H01L21/28185 , H01L21/28202 , H01L21/3144 , H01L29/518
摘要： A method of forming a gate dielectric layer is disclosed. The method comprises the following steps. A substrate is provided having silicon regions containing surfaces upon which gate dielectrics are to be disposed. An oxide is formed over the surfaces. A silicon layer is formed over the oxide layer. A nitridation process is performed. An optional high temperature annealing step may be performed.
摘要翻译：公开了一种形成栅介质层的方法。该方法包括以下步骤。提供了具有硅区域的衬底，所述硅区域包含要在其上设置栅极电介质的表面。在表面上形成氧化物。在氧化物层上形成硅层。进行氮化处理。可以进行可选的高温退火步骤。

6. 发明申请

US20060234479A1 Implantation-less approach to fabricating strained semiconductor on isolation wafers 有权
标题翻译：无离子方法在隔离晶圆上制造应变半导体
公开(公告)号：US20060234479A1
公开(公告)日：2006-10-19
申请号：US11107712
申请日：2005-04-15
申请人： Jinping Liu , Dong Sohn , Liang Hsia
发明人： Jinping Liu , Dong Sohn , Liang Hsia
IPC分类号： H01L21/20 , H01L21/265 , H01L21/36 , H01L31/20
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/02395 , H01L21/02447 , H01L21/0245 , H01L21/02488 , H01L21/02502 , H01L21/0251 , H01L21/02532 , H01L21/02664 , H01L21/76262 , H01L29/78 , Y10S438/933
摘要： A method of fabrication of semiconductor substrate structure comprising the following. A buffer layer is formed on the Si Substrate. We form a SiGe layer on the novel buffer layer. The buffer layer has defects therein so that the buffer layer is oxidized to form a buried isolation layer comprised of silicon oxide and an oxide layer and oxidize the SiGe layer for form a oxide layer. The oxide layer is then removed. An upper semiconductor layer (e.g., Si, SiGe or Ge layer) is epitaxially formed on the SiGe layer. Devices are formed on said an upper semiconductor layer. The buffer layer can be formed by several aspects.
摘要翻译：一种制造半导体衬底结构的方法，包括以下步骤。在Si基板上形成缓冲层。我们在新型缓冲层上形成SiGe层。缓冲层在其中具有缺陷，使得缓冲层被氧化以形成由氧化硅和氧化物层组成的掩埋隔离层，并氧化SiGe层以形成氧化物层。然后除去氧化物层。在SiGe层上外延形成上半导体层（例如Si，SiGe或Ge层）。器件形成在所述上半导体层上。缓冲层可以由几个方面形成。

7. 发明申请

US20050164473A1 Method of forming a relaxed semiconductor buffer layer on a substrate with a large lattice mismatch 有权
标题翻译：在具有大晶格失配的衬底上形成松散半导体缓冲层的方法
公开(公告)号：US20050164473A1
公开(公告)日：2005-07-28
申请号：US10763305
申请日：2004-01-23
申请人： Jin Liu , Dong Sohn , Liang Hsia
发明人： Jin Liu , Dong Sohn , Liang Hsia
IPC分类号： C30B29/52 , H01L21/20 , H01L29/10 , C30B1/00
CPC分类号： C30B29/52 , H01L21/02381 , H01L21/0245 , H01L21/02463 , H01L21/02502 , H01L21/0251 , H01L21/02532 , H01L21/02543 , H01L21/0262 , H01L29/1054 , Y10S438/933
摘要： A method of forming a relaxed silicon-germanium layer for use as an underlying layer for a subsequent overlying tensile strain silicon layer, has been developed. The method features initial growth of a underlying first silicon-germanium layer on a semiconductor substrate, compositionally graded to feature the largest germanium content at the interface of the first silicon-germanium layer and the semiconductor substrate, with the level of germanium decreasing as the growth of the graded first silicon-germanium layer progresses. This growth sequence allows the largest lattice mismatch and greatest level of threading dislocations to be present at the bottom of the graded silicon-germanium layer, with the magnitude of lattice mismatch and threading dislocations decreasing as the growth of the graded silicon-germanium layer progresses. In situ growth of an overlying silicon-germanium layer featuring uniform or non-graded germanium content, results in a relaxed silicon-germanium layer with a minimum of dislocations propagating from the underlying graded silicon-germanium layer. In situ growth of a silicon layer results in a tensile strain, low defect density layer to be used for MOSFET device applications.
摘要翻译：已经开发了形成用于随后的上覆拉伸应变硅层的下层的松弛硅 - 锗层的方法。该方法的特征在于半导体衬底上的底层第一硅 - 锗层的初始生长，其组成分级以在第一硅 - 锗层和半导体衬底的界面处具有最大的锗含量，锗的含量随着生长的分级第一硅锗层进行。该生长序列允许最大的晶格失配和最高级别的穿透位错存在于渐变硅 - 锗层的底部，随着梯度硅 - 锗层的生长进行，晶格失配和穿透位错的大小减小。具有均匀或非分级锗含量的上覆硅锗层的原位生长导致松弛的硅 - 锗层，其中最小的位错从下面的梯度硅 - 锗层传播。硅层的原位生长导致用于MOSFET器件应用的拉伸应变，低缺陷密度层。

8. 发明申请

US20070132032A1 Selective stress relaxation of contact etch stop layer through layout design 有权
标题翻译：通过布局设计，接触蚀刻停止层的选择性应力松弛
公开(公告)号：US20070132032A1
公开(公告)日：2007-06-14
申请号：US11302035
申请日：2005-12-13
申请人： Lee Teo , Elgin Quek , Dong Sohn
发明人： Lee Teo , Elgin Quek , Dong Sohn
IPC分类号： H01L29/78 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/76816 , H01L21/76829 , H01L21/823814 , H01L21/823871 , H01L27/0207 , H01L29/665 , H01L29/6659 , H01L29/7843
摘要： A structure and method of fabrication of a semiconductor device, where a stress layer is formed over a MOS transistor to put either tensile stress or compressive stress on the channel region. The parameters such as the location and area of the contact hole thru the stress layer are chosen to produce a desired amount of stress to improve device performance. In an example embodiment for a tensile stress layer, the PMOS S/D contact area is larger than the NMOS S/D contact area so the tensile stress on the PMOS channel is less than the tensile stress on the NMOS channel. In an example embodiment for a compressive stress layer, the NMOS contact area is larger than the PMOS contact area so that the compressive stress on the NMOS channel is less than the compressive stress on the PMOS channel.
摘要翻译：一种制造半导体器件的结构和方法，其中在MOS晶体管上形成应力层以在沟道区域上施加拉伸应力或压应力。选择诸如通过应力层的接触孔的位置和面积的参数以产生期望量的应力以改善器件性能。在拉伸应力层的示例实施例中，PMOS S / D接触面积大于NMOS S / D接触面积，因此PMOS沟道上的拉伸应力小于NMOS沟道上的拉伸应力。在压应力层的示例实施例中，NMOS接触面积大于PMOS接触面积，使得NMOS沟道上的压应力小于PMOS沟道上的压应力。

9. 发明申请

US20060166435A1 Synthesis of GE nanocrystal memory cell and using a block layer to control oxidation kinetics 审中-公开
标题翻译： GE纳米晶体记忆体的合成和阻挡层控制氧化动力学
公开(公告)号：US20060166435A1
公开(公告)日：2006-07-27
申请号：US11040620
申请日：2005-01-21
申请人： Lee Teo , Sripao Nagarao , Elgin Kiok Quek , Dong Sohn
发明人： Lee Teo , Sripao Nagarao , Elgin Kiok Quek , Dong Sohn
IPC分类号： H01L21/336
CPC分类号： B82Y10/00 , H01L29/40114
摘要： A structure and a method of manufacturing a memory devices using nanoncrystals. A first embodiment is characterized as follows. We form a first gate insulator over the substrate. The first gate insulator is comprised of an oxide layer and blocking layer. We form a SiGe layer over the first gate insulator layer. Then we perform an oxidation/anneal process consume the SiGe layer to form Ge nanocrystals7 on the first gate insulator layer and a silicon oxide layer over the first gate insulator layer. We form a gate electrode over the a silicon oxide layer. In a second embodiment, the first gate insulator is comprised of one layer of oxidation blocking material. The blocking layer prevents the oxidation of the substrate during process steps used to form the nanocrystals.
摘要翻译：使用纳米晶体制造存储器件的结构和方法。第一实施例的特征如下。我们在衬底上形成第一个栅极绝缘体。第一栅极绝缘体由氧化物层和阻挡层构成。我们在第一栅极绝缘体层上形成SiGe层。然后，我们进行氧化/退火工艺消耗SiGe层，以在第一栅极绝缘体层上形成Ge纳米晶体7，在第一栅极绝缘体层上形成氧化硅层。我们在氧化硅层上形成栅电极。在第二实施例中，第一栅极绝缘体由一层氧化阻挡材料构成。阻挡层防止在用于形成纳米晶体的工艺步骤期间底物的氧化。

10. 发明申请

US20070265393A1 Composition for low-odor thermoplastic resin 审中-公开
标题翻译：低气味热塑性树脂组合物
公开(公告)号：US20070265393A1
公开(公告)日：2007-11-15
申请号：US11648862
申请日：2006-12-29
申请人： Dong Sohn , Je Lee , Bong Park , Jae Kim , Soon Jung , Yong Lee
发明人： Dong Sohn , Je Lee , Bong Park , Jae Kim , Soon Jung , Yong Lee
IPC分类号： C08G63/48
CPC分类号： C08L25/12 , C08L25/16 , C08L25/18 , C08L55/02 , C08L2205/035 , C08L2666/02 , C08L2666/24 , C08L2666/04
摘要： The present invention relates to a low-odor thermoplastic resin composition. In particular the resin of the resin composition is prepared by a new bulk polymerization process that is used to reduce the characteristic chemical odor in new cars. The resin minimizes the use of the resin prepared by the conventional emulsion polymerization process, N-substituted maleimide and α-alkylstyrene-based heat-resistant materials which are used to improve heat resistance and the molecular weight of the matrix of the thermoplastic composition. The resin is also improves impact strength, thereby having reduced characteristic chemical odor, while having superior impact strength and heat resistance.
摘要翻译：本发明涉及一种低气味的热塑性树脂组合物。特别地，树脂组合物的树脂通过新的本体聚合方法制备，该方法用于降低新车中的特征化学气味。该树脂使通过常规乳液聚合方法制备的树脂，N-取代马来酰亚胺和α-烷基苯乙烯类耐热材料的用途最小化，这些材料用于改善热塑性组合物的耐热性和基质的分子量。树脂也提高冲击强度，从而具有降低的特征化学气味，同时具有优异的冲击强度和耐热性。

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