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1. 发明申请

US20070138570A1 Formation of raised source/drain structures in NFET with embedded SiGe in PFET 有权
标题翻译：在PFET中嵌入SiGe的NFET中形成凸起的源极/漏极结构
公开(公告)号：US20070138570A1
公开(公告)日：2007-06-21
申请号：US11305584
申请日：2005-12-16
申请人： Yung Chong , Zhijiong Luo , Joo Kim , Judson Holt
发明人： Yung Chong , Zhijiong Luo , Joo Kim , Judson Holt
IPC分类号： H01L29/76 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/66636
摘要： A structure and method for forming raised source/drain structures in a NFET device and embedded SiGe source/drains in a PFET device. We provide a NFET gate structure over a NFET region in a substrate and PFET gate structure over a PFET region. We provide NFET SDE regions adjacent to the NFET gate and provide PFET SDE regions adjacent to the PFET gate. We form recesses in the PFET region in the substrate adjacent to the PFET second spacers. We form a PFET embedded source/drain stressor in the recesses. We form a NFET S/D epitaxial Si layer over the NFET SDE regions and a PFET S/D epitaxial Si layer over PFET embedded source/drain stressor. The epitaxial Si layer over PFET embedded source/drain stressor is consumed in a subsequent salicide step to form a stable and low resistivity silicide over the PFET embedded source/drain stressor. We perform a NFET S/D implant by implanting N-type ions into NFET region adjacent to the NFET gate structure and into the NFET S/D stressor Si layer to form the raised NFET source/drains.
摘要翻译：用于在NFET器件中形成凸起的源极/漏极结构并在PFET器件中形成嵌入的SiGe源极/漏极的结构和方法。我们在衬底上的NFET区域和PFET区域上的PFET栅极结构提供NFET栅极结构。我们提供与NFET栅极相邻的NFET SDE区域，并提供与PFET栅极相邻的PFET SDE区域。我们在邻近PFET第二间隔物的衬底中的PFET区域中形成凹陷。我们在凹槽中形成PFET嵌入式源极/漏极应力器。我们在NFET SDE区域上形成NFET S / D外延Si层，并在PFET嵌入式源极/漏极应力器上形成PFET S / D外延Si层。在随后的自对准硅化物步骤中，在PFET嵌入式源极/漏极应力源上的外延Si层被消耗，以在PFET嵌入式源极/漏极应力器上形成稳定和低电阻率的硅化物。我们通过将N型离子注入到与NFET栅极结构相邻的NFET区域中并进入NFET S / D应力Si层来形成NFET S / D注入，以形成升高的NFET源极/漏极。

2. 发明申请

US20070235802A1 Method to control source/drain stressor profiles for stress engineering 有权
标题翻译：控制应力工程源/排泄应力曲线的方法
公开(公告)号：US20070235802A1
公开(公告)日：2007-10-11
申请号：US11399016
申请日：2006-04-05
申请人： Yung Chong , Zhijiong Luo , Judson Holt
发明人： Yung Chong , Zhijiong Luo , Judson Holt
IPC分类号： H01L21/8234
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： An example embodiment of a strained channel transistor structure comprises the following: a strained channel region comprising a first semiconductor material with a first natural lattice constant; a gate dielectric layer overlying the strained channel region; a gate electrode overlying the gate dielectric layer; and a source region and drain region oppositely adjacent to the strained channel region, one or both of the source region and drain region are comprised of a stressor region comprised of a second semiconductor material with a second natural lattice constant different from the first natural lattice constant; the stressor region has a graded concentration of a dopant impurity and/or of a stress inducing molecule. Another example embodiment is a process to form the graded impurity or stress inducing molecule stressor embedded S/D region, whereby the location/profile of the S/D stressor is not defined by the recess depth/profile.
摘要翻译：应变通道晶体管结构的示例性实施例包括以下：包含具有第一自然晶格常数的第一半导体材料的应变通道区域; 覆盖在应变通道区上的栅介质层; 覆盖所述栅介质层的栅电极; 以及源极区域和漏极区域，其与所述应变通道区域相邻地邻近，所述源极区域和漏极区域中的一个或两个由包含第二半导体材料的应力区域构成，所述第二半导体材料具有不同于所述第一自然晶格常数的第二自然晶格常数 ; 应力区域具有掺杂剂杂质和/或应力诱导分子的分级浓度。另一个示例性实施例是形成渐变杂质或应力诱导分子应力嵌入S / D区域的过程，由此S / D应力器的位置/轮廓不由凹槽深度/轮廓限定。

3. 发明申请

US20070278591A1 METHOD AND STRUCTURE TO FORM SELF-ALIGNED SELECTIVE-SOI 失效
标题翻译：形成自对准选择性SOI的方法和结构
公开(公告)号：US20070278591A1
公开(公告)日：2007-12-06
申请号：US11421594
申请日：2006-06-01
申请人： Zhijiong Luo , Yung Chong , Kevin Dezfulian , Huilong Zhu , Judson Holt
发明人： Zhijiong Luo , Yung Chong , Kevin Dezfulian , Huilong Zhu , Judson Holt
IPC分类号： H01L29/76 , H01L21/8238
CPC分类号： H01L29/66628 , H01L29/0653 , H01L29/665 , H01L29/6656 , H01L29/66636
摘要： Methods of forming a self-aligned, selective semiconductor on insulator (SOI) structure and a related structure are disclosed. In one embodiment, a method includes providing a substrate; forming a gate structure over a channel within the substrate; recessing a portion of the substrate adjacent the channel; forming an insulating layer on a bottom of the recessed portion; and forming a semiconductor material above the insulating layer. An upper surface of the semiconductor material may be sloped. A MOSFET structure may include a substrate; a channel; a source region and a drain region adjacent the channel; a gate structure above the channel and the substrate; a shallow trench isolation (STI) distal from the gate structure; a selectively laid insulating layer in at least one of the source region and the drain region; and an epitaxially grown semiconductor material above the selectively laid insulating layer.
摘要翻译：公开了形成自对准选择性半导体绝缘体（SOI）结构和相关结构的方法。在一个实施例中，一种方法包括提供基底; 在所述衬底内的沟道上形成栅极结构; 使靠近通道的衬底的一部分凹陷; 在所述凹部的底部形成绝缘层; 以及在绝缘层上方形成半导体材料。半导体材料的上表面可以是倾斜的。 MOSFET结构可以包括衬底; 一个渠道与沟道相邻的源极区域和漏极区域; 在通道和衬底上方的栅极结构; 远离栅极结构的浅沟槽隔离（STI）; 在源极区域和漏极区域中的至少一个中选择性地铺设绝缘层; 以及在选择性铺设的绝缘层上方的外延生长的半导体材料。

4. 发明申请

US20070132038A1 Embedded stressor structure and process 有权
标题翻译：嵌入式应力器结构与过程
公开(公告)号：US20070132038A1
公开(公告)日：2007-06-14
申请号：US11297522
申请日：2005-12-08
申请人： Yung Chong , Zhijiong Luo , Joo Kim , Brian Greene , Kern Rim
发明人： Yung Chong , Zhijiong Luo , Joo Kim , Brian Greene , Kern Rim
IPC分类号： H01L29/76
CPC分类号： H01L21/823814 , H01L21/823807 , H01L29/165 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： An example embodiments are structures and methods for forming an FET with embedded stressor S/D regions (e.g., SiGe), a doped layer below the embedded S/D region adjacent to the isolation regions, and a stressor liner over reduced spacers of the FET gate. An example method comprising the following. We provide a gate structure over a first region in a substrate. The gate structure is comprised of gate dielectric, a gate, and sidewall spacers. We provide isolation regions in the first region spaced from the gate structure; and a channel region in the substrate under the gate structure. We form S/D recesses in the first region in the substrate adjacent to the sidewall spacers. We form S/D stressor regions filling the S/D recesses. The S/D stressor regions can be thicker adjacent to the gate structure than adjacent to the isolation regions; We implant dopant ions into the S/D stressor regions and into the substrate below the S/D stressor regions adjacent to the isolation regions to form upper stressor doped regions.
摘要翻译：示例性实施例是用于形成具有嵌入的应力源S / D区域（例如，SiGe）的FET的结构和方法，位于与隔离区域相邻的嵌入式S / D区域下方的掺杂层，以及FET上减少的间隔物上的应力衬垫门。包括以下的示例性方法。我们在衬底的第一区域上提供栅极结构。栅极结构由栅极电介质，栅极和侧壁间隔物组成。我们提供与栅极结构间隔开的第一区域中的隔离区域; 以及栅极结构下的衬底中的沟道区。我们在邻近侧壁间隔物的衬底的第一区域中形成S / D凹槽。形成填充S / D凹槽的S / D应力区域。与隔离区相邻的S / D应力区可以比栅极结构更厚; 我们将掺杂剂离子注入到S / D应力区域中并进入与隔离区域相邻的S / D应力区域下方的衬底中以形成上部应力源掺杂区域。

5. 发明申请

US20100320503A1 STRAINED CHANNEL TRANSISTOR AND METHOD OF FABRICATION THEREOF 有权
标题翻译：应变通道晶体管及其制造方法
公开(公告)号：US20100320503A1
公开(公告)日：2010-12-23
申请号：US12852995
申请日：2010-08-09
申请人： Yung Fu Chong , Zhijiong Luo , Judson Holt
发明人： Yung Fu Chong , Zhijiong Luo , Judson Holt
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66628 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66636
摘要： The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. A strained channel CMOS transistor structure comprises a source stressor region comprising a source extension stressor region; and a drain stressor region comprising a drain extension stressor region; wherein a strained channel region is formed between the source extension stressor region and the drain extension stressor region, a width of said channel region being defined by adjacent ends of said extension stressor regions.
摘要翻译：本发明涉及半导体集成电路。更具体地但非唯一地，本发明涉及应变通道互补金属氧化物半导体（CMOS）晶体管结构及其制造方法。应变通道CMOS晶体管结构包括源应力源区域，其包括源延伸应力区域; 和漏极应力区域，包括漏极延伸应力区域; 其中在所述源延伸应力区域和所述漏极延伸应力区域之间形成应变通道区域，所述沟道区域的宽度由所述延伸应力区域的相邻端限定。

6. 发明授权

US07772071B2 Strained channel transistor and method of fabrication thereof 有权
标题翻译：应变通道晶体管及其制造方法
公开(公告)号：US07772071B2
公开(公告)日：2010-08-10
申请号：US11383951
申请日：2006-05-17
申请人： Yung Fu Chong , Zhijiong Luo , Judson Holt
发明人： Yung Fu Chong , Zhijiong Luo , Judson Holt
IPC分类号： H01L21/336
CPC分类号： H01L29/66628 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66636
摘要： The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. A strained channel CMOS transistor structure comprises a source stressor region comprising a source extension stressor region; and a drain stressor region comprising a drain extension stressor region; wherein a strained channel region is formed between the source extension stressor region and the drain extension stressor region, a width of said channel region being defined by adjacent ends of said extension stressor regions.
摘要翻译：本发明涉及半导体集成电路。更具体地但非唯一地，本发明涉及应变通道互补金属氧化物半导体（CMOS）晶体管结构及其制造方法。应变通道CMOS晶体管结构包括源应力源区域，其包括源延伸应力区域; 和漏极应力区域，包括漏极延伸应力区域; 其中在所述源延伸应力区域和所述漏极延伸应力区域之间形成应变通道区域，所述沟道区域的宽度由所述延伸应力区域的相邻端限定。

7. 发明授权

US08912567B2 Strained channel transistor and method of fabrication thereof 有权
标题翻译：应变通道晶体管及其制造方法
公开(公告)号：US08912567B2
公开(公告)日：2014-12-16
申请号：US12852995
申请日：2010-08-09
申请人： Yung Fu Chong , Zhijiong Luo , Judson Holt
发明人： Yung Fu Chong , Zhijiong Luo , Judson Holt
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/66628 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66636
摘要： The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. A strained channel CMOS transistor structure comprises a source stressor region comprising a source extension stressor region; and a drain stressor region comprising a drain extension stressor region; wherein a strained channel region is formed between the source extension stressor region and the drain extension stressor region, a width of said channel region being defined by adjacent ends of said extension stressor regions.
摘要翻译：本发明涉及半导体集成电路。更具体地但非唯一地，本发明涉及应变通道互补金属氧化物半导体（CMOS）晶体管结构及其制造方法。应变通道CMOS晶体管结构包括源应力源区域，其包括源延伸应力区域; 和漏极应力区域，包括漏极延伸应力区域; 其中在所述源延伸应力区域和所述漏极延伸应力区域之间形成应变通道区域，所述沟道区域的宽度由所述延伸应力区域的相邻端限定。

8. 发明申请

US20070267703A1 STRAINED CHANNEL TRANSISTOR AND METHOD OF FABRICATION THEREOF 有权
标题翻译：应变通道晶体管及其制造方法
公开(公告)号：US20070267703A1
公开(公告)日：2007-11-22
申请号：US11383951
申请日：2006-05-17
申请人： Yung Fu Chong , Zhijiong Luo , Judson Holt
发明人： Yung Fu Chong , Zhijiong Luo , Judson Holt
IPC分类号： H01L29/94
CPC分类号： H01L29/66628 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66636
摘要： The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. A strained channel CMOS transistor structure comprises a source stressor region comprising a source extension stressor region; and a drain stressor region comprising a drain extension stressor region; wherein a strained channel region is formed between the source extension stressor region and the drain extension stressor region, a width of said channel region being defined by adjacent ends of said extension stressor regions.
摘要翻译：本发明涉及半导体集成电路。更具体地但非唯一地，本发明涉及应变通道互补金属氧化物半导体（CMOS）晶体管结构及其制造方法。应变通道CMOS晶体管结构包括源应力源区域，其包括源延伸应力区域; 和漏极应力区域，包括漏极延伸应力区域; 其中在所述源延伸应力区域和所述漏极延伸应力区域之间形成应变通道区域，所述沟道区域的宽度由所述延伸应力区域的相邻端限定。

9. 发明申请

US20070205469A1 Integrated circuit isolation system 有权
标题翻译：集成电路隔离系统
公开(公告)号：US20070205469A1
公开(公告)日：2007-09-06
申请号：US11369239
申请日：2006-03-06
申请人： Yung Chong , Zhijiong Luo
发明人： Yung Chong , Zhijiong Luo
IPC分类号： H01L29/76
CPC分类号： H01L21/76232 , H01L21/823481
摘要： A method of manufacturing a self-aligned inverted T-shaped isolation structure. An integrated circuit isolation system including providing a substrate, forming a base insulator region in the substrate, and depositing an insulator column having a narrower width than the base insulator region on the base insulator region.
摘要翻译：一种制造自对准倒置T形隔离结构的方法。一种集成电路隔离系统，包括提供衬底，在所述衬底中形成基极绝缘体区域，以及沉积具有比所述基极绝缘体区域上的所述基底绝缘体区域窄的宽度的绝缘体柱。

10. 发明申请

US20070122955A1 METHOD OF MANUFACTURING A SEMICONDUCTOR STRUCTURE 失效
标题翻译：制造半导体结构的方法
公开(公告)号：US20070122955A1
公开(公告)日：2007-05-31
申请号：US11164568
申请日：2005-11-29
申请人： Zhijiong Luo , Yung Chong , Huilong Zhu
发明人： Zhijiong Luo , Yung Chong , Huilong Zhu
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L21/823814 , H01L21/823807 , H01L21/823835 , H01L21/823842 , H01L21/823864 , H01L29/4975 , H01L29/66545 , H01L29/6656 , H01L29/66636 , H01L29/7848
摘要： There is provided a method of manufacturing a field effect transistor (FET) that includes the steps of forming a gate structure on a semiconductor substrate, and forming a recess in the substrate and embedding a second semiconductor material in the recess. The gate structure includes a gate dielectric layer, conductive layers and an insulating layer. Forming said gate structure includes a step of recessing the conductive layer in the gate structure, and the steps of recessing the conductive layer and forming the recess in the substrate are performed in a single step. There is also provided a FET device.
摘要翻译：提供了一种制造场效应晶体管（FET）的方法，该方法包括以下步骤：在半导体衬底上形成栅极结构，并在衬底中形成凹陷并将第二半导体材料嵌入凹槽中。栅极结构包括栅极电介质层，导电层和绝缘层。形成所述栅极结构包括使栅极结构中的导电层凹陷的步骤，并且在单个步骤中执行使导电层凹陷并且在衬底中形成凹部的步骤。还提供了一种FET器件。

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