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1. 发明授权

US08675949B2 Reviewed defect selection processing method, defect review method, reviewed defect selection processing tool, and defect review tool 有权
标题翻译：审查缺陷选择处理方法，缺陷审查方法，审查缺陷选择处理工具和缺陷审查工具
公开(公告)号：US08675949B2
公开(公告)日：2014-03-18
申请号：US13266800
申请日：2010-03-25
申请人： Yuji Takagi , Minoru Harada , Yuichi Hamamura
发明人： Yuji Takagi , Minoru Harada , Yuichi Hamamura
IPC分类号： G06K9/00
CPC分类号： G01N21/9501 , G01N21/956 , G01N2021/8867 , H01L22/12 , H01L22/20
摘要： The present invention relates to semiconductor inspection and provides a technology capable of efficiently detecting a systematic defect. In the present system, with regard to the process (S7, S8) of matching hot spot (HS) points that can be simulated in advance and defect points obtained as a result of a visual inspection each other and the unmatched defect points, a process (S6, S9) of classifying the defect points into groups based on similarity of pattern layout at the defect points to determine the defects belonging to a pattern layout where defects frequently occur, thereby reliably detecting the systematic defect. Also, with a process (S11) of acquiring an uneven distribution in a defect occurrence distribution on a wafer, the systematic defect occurring due to topography of the wafer can also be detected.
摘要翻译：本发明涉及半导体检查，并且提供能够有效地检测系统缺陷的技术。在本系统中，关于可以预先模拟的热点（HS）点和作为目视检查的结果获得的缺陷点与不匹配的缺陷点的处理（S7，S8），处理（S6，S9），根据缺陷点的图案布局的相似度将缺陷点分类成组，以确定属于频繁发生缺陷的图案布局的缺陷，从而可靠地检测系统缺陷。此外，通过获取晶片上的缺陷发生分布中的不均匀分布的处理（S11），也可以检测由于晶片的形貌而发生的系统缺陷。

2. 发明授权

US07062081B2 Method and system for analyzing circuit pattern defects 失效
标题翻译：分析电路图形缺陷的方法和系统
公开(公告)号：US07062081B2
公开(公告)日：2006-06-13
申请号：US09783604
申请日：2001-02-15
申请人： Atsushi Shimoda , Ichirou Ishimaru , Yuji Takagi , Takuo Tamura , Yuichi Hamamura , Kenji Watanabe , Yasuhiko Ozawa , Seiji Isogai
发明人： Atsushi Shimoda , Ichirou Ishimaru , Yuji Takagi , Takuo Tamura , Yuichi Hamamura , Kenji Watanabe , Yasuhiko Ozawa , Seiji Isogai
IPC分类号： G06K9/00
CPC分类号： G06T7/0004 , G06T2207/30148 , H01L22/20
摘要： In order to allow critical flaws in an inspected item to be determined early during a production process, the present invention includes the following steps: a step of detecting defects in a production process for the inspected item and storing defect positions; a step of collecting detailed defect information and storing the detailed information in association with defect positions; a step of storing positions at which flaws were generated based on a final inspection of the inspected item; a step of comparing defect positions with positions at which flaws were generated; and a step of classifying and displaying detailed information based on the comparison results.
摘要翻译：为了在生产过程中早期确定检查项目中的关键缺陷，本发明包括以下步骤：检测检查项目的生产过程中的缺陷并存储缺陷位置的步骤; 收集详细缺陷信息并存储与缺陷位置相关联的详细信息的步骤; 基于检查项目的最终检查来存储产生缺陷的位置的步骤; 将缺陷位置与产生缺陷的位置进行比较的步骤; 并根据比较结果对详细信息进行分类和显示。

3. 发明授权

US08621400B2 Method of evaluating systematic defect, and apparatus therefor 有权
标题翻译：评价系统缺陷的方法及其设备
公开(公告)号：US08621400B2
公开(公告)日：2013-12-31
申请号：US13877922
申请日：2011-09-30
申请人： Yuji Takagi , Yuichi Hamamura
发明人： Yuji Takagi , Yuichi Hamamura
IPC分类号： G06F17/50 , G06F11/22
CPC分类号： G06F17/5081 , H01L22/12 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： In order to enable an evaluation of systematic defects, a method of evaluating systematic defects was configured so as to sample a circuit pattern of a specific layer of a semiconductor device, evaluate the state of superimposition between the sampled circuit pattern and circuit patterns of layers other than the specific layer, using design data, classify the state of superimposition, calculate the ratio thereof as a reference ratio, evaluate the state of superimposition between a pattern in design data corresponding to a defect of the specific layer detected by another inspection apparatus and patterns at positions corresponding to the defects in layers other than the specific layer, classify the evaluated state of superimposition, calculate the ratio of the classification as inspection-result ratio, compare the calculated reference ratio and the calculated inspection-result ratio, and evaluate systematic defects by the comparison between the calculated reference ratio and the calculated inspection-result ratio.
摘要翻译：为了能够对系统缺陷进行评估，构造了评价系统缺陷的方法，以对半导体器件的特定层的电路图案进行采样，评估采样电路图案和其他层的电路图案之间的叠加状态比特定层使用设计数据，将叠加状态进行分类，将其比例作为参考比计算，评价与由另一检查装置检测到的特定层的缺陷相对应的设计数据中的图案之间的叠加状态在与特定层以外的层的缺陷相对应的位置，对评价的叠加状态进行分类，计算分类比作为检查结果比，比较计算出的参考比和计算出的检查结果比，并评价系统缺陷通过比较计算的参考比和计算检验结果比例。

4. 发明授权

US07352890B2 Method for analyzing circuit pattern defects and a system thereof 失效
标题翻译：电路图形缺陷分析方法及其系统
公开(公告)号：US07352890B2
公开(公告)日：2008-04-01
申请号：US11356210
申请日：2006-02-17
申请人： Atsushi Shimoda , Ichirou Ishimaru , Yuji Takagi , Takuo Tamura , Yuichi Hamamura , Kenji Watanabe , Yasuhiko Ozawa , Seiji Isogai
发明人： Atsushi Shimoda , Ichirou Ishimaru , Yuji Takagi , Takuo Tamura , Yuichi Hamamura , Kenji Watanabe , Yasuhiko Ozawa , Seiji Isogai
IPC分类号： G06K9/00
CPC分类号： G06T7/0004 , G06T2207/30148 , H01L22/20
摘要： A system for analyzing defects in electronic circuit patterns, including: comparing position information of structural defects with position information of electrical faults and extracting corroborated defects having common position information between the structural defects and electrical faults; classifying images of extracted corroborated defects into critical defect images and non-critical defect images based on a pre-stored classification rule which defines critical and non-critical defects by referring to images of defects, position information of defects, and results of performing an electronic test; modifying the pre-stored classification rule by correcting classification of classified defect images displayed on the screen; and repeating the operations for each subsequent object, wherein for each present object under inspection, using a modified pre-stored classification rule with respect to a previous object, as the pre-stored classification rule for the operations with respect to the present object.
摘要翻译：一种用于分析电子电路图案缺陷的系统，包括：将结构缺陷的位置信息与电气故障的位置信息进行比较，并提取在结构缺陷和电气故障之间具有共同位置信息的证实缺陷; 基于预先存储的分类规则将提取的确证缺陷的图像分类为关键缺陷图像和非关键缺陷图像，该分类规则通过参考缺陷图像，缺陷位置信息和执行电子化的结果来定义关键和非关键缺陷测试; 通过校正显示在屏幕上的分类缺陷图像的分类来修改预先存储的分类规则; 并对每个后续对象重复操作，其中对于被检查的每个当前对象，使用关于先前对象的经修改的预先存储的分类规则作为关于本对象的操作的预先存储的分类规则。

5. 发明申请

US20060140472A1 Method for analyzing circuit pattern defects and a system thereof 失效
标题翻译：电路图形缺陷分析方法及其系统
公开(公告)号：US20060140472A1
公开(公告)日：2006-06-29
申请号：US11356210
申请日：2006-02-17
申请人： Atsushi Shimoda , Ichirou Ishimaru , Yuji Takagi , Takuo Tamura , Yuichi Hamamura , Kenji Watanabe , Yasuhiko Ozawa , Seiji Isogai
发明人： Atsushi Shimoda , Ichirou Ishimaru , Yuji Takagi , Takuo Tamura , Yuichi Hamamura , Kenji Watanabe , Yasuhiko Ozawa , Seiji Isogai
IPC分类号： G06K9/00
CPC分类号： G06T7/0004 , G06T2207/30148 , H01L22/20
摘要： A system for analyzing defects in electronic circuit patterns, including: comparing position information of structural defects with position information of electrical faults and extracting corroborated defects having common position information between the structural defects and electrical faults; classifying images of extracted corroborated defects into critical defect images and non-critical defect images based on a pre-stored classification rule which defines critical and non-critical defects by referring to images of defects, position information of defects, and results of performing an electronic test; modifying the pre-stored classification rule by correcting classification of classified defect images displayed on the screen; and repeating the operations for each subsequent object, wherein for each present object under inspection, using a modified pre-stored classification rule with respect to a previous object, as the pre-stored classification rule for the operations with respect to the present object.
摘要翻译：一种用于分析电子电路图案缺陷的系统，包括：将结构缺陷的位置信息与电气故障的位置信息进行比较，并提取在结构缺陷和电气故障之间具有共同位置信息的证实缺陷; 基于预先存储的分类规则将提取的确证缺陷的图像分类为关键缺陷图像和非关键缺陷图像，该分类规则通过参考缺陷图像，缺陷位置信息和执行电子化的结果来定义关键和非关键缺陷测试; 通过校正显示在屏幕上的分类缺陷图像的分类来修改预先存储的分类规则; 并对每个后续对象重复操作，其中对于被检查的每个当前对象，使用关于先前对象的经修改的预先存储的分类规则作为关于本对象的操作的预先存储的分类规则。

6. 发明申请

US20130191807A1 METHOD OF EVALUATING SYSTEMATIC DEFECT, AND APPARATUS THEREFOR 有权
标题翻译：评估系统缺陷的方法及其设备
公开(公告)号：US20130191807A1
公开(公告)日：2013-07-25
申请号：US13877922
申请日：2011-09-30
申请人： Yuji Takagi , Yuichi Hamamura
发明人： Yuji Takagi , Yuichi Hamamura
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , H01L22/12 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： In order to enable an evaluation of systematic defects, a method of evaluating systematic defects was configured so as to sample a circuit pattern of a specific layer of a semiconductor device, evaluate the state of superimposition between the sampled circuit pattern and circuit patterns of layers other than the specific layer, using design data, classify the state of superimposition, calculate the ratio thereof as a reference ratio, evaluate the state of superimposition between a pattern in design data corresponding to a defect of the specific layer detected by another inspection apparatus and patterns at positions corresponding to the defects in layers other than the specific layer, classify the evaluated state of superimposition, calculate the ratio of the classification as inspection-result ratio, compare the calculated reference ratio and the calculated inspection-result ratio, and evaluate systematic defects by the comparison between the calculated reference ratio and the calculated inspection-result ratio.
摘要翻译：为了能够对系统缺陷进行评估，构造了评价系统缺陷的方法，以对半导体器件的特定层的电路图案进行采样，评估采样电路图案与其他层的电路图案之间的叠加状态比特定层使用设计数据，将叠加状态进行分类，将其比例作为参考比计算，评价与由另一检查装置检测到的特定层的缺陷相对应的设计数据中的图案之间的叠加状态在与特定层以外的层的缺陷相对应的位置，对评价的叠加状态进行分类，计算分类比作为检查结果比，比较计算出的参考比和计算出的检查结果比，并评价系统缺陷通过比较计算的参考比和计算检验结果比例。

7. 发明申请

US20120093392A1 REVIEWED DEFECT SELECTION PROCESSING METHOD, DEFECT REVIEW METHOD, REVIEWED DEFECT SELECTION PROCESSING TOOL, AND DEFECT REVIEW TOOL 有权
标题翻译：回顾缺陷选择处理方法，缺陷审查方法，回顾缺陷选择处理工具和缺陷审查工具
公开(公告)号：US20120093392A1
公开(公告)日：2012-04-19
申请号：US13266800
申请日：2010-03-25
申请人： Yuji Takagi , Minoru Harada , Yuichi Hamamura
发明人： Yuji Takagi , Minoru Harada , Yuichi Hamamura
IPC分类号： G06K9/62
CPC分类号： G01N21/9501 , G01N21/956 , G01N2021/8867 , H01L22/12 , H01L22/20
摘要： The present invention relates to semiconductor inspection and provides a technology capable of efficiently detecting a systematic defect. In the present system, with regard to the process (S7, S8) of matching hot spot (HS) points that can be simulated in advance and defect points obtained as a result of a visual inspection each other and the unmatched defect points, a process (S6, S9) of classifying the defect points into groups based on similarity of pattern layout at the defect points to determine the defects belonging to a pattern layout where defects frequently occur, thereby reliably detecting the systematic defect. Also, with a process (S11) of acquiring an uneven distribution in a defect occurrence distribution on a wafer, the systematic defect occurring due to topography of the wafer can also be detected.
摘要翻译：本发明涉及半导体检查，并且提供能够有效地检测系统缺陷的技术。在本系统中，关于可以预先模拟的热点（HS）点和作为目视检查的结果获得的缺陷点与不匹配的缺陷点的处理（S7，S8），处理（S6，S9），根据缺陷点的图案布局的相似度将缺陷点分类成组，以确定属于频繁发生缺陷的图案布局的缺陷，从而可靠地检测系统缺陷。此外，通过获取晶片上的缺陷发生分布中的不均匀分布的处理（S11），也可以检测由于晶片的形貌而发生的系统缺陷。

8. 发明授权

US06841405B2 Photomask for test wafers 失效
标题翻译：用于测试晶片的光掩模
公开(公告)号：US06841405B2
公开(公告)日：2005-01-11
申请号：US10269268
申请日：2002-10-10
申请人： Yuichi Hamamura , Takaaki Kumazawa , Hisao Asakura , Aritoshi Sugimoto , Kazuyuki Tsunokuni
发明人： Yuichi Hamamura , Takaaki Kumazawa , Hisao Asakura , Aritoshi Sugimoto , Kazuyuki Tsunokuni
IPC分类号： G01R31/28 , H01L21/00
CPC分类号： G01R31/2812 , G01R31/2818
摘要： A manufacturing method of an electronic device is to improve test efficiency using test structure and improve yield. The manufacturing method performs test using a first lead wire disposed on an insulating layer formed on a substrate and a second lead wire electrically connected to the substrate and disposed on the insulating layer and manages the electronic device on the basis of results of the test to manufacture the electronic device. The manufacturing method includes a step of testing whether the first lead wire is disconnected or not by measuring an electric resistance between both ends of the first lead wire and a step of testing whether the first and second lead wires are short-circuited or not by measuring an electric resistance between the first lead wire and the substrate.
摘要翻译：电子设备的制造方法是使用测试结构提高测试效率并提高产量。该制造方法使用设置在形成于基板上的绝缘层上的第一引线和与基板电连接并设置在绝缘层上的第二引线进行测试，并基于制造试验的结果来管理电子设备电子设备。该制造方法包括通过测量第一引线的两端之间的电阻和通过测量第一和第二引线是否短路的步骤来测试第一引线是否断开的步骤第一引线与基板之间的电阻。

9. 发明授权

US06344115B1 Pattern forming method using charged particle beam process and charged particle beam processing system 有权
标题翻译：使用带电粒子束工艺和带电粒子束处理系统的图案形成方法
公开(公告)号：US06344115B1
公开(公告)日：2002-02-05
申请号：US09417996
申请日：1999-10-13
申请人： Junzou Azuma , Akira Shimase , Yuichi Hamamura , Hidemi Koike
发明人： Junzou Azuma , Akira Shimase , Yuichi Hamamura , Hidemi Koike
IPC分类号： C23C1400
CPC分类号： H01J37/18 , C23C16/26 , H01J2237/317
摘要： A pattern forming method using an improved charged particle beam process, and a charged particle beam processing system prevent effectively the corrosion of a workpiece by a reactive gas adsorbed by and adhering to the surface of the workpiece when the workpiece is taken out into the atmosphere after pattern formation. The charged particle beam processing system comprises, as principal components, an ion beam chamber provided with an ion beam optical system, a processing chamber provided with a gas nozzle through which a reactive gas is blown against a workpiece, a load-lock chamber connected through a gate valve to the processing chamber. The load-lock chamber is capable of producing a plasma of an inert gas for processing the surface of the workpiece by sputtering. The workpiece is returned to the load-lock chamber after a pattern has been formed thereon in the processing chamber by reactive processing including irradiating the surface of the workpiece with a charged particle beam in an environment of the reactive gas, and the workpiece is subjected to a plasma process to remove the reactive gas adsorbed by the workpiece during pattern formation and adhering to the workpiece.
摘要翻译：使用改进的带电粒子束工艺的图案形成方法和带电粒子束处理系统，当工件被排出到大气中之后，通过被吸收并附着在工件表面上的反应气体有效地防止工件的腐蚀图案形成。带电粒子束处理系统作为主要部件包括设置有离子束光学系统的离子束室，设置有气体喷嘴的处理室，反应气体通过该喷嘴吹向工件，负载锁定室通过一个闸阀到处理室。负载锁定室能够产生用于通过溅射处理工件的表面的惰性气体的等离子体。在通过反应性处理在处理室中形成图案之后，工件返回到装载锁定室，包括在反应气体的环境中用带电粒子束照射工件的表面，并且对工件进行等离子体处理，以在图案形成期间去除被工件吸附的反应气体并附着到工件上。

10. 发明授权

US07945410B2 Semiconductor device yield prediction system and method 失效
标题翻译：半导体器件产量预测系统及方法
公开(公告)号：US07945410B2
公开(公告)日：2011-05-17
申请号：US11836199
申请日：2007-08-09
申请人： Natsuyo Morioka , Seiji Ishikawa , Katsumi Ikegaya , Yasunori Yamaguchi , Kazuo Ito , Yuichi Hamamura
发明人： Natsuyo Morioka , Seiji Ishikawa , Katsumi Ikegaya , Yasunori Yamaguchi , Kazuo Ito , Yuichi Hamamura
IPC分类号： G01N37/00 , G06F19/00
CPC分类号： G05B15/02 , G05B17/02
摘要： An average fault ratio is calculated from product characteristics of a product as a target of yield prediction, in order to predict yield accurately in the course of manufacturing the prediction target product.With respect to a reference product, whose wiring pattern is different from the prediction target product but manufactured by the same manufacturing process, a monthly electric fault density is calculated from actually measured data. Respective average fault ratios are obtained from product characteristics of the prediction target product and the reference product. A monthly electric fault density of the prediction target product is obtained by multiplying the monthly electric fault density of the reference product by the ratio of the average fault ratios. The yield is calculated by using the monthly electric fault density of the month in which a yield prediction target lot of the prediction target product was processed.
摘要翻译：从作为产量预测目标的产品的产品特性计算平均故障率，以便在制造预测目标产品的过程中准确地预测产量。对于其参考产品，其布线图案与预测目标产品不同但通过相同的制造工艺制造，每月电故障密度由实际测量数据计算。相应的平均故障率是从预测目标产品和参考产品的产品特性获得的。通过将参考产品的每月电气故障密度乘以平均故障率的比率来获得预测目标乘积的每月电气故障密度。通过使用处理预测目标产品的产量预测目标批次的月份的每月电气故障密度来计算产量。

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