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    • 7. 发明授权
    • Chondroitinase ABC isolated from proteus vulgaris ATCC 6896
    • 从普通寻常型ATCC 6896中分离的软骨素酶ABC
    • US5496718A
    • 1996-03-05
    • US082853
    • 1993-06-23
    • Nobukazu HashimotoHideo MochizukiAkio Hamai
    • Nobukazu HashimotoHideo MochizukiAkio Hamai
    • A61K38/43A61K38/00C12N9/16C12N9/20C12N9/88C01G17/04C12N1/12
    • C12N9/88A61K38/00G03C2001/0471Y10S435/873
    • A crystallizable, purified chondroitinase ABC having a molecular weight of about 100,000 dalton by the measurement of the SDS-polyacrylamide gel electrophoresis (SDS-PAGE) and the measurement by the gel permeation chromatography method, having alanine as the N-terminal amino acid and proline as the C-terminal amino acid. A process for the purification of the crystallizable purified chondroitinase ABC comprising removing nucleic acid from an surfactant solution extract obtained from cells of chondroitinase ABC-producing microorganisms and chromatographically treating by concentration gradient elution using a weak cation exchange resin or a strong cation exchange resin. A composition comprising a chondroitinase and serum albumin, gelatin, or a nonionic surfactant. The chondroitinase ABC is isolated from Proteus vulgaris ATCC 6896.
    • 通过SDS-聚丙烯酰胺凝胶电泳(SDS-PAGE)的测量和通过凝胶渗透色谱法测定的具有约100,000道尔顿分子量的可结晶纯化的软骨素酶ABC,其具有丙氨酸作为N-末端氨基酸和脯氨酸 作为C末端氨基酸。 一种用于纯化可结晶的纯化软骨素酶ABC的方法,包括从获自软骨素酶ABC微生物的细胞获得的表面活性剂溶液提取物中除去核酸,并使用弱阳离子交换树脂或强阳离子交换树脂进行色谱法处理。 包含软骨素酶和血清白蛋白,明胶或非离子表面活性剂的组合物。 软骨素酶ABC从普通变形杆菌ATCC 6896中分离。
    • 8. 发明授权
    • Memory interface circuit and semiconductor device
    • 存储器接口电路和半导体器件
    • US08315109B2
    • 2012-11-20
    • US13272856
    • 2011-10-13
    • Hideo Mochizuki
    • Hideo Mochizuki
    • G11C7/10
    • G11C7/10G06F13/1673G06F13/1689
    • There is a need to provide a small-sized memory interface circuit capable of adjusting timing between a strobe signal and a data signal without interrupting a normal memory access.An expected value acquisition latch latches write data in synchronization with a clock signal. A WDLL outputs a write strobe signal WDQS. An RDLL outputs a delayed write strobe signal WDQS_d. A read data latch latches looped-back write data in synchronization with the delayed write strobe signal WDQS_d. A comparator compares the read data latch with an output from the expected value acquisition latch. A register portion stores a delay value to be placed in the RDLL. A register control portion updates a delay value in the register portion in accordance with a comparison result. A delay selection portion places a delay value read from the register portion in the RDLL.
    • 需要提供能够调整选通信号和数据信号之间的定时的小型存储器接口电路,而不中断正常的存储器访问。 期望值采集锁存器与时钟信号同步地锁存写入数据。 WDLL输出写选通信号WDQS。 RDLL输出延迟的写选通信号WDQS_d。 读取数据锁存器与延迟写入选通信号WDQS_d同步地锁存环回写入数据。 比较器将读取的数据锁存器与期望值采集锁存器的输出进行比较。 寄存器部分存储要放置在RDLL中的延迟值。 寄存器控制部分根据比较结果更新寄存器部分中的延迟值。 延迟选择部分将从寄存器部分读取的延迟值放在RDLL中。